SDRAM Unbuffered SODIMM. 144pin Unbuffered SODIMM based on 256Mb J-die. 54 TSOP-II/sTSOP II with Lead-Free and Halogen-Free.

Transcription

1 Unbuffered SODIMM 144pin Unbuffered SODIMM based on 256Mb J-die 54 TSOP-II/sTSOP II with Lead-Free and Halogen-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 15

2 Table of Contents 1.0 Ordering Information Operating Frequencies Feature Pin Configuration (Front side/back side) Pin Description Pin Configuration Description Functional Block Diagram MB, 32Mx64 Module (M464S3254JLS) MB, 64Mx64 Module (M464S6453J60) Absolute Maximum Ratings DC Operating Conditions And Characteristics Capacitance(Max.) DC CHARACTERISTI M464S3254JLS (32M x 64, 256MB Module) M464S6453J60 (64M x64, 512MB Module) AC Operating Test Conditions OPERATING AC PARAMETER AC CHARACTERISTI SIMPLIFIED TRUTH TABLE PHYSICAL DIMENSIONS Mx64 (M464S3254JLS) Mx64 (M464S6453J60) of 15

3 Revision History Revision Month Year History 1.0 November Initial Release 1.1 August Changed module part number 3 of 15

4 144Pin Unbuffered SODIMM based on 256Mb J-die (x8, x16) 1.0 Ordering Information Part Number Density Organization Component Composition Component Package Height M464S3254JLS-C(L)7A 256MB 32M x 64 16M x 16 (K4S561632J) * 8EA 54-TSOP(II) 1,250mil M464S6453J60-C(L)7A 512MB 64M x 64 32M x 8 (K4S560832J) * 16EA 54-sTSOP(II) 1,250mil Note: 1. L and 6 of Part number(11th digit) stand for Lead-Free, Halogen-Free, and RoHS compliant products. 2.0 Operating Frequencies 7A Maximum Clock Frequency 133MHz(7.5ns) 100MHz(10ns) CL-tRCD-tRP Feature Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V ± 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8) Data scramble (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Serial presence detect with EEPROM 54pin TSOP II & stsop II Lead-Free and Halogen Free package All of products are Lead-Free and Halogen-Free, and RoHS compliant 4 of 15

5 4.0 Pin Configuration (Front side/back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 V SS 2 V SS V SS 56 V SS NC 58 NC 101 V DD 102 V DD NC 60 NC 103 A6 104 A7 11 V DD 12 V DD 105 A8 106 BA Voltage Key 107 V SS 108 VSS A9 110 BA **CLK0 62 **CKE0 111 A10/AP 112 A V DD 64 V DD 113 V DD 114 V DD 21 V SS 22 V SS 65 RAS 66 CAS WE 68 **CKE **0 70 A V SS 120 V SS 27 V DD 28 V DD 71 **1 72 *A A0 30 A3 73 DU 74 **CLK A1 32 A4 75 V SS 76 V SS A2 34 A5 77 NC 78 NC V SS 36 V SS 79 NC 80 NC 129 V DD 130 V DD V DD 82 V DD V DD 46 V DD V SS 140 V SS V SS 92 V SS 141 SDA 142 SCL V DD 144 V DD Note : Permanent device damage may occur if "ABSOLUTE MAIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 5.0 Pin Description Pin Name Function Pin Name Function A0 ~ A12 Address input (Multiplexed) WE Write enable BA0 ~ BA1 Select bank 0 ~ 7 ~ 3 Data input/output V DD Power supply (3.3V) CLK0, CLK1 Clock input V SS Ground CKE0, CKE1 Clock enable input SDA Serial data I/O 0, 1 Chip select input SCL Serial clock RAS Row address strobe DU Don t use CAS Colume address strobe NC No connection 5 of 15

6 6.0 Pin Configuration Description Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Column address : (x16 : CA0 ~ CA9) BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. 0 ~ 7 Data input/output mask Makes data output Hi-Z, tshz after the clock and masks the output. Blocks data input when active. (Byte masking) ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic. 6 of 15

7 7.0 Functional Block Diagram MB, 32Mx64 Module (M464S3254JLS) (Populated as 2 bank of x16 Module) L U U0 L U U L U U2 L U L L L L U U1 U U5 U U3 U U6 U7 A0 ~ A12, BA0 & 1 U0 ~ U7 RAS CAS WE U0 ~ U7 U0 ~ U7 U0 ~ U7 SCL 47KΩ WP SA0 Serial PD SA1 SA2 SDA CKE0 U0 ~ U3 CKE1 DQn 10Ω U4 ~ U7 Every DQ pin of U0/U4 V DD V SS Three 0.1 uf 7R 0603 Capacitors per each To all s CLK0/1 U1/U5 U2/U6 U3/U7 7 of 15

8 MB, 64Mx64 Module (M464S6453J60) (Populated as 2 bank of x8 Module) U0 U U U4 U U2 U U U3 U U6 U7 U12 U13 U14 U15 A0 ~ A12, BA0 & 1 RAS U0 ~ U15 U0 ~ U15 SCL 47KΩ WP SA0 Serial PD SA1 SA2 SDA CAS U0 ~ U15 WE U0 ~ U15 V DD V SS CKE0 DQn 10Ω U0 ~ U7 Two 0.1uF Capacitors per each CKE1 Every DQpin of To all s U8 ~ U15 CLK0 CLK1 U0/U1/U4/U5 U8/U9/U12/U13 U2/U3/U6/U7 U10/U11/U14/U15 8 of 15

9 8.0 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS V IN, V OUT -1.0 ~ 4.6 V Voltage on V DD supply relative to V SS V DD, V DDQ -1.0 ~ 4.6 V Storage temperature T STG -55 ~ +150 C Power dissipation P D 1.0 * # of component W Short circuit current I OS 50 ma Note : Permanent device damage may occur if ABSOLUTE MAIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 9.0 DC Operating Conditions And Characteristics Recommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage V DD V Input high voltage V IH V DDQ +0.3 V 1 Input low voltage V IL V 2 Output high voltage V OH V I OH = -2mA Output low voltage V OL V I OL = 2mA Input leakage current I LI ua 3 Note : 1. V IH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. V IL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V V IN V DDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs Capacitance(Max.) (V DD = 3.3V, T A = 23 C, f = 1MHz, V REF = 1.4V ± 200 mv) Parameter Symbol M464S3254JLS M464S6453J60 Min Max Min Max Unit Input capacitance (A0 ~ A12, BA0 ~ BA1) Input capacitance (RAS, CAS, WE) Input capacitance (CKE0 ~ CKE1) Input capacitance (CLK0 ~ CLK1) Input capacitance (0 ~ 1) Input capacitance (0 ~ 7) Data input/output capacitance ( ~ 3) CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT pf pf pf pf pf pf pf 9 of 15

10 11.0 DC CHARACTERISTI 11.1 M464S3254JLS (32M x 64, 256MB Module) (Recommended operating condition unless otherwise noted, TA = 0 to 70 C) Parameter Symbol Test Condition Version 7A Unit Note Operating current (One bank active) ICC1 Burst length = 1, trc trc(min), IO = 0 ma 392 ma 1 Precharge standby current in ICC2P CKE V IL (max), tcc = 10ns 16 power-down mode ICC2PS CKE & CLK V IL (max), tcc = 16 ma ICC2N IH (min), V IH (min), tcc = 10ns Precharge standby current in Input signals are changed one time during 20ns 120 non power-down mode ICC2NS IH (min), CLK V IL (max), tcc = Input signals are stable 80 ma Active standby current in ICC3P CKE V IL (max), tcc = 10ns 40 power-down mode ICC3PS CKE & CLK V IL (max), tcc = 40 ma Active standby current in ICC3N IH (min), V IH (min), tcc = 10ns 224 ma Input signals are changed one time during 20ns non power-down mode (One bank active) ICC3NS IH (min), CLK V IL (max), tcc = 160 ma Input signals are stable Operating current IO = 0 ma, ICC4 (Burst mode) Page burst 4Banks activated tccd = 2CLKs 552 ma 1 Refresh current ICC5 trc trc(min) 752 ma 2 Self refresh current ICC6 CKE 0.2V C 24 ma L 12 ma 11.2 M464S6453J60 (64M x64, 512MB Module) Note : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(V IH /V IL =V DDQ /V SSQ ) (Recommended operating condition unless otherwise noted, TA = 0 to 70 C) Parameter Symbol Test Condition Version 7A Unit Note Operating current (One bank active) ICC1 Burst length = 1, trc trc(min), IO = 0 ma 784 ma 1 Precharge standby current in ICC2P CKE V IL (max), tcc = 10ns 32 power-down mode ICC2PS CKE & CLK V IL (max), tcc = 32 ma ICC2N IH (min), V IH (min), tcc = 10ns Precharge standby current in Input signals are changed one time during 20ns 240 non power-down mode ICC2NS IH (min), CLK V IL (max), tcc = Input signals are stable 160 ma Active standby current in ICC3P CKE V IL (max), tcc = 10ns 80 power-down mode ICC3PS CKE & CLK V IL (max), tcc = 80 ma Active standby current in ICC3N IH (min), V IH (min), tcc = 10ns 448 ma Input signals are changed one time during 20ns non power-down mode (One bank active) ICC3NS IH (min), CLK V IL (max), tcc = 320 ma Input signals are stable Operating current IO = 0 ma, ICC4 (Burst mode) Page burst 4Banks activated tccd = 2CLKs 1,104 ma 1 Refresh current ICC5 trc trc(min) 1,504 ma 2 Self refresh current ICC6 CKE 0.2V C 48 ma L 24 ma 10 of 15

11 12.0 AC Operating Test Conditions (V DD = 3.3V ± 0.3V, T A = 0 to 70 C) Parameter Value Unit AC input levels (V IH /V IL ) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig V V TT = 1.4V 1200Ω 50Ω Output V OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mA Output Z0 = 50Ω 870Ω 50pF 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit 13.0 OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Symbol Version 7A Unit Note Row active to row active delay trrd(min) 15 ns 1 RAS to CAS delay trcd(min) 20 ns 1 Row precharge time trp(min) 20 ns 1 Row active time tras(min) 45 ns 1 tras(max) 100 us Row cycle time trc(min) 65 ns 1 Last data in to row precharge trdl(min) 2 CLK 2 Last data in to Active delay tdal(min) 2 CLK + trp - Last data in to new col. address delay tcdl(min) 1 CLK 2 Last data in to burst stop tbdl(min) 1 CLK 2 Col. address to col. address delay tccd(min) 1 CLK 3 Number of valid output data CAS latency=3 2 CAS latency=2 1 ea 4 Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 11 of 15

12 14.0 AC CHARACTERISTI REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE. Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. (AC operating conditions unless otherwise noted) Parameter Symbol 7A Min Max Unit Note CLK cycle CAS latency=3 7.5 tcc time CAS latency= ns 1 CLK to valid CAS latency=3-5.4 tsac output delay CAS latency=2-6 ns 1,2 Output data CAS latency=3 3 - toh hold time CAS latency=2 3 - ns 2 CLK high pulse width tch ns 3 CLK low pulse width tcl ns 3 Input setup time tss ns 3 Input hold time tsh ns 3 CLK to output in Low-Z tslz 1 - ns 2 CLK to output CAS latency=3-5.4 tshz in Hi-Z CAS latency=2-6 ns 12 of 15

13 15.0 SIMPLIFIED TRUTH TABLE (V=Valid, =Don t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn RAS CAS WE BA0,1 A10/AP Note : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at trp after the end of burst. 6. Burst stop command is valid at every burst length. 7. sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read latency is 2) A0 ~ A9, A11, A12 Register Mode register set H L L L L OP code 1,2 Auto refresh H 3 H L L L H Entry L 3 Refresh Self L H H H 3 refresh Exit L H H 3 Bank active & row addr. H L L H H V Row address Read & Auto precharge disable L Column 4 column address H L H L H V address Auto precharge enable H 4,5 Write & Auto precharge disable L Column 4 column address H L H L L V address Auto precharge enable H 4,5 Burst stop H L H H L 6 Bank selection V L Precharge H L L H L All banks H H Clock suspend or Entry H L L V V V active power down Exit L H H Entry H L L H H H Precharge power down mode H Exit L H L V V V H V 7 H No operation command H L H H H Note 13 of 15

14 16.0 PHYSICAL DIMENSIONS Mx64 (M464S3254JLS) Units : Inches (Millimeters) 0.16 ± (4.00 ± 0.10) 0.24 (6.0) 2.66 (67.60) 2.50 (63.60) (20.00) 1.25 (31.75) 2-R Min (2.00 Min) 0.13 (3.30) 0.91 (23.20) 0.10 (2.50) 0.18 (4.60) (2.10) 1.29 (32.80) 2-φ 0.07 (1.80) 0.15 (3.70) Z Y Min (3.20 Min) Max (3.80 Max) Min (4.00 Min) 0.16 ± (4.00 ± 0.10) Min (2.55 Min) ± (0.600 ± 0.050) ±0.006 (0.200 ±0.150) 0.04 ± (1.00 ± 0.10) Detail Z 0.06 ± (1.50 ± 0.1) 0.03 TYP (0.80 TYP) Detail Y Tolerances : ±.006(.15) unless otherwise specified The used device is 16Mx16, TSOPII Part No. : K4S561632J 14 of 15

15 Mx64 (M464S6453J60) Units : Inches (Millimeters) 0.16 ± (4.00 ± 0.10) 0.24 (6.0) 2.66 (67.60) 2.50 (63.60) (20.00) 1.25 (31.75) 2-R Min (2.00 Min) 0.13 (3.30) 0.91 (23.20) 0.10 (2.50) 0.18 (4.60) (2.10) 1.29 (32.80) 2-φ 0.07 (1.80) 0.15 (3.70) Z Y Min (3.20 Min) Max (3.80 Max) Min (4.00 Min) 0.16 ± (4.00 ± 0.10) Min (2.55 Min) ± (0.600 ± 0.050) ±0.006 (0.200 ±0.150) 0.04 ± (1.00 ± 0.10) Detail Z 0.06 ± (1.50 ± 0.1) 0.03 TYP (0.80 TYP) Detail Y Tolerances : ±.006(.15) unless otherwise specified The used device is 32Mx8, stsop Part No. : K4S560832J 15 of 15