ISSI. 256 Mb Synchronous DRAM. IS42S83200A (4-bank x 8,388,608 - word x 8-bit) IS42S16160A (4-bank x 4,194,304 - word x 16-bit) DESCRIPTION FEATURES

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1 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) 256 Mb Synchronous DRAM DESCRIPTION IS42S832A is a synchronous 256Mb SDRAM and is organized as 4-bank x 8,388,68-word x 8-bit; and IS42S66A is organized as 4-bank x 4,94,34-word x 6-bit. All inputs and outputs are referencedto the rising edge of. IS42S832A and IS42S66A achieve very high speed clock rates up to 66MHz, and are suitable for main memories or graphic memories in computer systems. FEATURES ITEM - Single 3.3V ±.3V power supply - Max. Clock frequency: -6:66MHz<3-3-3> -7:43MHz<3-3-3> -75:33MHz<3-3-3> - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA,BA(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- /2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- ML and MU (IS42S66A) - Random column access - Auto precharge / All bank precharge controlled by A - Auto and self refresh refresh cycles /64ms(4 banks concurrent refresh) - LVTTL Interface - Row address A-2 /Column address A-9(x8) / A-8(x6) - Package: 4-mil, 54-pin Thin Small Outline (TSOP II) with.8mm lead pitch - Lead-free available Unit CL=2 - - ns t Clock Cycle Time (Min.) CL= ns tras Active to Precharge Period (Min.) ns Row to Column Delay (Min.) ns CL= ns tac Access Time from (Max.) CL= ns trc Ref /Active Period (Min.) ns Icc Operation Current (Single Bank) (Max.) IS42S832A/66A - - IS42S832A ma IS42S66A 3 3 ma Icc6 Self Refresh Current (Max.) -6,-7, ma - Integrated Silicon Solution, Inc //5

2 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) PIN CONFIGURATION (TOP VIEW) x8 x6 Vdd Vdd 54 Vss Vss VddQ VddQ 3 52 VssQ VssQ NC NC VssQ VssQ 6 49 VddQ VddQ NC NC VddQ VddQ 9 46 VssQ VssQ NC 5 45 NC VssQ VssQ 2 43 VddQ VddQ NC NC Vdd Vdd 4 4 Vss Vss NC ML 5 4 NC NC /WE /WE 6 39 MU M /CAS /CAS 7 38 /RAS /RAS 8 37 /CS /CS 9 36 A2 A2 BA BA 2 35 A A BA BA 2 34 A9 A9 A/AP A/AP A8 A8 A A A7 A7 A A 24 3 A6 A6 A2 A A5 A5 A3 A A4 A4 Vdd Vdd Vss Vss 4mil x 875mil 54pin.8mm pitch TSOP(II) : Master Clock M, MU/L : Output Disable / Write Mask : Clock Enable A-2 : Address Input /CS : Chip Select BA, : Bank Address Input /RAS : Row Address Strobe Vdd : Power Supply /CAS : Column Address Strobe VddQ : Power Supply for Output /WE : Write Enable Vss : Ground -5 : Data I/O VssQ : Ground for Output 2 Integrated Silicon Solution, Inc //5

3 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) BLOCK DIAGRAM -7 I/O Buffer Memory Array 892x24x8 Cell Array Bank # Memory Array Memory Array Memory Array 892x24x8 892x24x8 892x24x8 Cell Array Cell Array Cell Array Bank # Bank #2 Bank #3 Mode Register Control Circuitry Address Buffer Control Signal Buffer Clock Buffer A-2 BA, /CS /RAS /CAS /WE M Note:This figure shows the IS42S832A The IS42S66A configuration is 892x52x6 of cell array and -5 Integrated Silicon Solution, Inc //5

4 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) PIN FUNCTION Input Master Clock: All other inputs are referenced to the rising edge of Input Clock Enable: controls internal clock.when is low, internal clock for the following cycle is ceased. is also used to select auto / self-refresh. After self-refresh mode is started, becomes asynchronous input. Self-refresh is maintained as long as is low. /CS Input Chip Select: When /CS is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. A-2 Input A-2 specify the Row / Column Address in conjunction with BA,. The Row Address is specified by A-2. The Column Address is specified by A-9(x8)/A-8(x6). A is also used to indicate precharge option. When A is high at a read / write command, an auto precharge is performed. When A is high at a precharge command, all banks are precharged. BA, Input Bank Address: BA, specifies one of four banks to which a command is applied. BA, must be set with ACT, PRE,, WRITE commands. -7(x8), -5(x6) Input / Output Data In and Data out are referenced to the rising edge of. M(x8), MU/L(x6) Input Din Mask / Output Disable: When M(U/L) is high in burst write, Din for the current cycle is masked. When M(U/L) is high in burst read, Dout is disabled at the next but one cycle. Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only. 4 Integrated Silicon Solution, Inc //5

5 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) BASIC FUNCTIONS The IS42S832A/66A provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at rising edge. In addition to 3 signals, /CS, and A are used as chip select, refresh opt ion, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. /CS /RAS Chip Select : L=select, H=deselect /CAS define basic command /WE A Refresh refresh command Precharge precharge or read/write command Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read () [/RAS =H, /CAS =L, /WE =H] command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A =H at this command, the bank is deactivated after the burst read (auto-precharge, A). Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A =H at this command, all banks are deactivated (precharge all, PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE = =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. Integrated Silicon Solution, Inc //5

6 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) COMMAND TRUTH TABLE COMMAND MNEMONIC n- n /CS /RAS /CAS /WE BA, Deselect DESEL H H No Operation NOP H L H H H Row Address Entry & Bank Activate ACT H L L H H V V V Single Bank Precharge PRE H L L H L V L Precharge All Banks PREA H L L H L H Column Address Entry & Write WRITE H L H L L V L V Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge A /AP A-9, -2 WRITEA H L H L L V H V H L H L H V L V A H L H L H V H V Auto-Refresh REFA H H L L L H Self-Refresh Entry REFS H L L L L H Self-Refresh Exit REFS L H H L H L H H H Burst Terminate TBST H L H H L Mode Register Set MRS H L L L L L L V H=High Level, L=Low Level, V=Valid, =Don't Care, n= cycle number NOTE:. A7-9,-2=L, A-A6 =Mode Address note 6 Integrated Silicon Solution, Inc //5

7 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) FUNCTION TRUTH TABLE Current State /CS /RAS /CAS /WE Address Action H DESEL NOP L H H H NOP NOP L H H L TBST ILLEGAL*2 IDLE L H L BA, CA, A / WRITE ILLEGAL*2 L L H H BA, RA ACT Bank Active, Latch RA L L H L BA, A PRE / PREA NOP*4 L L L H REFA Auto-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 ROW ACTIVE H DESEL NOP L H H H NOP NOP L H H L TBST NOP L H L H BA, CA, A Begin Read, Latch CA, / A Determine Auto-Precharge L H L L BA, CA, A WRITE / Begin Write, Latch CA, WRITEA Determine Auto-Precharge L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA Precharge / Precharge All L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H DESEL NOP (Continue Burst to END) L H H H NOP NOP (Continue Burst to END) L H H L TBST Terminate Burst Terminate Burst, Latch CA, L H L H BA, CA, A / A Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A Terminate Burst, Latch CA, WRITE / Begin Write, Determine Auto- WRITEA Precharge*3 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA Terminate Burst, Precharge L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Integrated Silicon Solution, Inc //5

8 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Action WRITE H DESEL NOP (Continue Burst to END) L H H H NOP NOP (Continue Burst to END) L H H L TBST Terminate Burst L H L H BA, CA, A / A L H L L BA, CA, A WRITE / WRITEA Terminate Burst, Latch CA, Begin Read, Determine Auto- Precharge*3 Terminate Burst, Latch CA, Begin Write, Determine Auto- Precharge*3 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA Terminate Burst, Precharge L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H DESEL NOP (Continue Burst to END) with AUTO PRECHARGE WRITE with AUTO PRECHARGE L H H H NOP NOP (Continue Burst to END) L H H L TBST ILLEGAL L H L H BA, CA, A / A ILLEGAL L H L L BA, CA, A WRITE / WRITEA ILLEGAL L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA ILLEGAL*2 L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H DESEL NOP (Continue Burst to END) L H H H NOP NOP (Continue Burst to END) L H H L TBST ILLEGAL L H L H BA, CA, A / A ILLEGAL WRITE / L H L L BA, CA, A ILLEGAL WRITEA L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A PRE / PREA ILLEGAL*2 L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL 8 Integrated Silicon Solution, Inc //5

9 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Action H DESEL NOP (Idle after trp) L H H H NOP NOP (Idle after trp) L H H L TBST ILLEGAL*2 PRE - CHARGING L H L BA, CA, A / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A PRE / PREA NOP*4 (Idle after trp) L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H DESEL NOP (Row Active after ) L H H H NOP NOP (Row Active after ) ROW ACTIVATING L H H L TBST ILLEGAL*2 L H L BA, CA, A / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A PRE / PREA ILLEGAL*2 L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H DESEL NOP L H H H NOP NOP L H H L TBST ILLEGAL*2 WRITE RE- COVERING L H L BA, CA, A / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A PRE / PREA ILLEGAL*2 L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Integrated Silicon Solution, Inc //5

10 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Action H DESEL NOP (Idle after trc) RE- FRESHING MODE REGISTER SETTING L H H H NOP NOP (Idle after trc) L H H L TBST ILLEGAL L H L BA, CA, A / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A PRE / PREA ILLEGAL L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H DESEL NOP (Idle after trsc) L H H H NOP NOP (Idle after trsc) L H H L TBST ILLEGAL L H L BA, CA, A / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A PRE / PREA ILLEGAL L L L H REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, =Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES:. All entries assume that was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. Integrated Silicon Solution, Inc //5

11 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) FUNCTION TRUTH TABLE (continued) Current State SELF- REFRESH* POWER DOWN ALL BANKS IDLE*2 AN STATE other than listed above n- n /CS /RAS /CAS /WE Add Action H INVALID L H H Exit Self-Refresh (Idle after trc) L H L H H H Exit Self-Refresh (Idle after trc) L H L H H L ILLEGAL L H L H L ILLEGAL L H L L ILLEGAL L L NOP (Maintain Self-Refresh) H INVALID L H Exit Power Down to Idle L L NOP (Maintain Power Down) H H Refer to Function Truth Table H L L L L H Enter Self-Refresh H L H Enter Power Down H L L H H H Enter Power Down H L L H H L ILLEGAL H L L H L ILLEGAL H L L L ILLEGAL L Refer to Current State =Power Down H H Refer to Function Truth Table H L Begin Suspend at Next Cycle*3 L H Exit Suspend at Next Cycle*3 L L Maintain Suspend ABBREVIATIONS: H=High Level, L=Low Level, =Don't Care NOTES:. Low to High transition will re-enable and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EIT. 2. Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. Integrated Silicon Solution, Inc //5

12 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) SIMPLIFIED STATE DIAGRAM SELF REFRESH REFS REFS MODE REGISTER SET MRS IDLE REFA AUTO REFRESH L SUSPEND L ACT H POWER DOWN H TERM WRITE ROW ACTIVE TERM WRITE SUSPEND L H WRITE WRITEA WRITE A L H SUSPEND WRITEA A WRITEA A WRITEA SUSPEND L H WRITEA PRE PRE PRE A L H A SUSPEND POWER APPLIED POWER ON PRE PRE CHARGE Automatic Sequence Sequence 2 Integrated Silicon Solution, Inc //5

13 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning.. Apply power and start clock. Attempt to maintain high, M high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 2µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After trsc from a MRS command, the SDRAM is ready for new command. /CS /RAS /CAS /WE BA, A2-A V BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A SW LTMODE BT BL SW Burst Write Single Write BL BT= BT= LATENC MODE CL /CAS LATENC R R 2 3 R R R R BURST LENGTH BURST TPE R R R Full Page SEQUENTIAL INTERLEAVED R R R R R: Reserved for Future Use Integrated Silicon Solution, Inc //5

14 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Address Read Write Q Q Q2 Q3 D D D2 D3 CL= 3 BL= 4 /CAS Latency Burst Length Burst Type Burst Length Initial Address BL Column Addressing A2 A A Sequential Interleaved Integrated Silicon Solution, Inc //5

15 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) OPERATIONAL DESCRIPTION BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA,). A row is indicated by the row addresses A-2. The minimum activation interval between one bank and the other bank is trrd.multiple banks can be active state concurrently by issuing multiple ACT commands. PRECHARGE The PRE command deactivates the bank indicated by BA,. When multiple banks are active, the precharge all command (PREA, PRE + A=H) is available to deactivate them at the same time. After trp from the precharge, an ACT command to the same bank can be issued.ba- are DON T CARE in this case. After from the bank activation, a command can be issued. st output data is available after the /CAS Latency from the, followed by (BL -) consecutive data when the Burst Length is BL. The start address is specified by A-9(8), A-8(6), and the address sequence of burst data is defined by the Burst Type. A command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. When A is high at a command, the auto-precharge (A) is performed. Any command (, WRITE, PRE, TBST, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after A. The next ACT command can be issued after (BL + trp) from the previous A. In any case, +BL trasmin must be met. Bank Activation and Precharge All (BL=4, CL=3) ACT ACT PRE ACT trrd trp A-9,-2 a b b a A a b a BA- Qb Qb Qb2 Qb3 Precharge All Integrated Silicon Solution, Inc //5

16 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Multi Bank Interleaving Read (CL=2, BL=4) A-9,-2 ACT ACT PRE ACT trp a a b b a A a b a BA- Qa Qa Qa2 Qa3 Qb Qb Qb2 Qb3 Read with Auto-Precharge (CL=2, BL=4) ACT ACT BL trp A-9,-2 a a a A a a BA- Qa Qa Qa2 Qa3 internal precharge starts Auto-Precharge Timing (, BL=4) ACT ACT BL CL=2 Qa Qa Qa2 Qa3 CL=3 Qa Qa Qa2 Qa3 internal precharge starts 6 Integrated Silicon Solution, Inc //5

17 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) WRITE A WRITE command can be issued to any active bank. The start address is specified by A-9(x8), A-8(x6). st input data is set at the same cycle as the WRITE. The consecutive data length to be write is defined by the Burst Length. The address sequence of burst data is defined by Burst Type. Minmum delay time of a WRITE command after an ACT command to the same bank is. From the last input data to the PRE command, the write recovery time (twr) is required. When A is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (,WRITE,PRE,ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at twr after the last input data cycle. The next ACT command can be issued after (BL+tWR-+tRP) from the previous WRITEA. In any case, +BL+tWR- trasmin must be met. Write (BL=4) A-9,-2 ACT Write PRE ACT BL trp a a a A a a BA- twr Da Da Da2 Da3 Write with Auto-Precharge (BL=4) ACT Write ACT BL trp A-9,-2 a a a A a a BA- twr Da Da Da2 Da3 internal precharge starts Integrated Silicon Solution, Inc //5

18 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed to interval is minimum.. Read interrupted by Read (CL=2, BL=4) A-9,-2 a b c A BA- Qa Qa Qa2 Qb Qc Qc Qc2 Qc3 [ Read Interrupted by Write ] Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the should be controlled adequately by using the M to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. Read interrupted by Write (CL=2, BL=4) ACT Write A-9,-2 a a a A a BA- M Qa Da Da Da2 Da3 Output disable by M by WRITE 8 Integrated Silicon Solution, Inc //5

19 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank. to PRE interval is minimum. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. Read interrupted by Precharge (BL=4) PRE Q Q Q2 PRE CL=2 Q Q PRE Q PRE Q Q Q2 PRE CL=3 Q Q PRE Q Integrated Silicon Solution, Inc //5

20 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) [Read Interrupted by Burst Terminate] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. to TBST interval is minimum. A TBST command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Terminate (BL=4) TBST Q Q Q2 TBST CL=2 Q Q TBST Q TBST Q Q Q2 TBST CL=3 Q Q TBST Q 2 Integrated Silicon Solution, Inc //5

21 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum. Write interrupted by Write (BL=4) Write Write Write A-9,-2 a b c A BA- Da Da Da2 Db Dc Dc Dc2 Dc3 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to interval is minimum. The input data on at the interrupting cycle is "don't care". Write interrupted by Read (CL=2, BL=4) ACT Write A-9,-2 a a b A a BA- Da Da Qb Qb Qb2 Qb3 don't care Integrated Silicon Solution, Inc //5

22 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank.write recovery time(twr) is required from the last data to PRE command. During write recovery, data inputs must be masked by M. Write interrupted by Precharge (BL=4) ACT Write PRE ACT trp A-9,-2 a a a A BA- M twr Da Da [Write Interrupted by Burst Terminate] Burst terminate command can terminate burst write operation.in this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum. Write interrupted by Terminate (BL=4) ACT Write TBST Write A-9,-2 a a b A BA- Da Da Db Db Db2 Db3 22 Integrated Silicon Solution, Inc //5

23 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) [Write with Auto-Precharge Interrupted by Write or Read to another Bank] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after(bl+twr-+ trp) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. WRITEA interrupted by WRITE to another bank (BL=4) Write Write ACT BL trp A-9,-2 a b a twr A a BA- Da Da Db Db Db2 Db3 auto-precharge interrupted activate WRITEA interrupted by to another bank (CL=2, BL=4) Write Read ACT BL trp A-9,-2 a b a twr A a BA- Da Da Qb Qb Qb2 Qb3 auto-precharge interrupted activate Integrated Silicon Solution, Inc //5

24 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) [Read with Auto-Precharge Interrupted by Read to another Bank] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after (BL+tRP) from the A. Auto-precharge interruption by a command to the same bank is inhibited. A interrupted by to another bank (CL=2, BL=4) Read Read ACT BL trp A-9,-2 a b a A a BA- Qa Qa Qb Qb Qb2 Qb3 auto-precharge interrupted activate [Full Page Burst] Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal. [Single Write] When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-). 24 Integrated Silicon Solution, Inc //5

25 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /= H) command. The refresh address is generated internally. 892 REFA cycles within 64ms refresh 256M bit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to autorefresh interval is minimum trfc. Any command must not be supplied to the device before trfc from the REFA command. Auto-Refresh /CS /RAS NOP or DESELECT /CAS /WE minimum trfc A-2 BA- Auto Refresh on All Banks Auto Refresh on All Banks Integrated Silicon Solution, Inc //5

26 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, = L). Once the self-refresh is initiated, it is maintained as long as is kept low. During the self-refresh mode, is asynchronous and the only enabled input. All other inputs including are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable inputs, asserting DESEL or NOP command and then asserting =H. After trfc from the st egde following =H, all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh /CS Stable NOP /RAS /CAS /WE A-2 new command BA- Self Refresh Entry Self Refresh Exit minimum trfc for recovery 26 Integrated Silicon Solution, Inc //5

27 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) SUSPEND controls the internal at the following cycle. Figure below shows how works. By negating, the next internal is suspended. The purpose of suspend is power down, output suspend or input suspend. is a synchronous input except during the self-refresh mode. suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. ext. tih tis tih tis int. Power Down by Standby Power Down PRE NOP NOP NOP Active Power Down ACT NOP NOP NOP Suspend by Write Read D D D2 D3 Q Q Q2 Q3 Integrated Silicon Solution, Inc //5

28 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) M CONTROL M is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, M(U,L) masks input data word by word. M(U,L) to write mask latency is. During reads, M(U,L) forces output to Hi-Z word by word. M(U,L) to output Hi-Z latency is 2. M Function Write Read MU/L D D2 D3 Q Q Q3 masked by MU/L=H disabled by MU/L=H 28 Integrated Silicon Solution, Inc //5

29 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) ABSOLUTE MAIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vdd Supply Voltage with respect to Vss V VddQ Supply Voltage for Output with respect to VssQ V VI Input Voltage with respect to Vss V VO Output Voltage with respect to VssQ V IO Output Current 5 ma Pd Power Dissipation Ta = 25 C mw Topr Operating Temperature - 7 C Tstg Storage Temperature C RECOMMENDED OPERATING CONDITIONS (Ta= - 7 C,unless otherwise noted) Symbol Parameter Limits Min. Typ. Max. Unit Vdd Supply Voltage V Vss Supply Voltage V VddQ Supply Voltage for output V VssQ Supply Voltage for output V VIH* High-Level Input Voltage all inputs 2. VddQ +.3 V VIL*2 Low-level Input Voltage all inputs V CAPACITANCE (Ta= -7 C,Vdd=VddQ=3.3±.3V,Vss=VssQ=V,unless otherwise noted) Symbol Parameter Test Condition Limits (min.) Limits (max.) -6 /-7-75 Unit CI(A) Input Capacitance, address MHz pf CI(C) Input Capacitance, contorl pin.4v bias pf CI(K) Input Capacitance, pin 2mV swing Vcc=3.3V pf CI/O Input Capacitance, I/O pin pf Integrated Silicon Solution, Inc //5

30 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) AVERAGE SUPPL CURRENT from Vdd (Ta= - 7 C, Vdd=VddQ=3.3±.3V,Vss=VssQ=V, unless otherwise noted) ITEM Symbol Organization Limits (max.) Unit Note Operating current Icc x8 - - ma trc=min, t=min BL=,IOL=mA x ma Precharge Standby current in Non-Power down mode Precharge Standby current in Power down mode Active Standby current Icc2N Icc2NS Icc2P Icc2PS Icc3N Icc3NS =VILmax t=5ns =VIHmin =VILmax(fixed) =VIHmin t=5ns(note) =VIHmin t=vilmax(fixed) =/CS=VIHmin t=5ns(note) =VIHmin t=vilmax(fixed) x8/x ma 2,3 x8/x ma 2,4 x8/x ma 2 x8/x ma x8/x ma 3,5 x8/x ma 4,5 Burst current Icc4 All Bank Active t = min BL=4, CL=3, IOL=mA x ma x ma 5 Auto-refresh current Icc5 trc=min, t=min x8/x ma Self-refresh current Icc6 <.2V x8/x6-6,-7, ma NOTE:.address are changed 3 times during trc, only bank is active & all other banks are idle 2.all banks are idle 3.input signals are changed one time during 3x t 4.input signals are stable 5.all banks are active AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta= - 7 C, Vdd=VddQ=3.3±.3V,Vss=VssQ=V, unless otherwise noted) Symbol Parameter Test Conditions Limits Min. Max. unit VOH (DC) High-Level Output Voltage (DC) IOH=-2mA V VOL (DC) Low-level Output Voltage (DC) IOL= 2mA -.4 V IOZ Off-state Output Current Q floating VO= -- VddQ - µa I I Input Current VIH = -- VddQ +.3V - µa 3 Integrated Silicon Solution, Inc //5

31 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) AC TIMING REQUIREMENTS (Ta= - 7 C, Vdd=VddQ=3.3±.3V,Vss=VssQ=V, unless otherwise noted) Input Pulse Levels:.8V-2.V Input Timing Measurement Level:.4V Symbol Parameter t cycle time CL=2 Limits Min. Max. Min. Max. Min. Max. - - Unit ns CL= ns tch High pulse width ns tcl Low pulse width tt Transition time of tis Input Setup time (all inputs) tih Input Hold time (all inputs) trc Row Cycle time trfc Refresh Cycle Time Row to Column Delay tras Row Active time trp Row Precharge time twr Write Recovery time trrd Act to Act Delay time trsc Mode Register Set Cycle time tref Refresh Interval time ns.8.8 ns ns ns ns 7 75 ns 2 2 ns 2K 45 2K 45 2K ns 2 2 ns 4 5 ns 4 5 ns 4 5 ns us.4v.4v Any AC timing is referenced to the input signal passing through.4v. Integrated Silicon Solution, Inc //5

32 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) SWITCHING CHARACTERISTICS (Ta= - 7 C, Vdd=VddQ=3.3±.3V,Vss=VssQ=V, unless otherwise noted) Limits Symbol Parameter Unit Note Min. Max. Min. Max. Min. Max. tac Access time from CL=2 6 ns CL= ns toh tolz tohz Output Hold time from CL=2 3 ns CL= ns Delay time, output lowimpedance from ns Delay time, output highimpedance from ns * NOTE:. If clock rising time is longer than ns,(tr/2-.5ns) should be added to the parameter. Output Load Condition V OUT.4V 5pF.4V Output Timing Measurement Reference Point.4V tolz.4v tac toh tohz 32 Integrated Silicon Solution, Inc //5

33 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Burst Write (Single Bank) [BL=4] /CS /RAS tras trc trp /CAS twr twr /WE M A-9, A A2 BA, D D D D D D D D ACT# WRITE# PRE# ACT# WRITE# PRE# Italic paramater shows minimum case Integrated Silicon Solution, Inc //5

34 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Burst Write (Multi Bank) [BL=4] /CS /RAS trrd tras trc trc trp /CAS twr twr /WE M A-9, A A2 BA, D D D D D D D D D D D D ACT# WRITE# PRE# ACT# WRITE# PRE# ACT# WRITEA# ACT# (Auto-Precharge) Italic paramater shows minimum case 34 Integrated Silicon Solution, Inc //5

35 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Burst Read (Single Bank) [CL=2, BL=4] /CS trc tras trp tras /RAS /CAS /WE M A-9, A A2 BA, Q Q Q Q Q Q Q Q ACT# # PRE# ACT# # PRE# Italic paramater shows minimum case Integrated Silicon Solution, Inc //5

36 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Burst Read (Multi Bank) [CL=2, BL=4] /CS trc trc /RAS trrd tras /CAS /WE M A-9, A A2 BA, Q Q Q Q Q Q Q Q Q Q Q Q ACT# A# ACT# # PRE# ACT# A# ACT# Italic paramater shows minimum case 36 Integrated Silicon Solution, Inc //5

37 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Write Interrupted by Write [BL=4] /CS /RAS /CAS trrd /WE twr M A-9, A A2 BA, D D D D D D D D D D D D ACT# WRITE# WRITE# WRITEA# WRITE# PRE# interrupt interrupt interrupt ACT# ACT# same bank other bank other bank Italic paramater shows minimum case Integrated Silicon Solution, Inc //5

38 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Read Interrupted by Read [CL=2, BL=4] /CS /RAS /CAS trrd /WE M A-9, A A2 BA, Q Q Q Q Q Q Q Q Q Q Q Q ACT# # # A# # interrupt interrupt interrupt ACT# other bank same bank other bank ACT# Italic paramater shows minimum case 38 Integrated Silicon Solution, Inc //5

39 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4] /CS /RAS /CAS trrd /WE twr M A-9, A A2 BA, D D Q Q D D D D ACT# WRITE# # WRITE# PRE# ACT# Italic paramater shows minimum case Integrated Silicon Solution, Inc //5

40 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Write / Read Terminated by Precharge [CL=2, BL=4] trc /CS trp tras trp /RAS /CAS /WE twr M A-9, A A2 BA, D D Q Q ACT# WRITE# PRE# ACT# # PRE# ACT# Terminate Terminate Italic paramater shows minimum case 4 Integrated Silicon Solution, Inc //5

41 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Write / Read Terminated by Burst Terminate [CL=2, BL=4] /CS /RAS /CAS /WE twr M A-9, A A2 BA, D D Q Q D D D D ACT# WRITE# TBST # TBST WRITE# PRE# Italic paramater shows minimum case Integrated Silicon Solution, Inc //5

42 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Single Write Burst Read [CL=2, BL=4] /CS /RAS /CAS /WE M A-9, A A2 BA, D Q Q Q Q ACT# WRITE# # Italic paramater shows minimum case 42 Integrated Silicon Solution, Inc //5

43 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Power-Up Sequence and Intialize /CS 2µs /RAS trp trfc trfc trsc /CAS /WE M A-9, MA A A2 BA, NOP Power On PRE ALL REFA REFA REFA MRS ACT# Minimum 8 REFA cycles Italic paramater shows minimum case Integrated Silicon Solution, Inc //5

44 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Auto Refresh /CS trfc /RAS trp /CAS /WE M A-9, A A2 BA, D D D D PRE ALL REFA ACT# WRITE# All banks must be idle before REFA is issued. Italic paramater shows minimum case 44 Integrated Silicon Solution, Inc //5

45 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Self Refresh /CS trfc /RAS trp /CAS /WE M A-9, A A2 BA, PRE ALL Self Refresh Entry Self Refresh Exit ACT# All banks must be idle before REFS is issued. Italic paramater shows minimum case Integrated Silicon Solution, Inc //5

46 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Suspension [CL=2, BL=4] /CS /RAS /CAS /WE M A-9, A A2 BA, D D D D Q Q Q Q ACT# WRITE# internal # internal suspended suspended Italic paramater shows minimum case 46 Integrated Silicon Solution, Inc //5

47 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) Power Down /CS /RAS /CAS /WE Standby Power Down Active Power Down M A-9, A A2 BA, PRE ALL ACT# Italic paramater shows minimum case Integrated Silicon Solution, Inc //5

48 IS42S832A (4-bank x 8,388,68 - word x 8-bit) IS42S66A (4-bank x 4,94,34 - word x 6-bit) ORDERING INFORMATION Commercial Range: C to +7 C Frequency Speed (ns) Order Part No. Package 66 MHz 6 IS42S66A-6T 54-pin TSOP-II 43 MHz 7 IS42S66A-7T 54-pin TSOP-II 33 MHz 7.5 IS42S832A-75T 54-pin TSOP-II Commercial Range: C to +7 C, Lead-free Frequency Speed (ns) Order Part No. Package 66 MHz 6 IS42S66A-6TL 54-pin TSOP-II 43 MHz 7 IS42S66A-7TL 54-pin TSOP-II 33 MHz 7.5 IS42S832A-75TL 54-pin TSOP-II 48 Integrated Silicon Solution, Inc //5

49 PACKAGING INFORMATION Plastic TSOP 54 Pin, 86-Pin Package Code: T (Type II) N N/2+ N/2 E E Notes:. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within.4 inches at the seating plane. D ZD A SEATING PLANE e b A L α C Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 54 A.2.47 A A2 b C D E E e.8 BSC.3 BSC L L ZD.7 REF α 8 8 Plastic TSOP (T - Type II) Millimeters Inches Symbol Min Max Min Max Ref. Std. No. Leads (N) 86 A.2.47 A A b C D E E e.5 BSC.2 BSC L L.8 REF.3 REF ZD.6 REF.24 BSC α 8 8 Integrated Silicon Solution, Inc. 3/3/7