Maximize Your Insight for Validation on MIPI and (LP)DDR Systems. Project Manager / Keysight Technologies

Transcription

1 Maximize Your Insight for Validation on MIPI and (LP)DDR Systems Project Manager / Keysight Technologies Jacky Yu Taipei

2 MIPI Standard and Application Program Overview Keysight M-PHY Electrical Testing Keysight C/D-PHY Electrical Testing Keysight (LP)DDR Electrical Testing 2

3 2018 Keysight Technologies 3

4 H U G E D I F F E R E N T I AT E D P O S I T I O N Keysight has your testing needs covered We offer the most complete test solutions portfolio. Keysight gives the best testing experience, whether you are working on a transmitter, receiver or cable tests for your high speed interface compliance, debug and validation testing. Keysight compliance software gives you the most insights Whether test software or hardware, Keysight s objective is always to deliver the most accuracy because you need to know true performance to make good decisions. We then design the test software to enable the most use cases whether your task is the compliance hurdles or any of the activities prior to compliance. Keysight experts help shape emerging test standards Our engineers help define test standards long before the products that use them are even available. We design our oscilloscopes and application software to meet these future standards, so you can get to market faster. 4

5 G O A L S Structure the intestines of mobile devices ranging from smartphones to wirelessenabled tablets and netbooks Benefit the entire mobile industry by establishing standards for hardware and software interfaces Enabling reuse and compatibility making system integration less burdensome The distinctive requirements of mobile terminals drive the development of MIPI Specifications Power saving / battery life Bandwidth on demand MIPI M-PHY Receiver Test Webinar August

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8 2018 Keysight Technologies 8

9 H I G H S P E E D A N D L O W S P E E D M O D E S High Speed NRZ (HS) and Lower Speed (LS) modes Common LS mode: Pulse Width Modulation (PWM) Always differential and 8b/10b coded High and low voltage swing operations Terminated (100 ohm) or not terminated operation 9

10 V E R S I O N 4. 0 T O 4. 1 M-PHY 4.0 : Approved Aug 3, 2015 Minor spec clarification Target BER to M-PHY : Approved Mar 28,

11 V E R S I O N 3. 1 T O 4. 1 CTS 3.1 : On-going(revision 21) Test HS-TX G3 and G4 Differential AC Eye (TEYE-HS-G3/G4-TX, VDIF-AC- HS-G3/G4-TX) Minor updates CTS 4.0/4.1 : On-going(revision 2) 11

12 MIPI M-PHY HSG3/G4 Test point C H A N G E S F R O M G E A R 3 T O G E A R 4 Test setup is same on both HSG3 and HSG4 but testing points has changed. MIPI M-PHY HS G3/G4 test setup Gear3 DUT CH1/CH2 PLL Oscilloscope CH1/CH2 PKG CTLE PLL DFE Gear4 12

13 N E W R E F E R E N C E PA C K A G E M O D E L Gear3 DUT CH1/CH2 PLL CH1/CH2 PKG CTLE PLL DFE Oscilloscope Gear4-3dB at 5.83GHz 13

14 D O E S I T C O R R E L AT E D B E T W E E N?? Not likely another application, M-PHY CTLE has vary wide range of zero pole value and Adc value What if A company think 2.5dB Adc + 400MHz Fz is optimal CTLE value B company think 0dB Adc + 400MHz Fz is optimal CTLE value? 14

15 T H E A N S W E R IS N O Same waveform but only change Adc value from 2.5dB to 0dB Adc : CTLE DC gain Fz : CTLE zero frequency 2.5dB Adc case Fz = 400MHz 0dB Adc case Fz = 400MHz Keysight MIPI M-PHY test solutions 15

16 EYE D I A G R A M S H A P E A R E D I F F E R E N T V DEF_RX : DFE feedback voltage signal 40mV V DEF_RX 60mV V DEF_RX 40mV/133mV = mV/133mV =

17 A L M O S T T H E S A M E E Y E S H A P E A N D R E S U LT Use SigTest tool Commonly used for High speed digital interface USB PCIe Provide similar result between oscilloscopes A company B company Keysight MIPI M-PHY test solutions 17

18 S U P P O R T I N G G E A R 4 T E S T Added support for the following HS-G4 Data Rate to support CTS v4.0 and v4.1. HS-G4A (9984) HS-G4B ( ) HS-G4B ( ) HS-G4B ( ) Added configurable option of SigTest (with remote name of TEYESigTestEnable ) in Set Up tab. This configurable option is used to enable or disable Test TEYE_G4, VDIF_AC_G4 [SigTest] tests. 18

19 T E S T I T E M S U P P O R T I N G CTS Test ID Test Name Test Availability [MPHY v3.2] H S t e s t P W M t e s t S Y S t e s t HS-TX Unit Interval and Frequency Offset (UIHS and foffset-tx) YES HS-TX Common-Mode AC Power Spectral Magnitude Limit (PSDCM-TX) (INFORMATIVE) YES HS-TX PREPARE Length (THS-PREPARE) YES HS-TX Common-Mode DC Output Voltage Amplitude (VCM-TX) YES HS-TX Differential DC Output Voltage Amplitude (VDIF-DC-TX) YES HS-TX G1 and G2 Differential AC Eye (TEYE-TX, VDIF-AC-TX) YES HS-TX G3 and G4 Differential AC Eye (TEYE-HS-G3/G4-TX, VDIF-AC-HS-G3/G4-TX) YES HS-TX 20/80% Rise and Fall Times (TR-HS-TX and TF-HS-TX) (INFORMATIVE) YES HS-TX Lane-to-Lane Skew (TL2L-SKEW-HS-TX) YES HS-TX Slew Rate Control Range (SRDIF-TX[MAX/MIN]) YES HS-TX Slew Rate State Monotonicity YES HS-TX Slew Rate State Resolution (ΔSRDIF-TX) YES HS-TX Intra-Lane Output Skew (TINTRA-SKEW-TX) YES HS-TX Transmitter Pulse Width (TPULSE-TX) YES HS-TX Total Jitter (TJTX) YES HS-TX Short-Term Total Jitter (STTJTX) YES HS-TX Deterministic Jitter (DJTX) YES HS-TX Short-Term Deterministic Jitter (STDJTX) YES PWM-TX Transmit Bit Duration (TPWM-TX) YES PWM-TX Transmit Ratio (kpwm-tx) YES PWM-TX PREPARE Length (TPWM-PREPARE) YES PWM-TX Common Mode DC Output Voltage Amplitude (VCM-TX) YES PWM-TX Differential DC Output Voltage Amplitude (VDIF-DC-TX) YES PWM-TX Minimum Differential AC Eye Opening (TEYE-TX)(OBSOLETE) YES PWM-TX Maximum Differential AC Output Voltage Amplitude (VDIF-AC-TX) YES PWM-TX 20/80% Rise and Fall Times (TR-PWM-TX and TF-PWM-TX) YES PWM-TX Lane-to-Lane Skew (TL2L-SKEW-PWM-TX) YES PWM-TX Transmit Bit Duration Tolerance (TOLPWM-TX, TOLPWM-G1-LR-TX) YES PWM-TX G0 Minor Duration (TPWM-MINOR-GO-TX) YES SYS-TX Unit Interval and Frequency Offset (UISYS and foffset-tx) NO SYS-TX RefClk Frequency (UIREFCLK and frefclk-tx) NO SYS-TX PREPARE Length (TSYS-PREPARE) NO SYS-TX Common Mode DC Output Voltage Amplitude (VCM-TX) NO SYS-TX Differential DC Output Voltage Amplitude (VDIF-DC-TX) NO SYS-TX Minimum Differential AC Eye Opening (TEYE-TX)(OBSOLETE) NO SYS-TX Maximum Differential AC Output Voltage Amplitude (VDIF-AC-TX) NO SYS-TX 20/80% Rise and Fall Times (TR-SYS-TX and TF-SYS-TX) NO SYS-TX Lane-to-Lane Skew (TL2L-SKEW-SYS-TX) NO Keysight does not support SYS mode, Because there has no customer for SYS mode. 19

20 T E S T R E S U LT E X A M P L E TEYE_G3_LA_RT_TX(CH2 embedded) TEYE_G3_LA_RT_TX[Far End HS-RX test point] TJ_LA_RT_TX TEYE_G4_LA_RT_TX(SigTest tool embedded) 20

21 Simplified Tx setup with N7010A active termination adaptor Infiniium DSAV254A 25GHz Oscilloscope N7010A Active adaptor 2x6 (1x6 differential) Switch Matrix Keysight U3020AS26 (for multi lane testing.) 21

22 J-BERT M8020A N7010A Simplified set-up with Keysight J-BERT M8020A ISI conformance channel integrated 22

23 Internal Loopback or Error counter Cal-plane Stress Signal Generation and Calibration according to CTS for Gear1 to Gear3 RT-Oscilloscope 100 Ohm Differential Probe BERT Pattern Generator w/ TTCs ISI Conformance Channel Replica Trace TP RX DUT ASIC Breakout Trace Test board with Replica Traces creating test point (TP) for calibration TX equivalent to the ASIC-input pins Ref Clk Custom Test Board 23

24 Internal Loopback or Error counter Cal-plane Stress Signal Generation and Calibration for Gear 4 (1) small EW/EH (2) BERT Pattern Generator w/ TTCs ISI Conformance Channel Replica Trace TP EQ RX DUT larger EW/EH ASIC Test board with Replica Traces creating test point (TP) for calibration Breakout Trace TX (3) equivalent to the ASIC-input pins Ref Clk Custom Test Board 24

25 N5990A Automatic Software 25

26 2018 Keysight Technologies 26

27 S U P P O R T B U R S T A N D C O N T I N U O U S M O D E New MIPI C-PHY v1.1 and D-PHY v2.0 or above require to send both Burst mode and Continuous mode signal on testing, so it is good to consider to implement both mode for easy testing. If not, it is not easy to get right test result. MIPI C-PHY CTS Annex B MIPI D-PHY CTS Annex B 27

28 E Y E D I A G R A M I S D I S T O R T E D W H E N H I G H E R D ATA R AT E RTB(Reference Termination Board) can t support new specifications sps : Symbol Per Second Click to add text 500Msps 1Gsps 1.5Gsps 2.0Gsps 2.5Gsps Same data, +/-250mV HS swing, 82ps R/F time, without reference channel 28

29 MIPI C-PHY MIPI D-PHY D I R E C T C O N N E C T I O N T O S C O P E Now, PHY WG defines direct connection to oscilloscope However, RTB is still required for LP to HS timing test. Setup 2 Direct connection to scope(hs only) TX HS Test Setup 2 Direct connection to oscilloscope (HS, 100ohm termination only) DUT Oscilloscope 29

30 S I G N A L Q U A L I T Y I S B A D W I T H R T B W H E N O V E R 1. 0 G Direct connection provide more accurate result on tests sps : Symbol Per Second 500Msps 1Gsps 1.5Gsps 2.0Gsps 2.5Gsps 30

31 O U T L O O K HS Burst(w/ or w/o LP EscapeMode), LP EscapeMode only and T3 PROGSEQMode Support CTS v1.0 and v1.1 Select test items 31

32 C L O C K R E C O V E R Y Clock is recovered from the earliest edge of a symbol transition. 2. Using function make VAB, VAC, VBC (Symbol transition) 3. Among VAB, VAC, VBC, find each first arrival edge on acquired signal and build clock recovery 1. Acquire VA, VB, VC at once 32

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34 O U T L O O K Support CTS v1.1, 1.2 and v2.0/2.1 Running separate testing based on termination impedance Select test items 34

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36 DDR Clock: Quarter rata clock HS Clock(6G) at TX HS Clock(6G) at RX This is because when we are running data 12Gbps, after channel, receiver side clock is become -40mV/40mV swing. And jitter will be more than 4 times. So it is not easy to use it 36

37 F U L LY A U T O M AT I C W I T H H T M L R E P O R T C-PHY Keysight DSAV134A digital oscilloscope + U7250A MIPI C-PHY compliance software Industry first supporting C-PHY v1.1 CTS test items Already proven solution with key industry leading customers Combined one eye diagram supports from 3 differential eye diagrams Eye Diagram test D-PHY Keysight DSAV164A digital oscilloscope + U7238E MIPI D-PHY compliance software Industry first supporting D-PHY v2.0/v2.1 specification test Already proven solution with key industry leading customers Reference channel embedding supporting VOD(differential voltage) test 37

38 F U L LY A U T O M AT I C A N D O N E B O X I N T E G R AT E D C-PHY Keysight M8195A Arbitrary Waveform generator + M8085CE1A and M8085CC1A C-PHY software Scalable up to 4 Trios Data rate up to 8Gbps Advanced TX Equalization supporting D-PHY Keysight M8195A Arbitrary Waveform generator + M8085DE1A and M8085DC1A D-PHY software Scalable up to 8 lanes(include clock) Data rate up to 16Gbps with dual module mode(single module, up to 8Gbps) Hardware SSC(spread spectrum clocking) Deemphasis and variety of Jitter injecting 38

39 Transmitter Characterization DSAQ93204A Infiniium Receiver Characterization N4903B/M8020A JBERT Impedance/Return Loss Validation E5071C ENA Option TDR Protocol Stimulus and Analysis U4421A D-PHY CSI-2 / DSI Analyzer and Exerciser U4431A M-PHY Analyzer (UFS, UniPro, CSI-3, SSIC, M-PCIe) U7238D D-PHY, U7249D M-PHY, C-PHY U7250A InfiniiMax Probes Switch matrix N5465A InfiniiSim N2809A PrecisionProbe M8190/M8195 AWG 81250A ParBERT N5990A Automated characterization DCA 86100D Wideband sampling oscilloscope N1055A TDR/TDT Scope Protocol Decoder N8802A CSI-2 / DSI N8807A DigRF v4 N8808A UniPro N8818A UFS N8809A LLI N8819A SSIC N8820A CSI-3 N8824A RFFE 54754A TDR/TDT Industry s highest analog bandwidth, lowest noise floor/sensitivity, jitter measurement floor with unique cable/probe correction Highest precision jitter lab source with automated compliance software for accurate, efficient, and consistent measurement Precision impedance measurements and S-Parameter capability Fast upload and display, accurate capture, intuitive GUI and customizable hardware. Correlate physical and protocol layer. 39

40 2018 Keysight Technologies 40

41 Operating voltage L P D D R 4 A N D L P D D R 4 X M A R K E T S H A R E O V E R 5 0 % V Copyright DRAMeXchange V DDR4 1.2V LPDDR4 1.1V DDR4 and LPDDR4 speed overlap DDR2 DDR4 DDR3 LPDDR1/2/3/4/5 41

42 Physical layout of a board Memory Controller DRAM probe Delay InfiniiMax probe head Memory Controller Simulation DRAM BLOCK E BGA probe S2P file BLOCK P InfiniiMax probe head s1p file Measurement 42

43 Supports x4/x8 pin-out DDR4 DRAM N2114A Note: All signals available at probe points except power, Vref, RFU Riser Elevates the interposer for smaller surface keep-out area 43

44 Solder-In or SMP connector option LPDDR4 200 BGA Interposer LPDDR4 366 BGA Interposer 44

45 N A S O L D E R E D O N T O X I L I N X D D R 4 B O A R D DDR4 BGA interposer soldered between PCB and DRAM. Zif probe heads provide connection to oscilloscope DDR x16 BGA interposer (N2115A) 45

46 DDR InfiniiSim on CLK (ch2) InfiniiSim off CLK (m1) DDR InfiniiSim on DQS (ch2) DQ (ch3) InfiniiSim off DQS (m2) DQ (m3) 46

47 InfiniiSim OFF InfiniiSim ON tdivw margin: 141% vdivw margin: 106% tdivw margin: 196% vdivw margin: 111% 47

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50 Evolutionary approach to 6.4Gb/s 16 bit bursts Two x40 channels per DIMM! Cmd + Addr busses combined into 6 DDR pins DDR4-style Rx Mask Eye will be closed at DRAM ball PCIe Gen 3 style DFE with a DRAM twist Single ended, xtalk dominated channel Bidirectional Rd/Wr separation required DDR4 pain causing vendors to take our advice seriously Loopback pin Tweaks to actual spec design Standard measurement procedures DDR5 DRAM Clock/DQS DQ DQM / Test pin MRS places DRAM in loopback mode BERT (e.g. N4903B or M8000) 50

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