32Gbaud PAM4 True BER Measurement Solution

Transcription

1 Product Introduction 32Gbaud PAM4 True BER Measurement Solution Signal Quality Analyzer-R MP1900A Series 32Gbaud Power PAM4 Converter G0375A 32Gbaud PAM4 Decoder with CTLE G0376A

2 MP1900A Series PAM4 Measurement Solution Features Supports high 64 Gbaud rate for both PAM4 and NRZ 32 Gbaud 8ch PAM4 transmission capacity* (512 Gbit/s for one MP1900A) Excellent expandability 32 Gbaud PAM4 8ch Multi-channel Expandability to 64 Gbaud Low Intrinsic Jitter, high-quality waveforms High-amplitude PAM4 output (G0375A + 32G PPG) High-input-sensitivity error detection 28 Gbaud CTLE (G0376A or 32G ED) and CDR functions (32G ED) Supports receiver tests using Jitter Addition function [PAM4 Applications] 28 Gbaud PAM4 ICs, Backplanes, Active Optical Cables, CEI-56G-PAM4 53 Gbaud/26 Gbaud, 200GbE/400GbE Optical Modules, Optical Devices, IC Future-proof instrument configuration Effective inspection supported by functions and performance * Refer to the MP1900A selection guide for today s module configuration support. 2

3 MP1900A 32 Gbaud PAM4 BER Solution Overview MP1900A 32 Gbaud Power PAM4 Converter G0375A Loss CH DUT 32 Gbaud PAM4 Decoder with CTLE G0376A Support PRBS31Q pattern of PAM4 BER measurement Small Remote Head for close-in approach to DUT Multi-channel Excellent expandability and PAM4/NRZ support 3.9Vp-p (differential) PAM4 output 10 Tap Emphasis (by MU195020A PPG) Clean Eye/low Jitter Tr/Tf 14ps (typ.) (PAM4 output) CTLE 14 GHz, 12dB Clock Recovery (by MU195040A ED) High input sensitivity of 40mV (EH) True PAM4 BER measurement 3

4 G0375A 32G High-Amplitude PAM4 Signal Generation EA modulator direct-driving, high-amplitude output and 3Eye independent level control support TOSA evaluation without external driver amplifier to reduce setup procedures and time Clean Eye and low-jitter waveforms using reference signal source support high-reproducibility evaluations G0375A Features Baud rates of 10 Gbaud to 32.1 Gbaud High-amplitude PAM4 output of 1.95 Vp-p (single-end), and 3.8 Vp-p (differential) Low-Jitter output waveforms with 200 fs (typ.) RJ Compact Remote Head Emphasis output Signal Quality Analyzer-R MP1900A 32 Gbit/s 2 ch PPG 32Gbaud Power PAM4 Converter G0375A MSB LSB 4

5 G0375A with MU195020A PPG, PAM4 Typical Waveforms Low intrinsic jitter PAM4 data output support high-reproducibility evaluations 28 Gbaud, 0.9 Vp-p (Single-end) 25 Gbaud, 0.9 Vp-p (Single-end) MU195020A Emphasis Pre1 = 0.5 db, Post1 = 0.3 db, 40 cm test cable 5

6 CEI-56G-VSR-PAM4 Receiver Evaluation Typical Test Signals Supports PAM4 high-speed device receiver tests Low Jitter/Clean Eye PAM4 10Tap Emphasis function 28 Gbaud Without Emphasis (before passing channel) 28 Gbaud With Emphasis (before passing 10 db channel) 28 Gbaud With Emphasis (after passing 10 db channel) 6

7 PAM4 Test Patterns (1/2) Support PAM4 Test Patterns Specified by 200/400 GbE Standards Supported Test Patterns Details PRBS13Q, PRBS31Q*, SSPRQ: Patterns defined by IEEE802.3bs, 802.3cd 200 GbE, and 400 GbE QPRBS13-CEI: Transmitter Output measurement and Receiver Input calibration patterns defined by CEI-56G PAM4 standard PRBS 7,9,10,11,15,20,23*,31* Pseudo Random Bit Sequence pattern SSPR (Short Stress Pattern Random): This 32,762-bit pattern is defined by CEI 3.1. The pattern length is equivalent to PRBS15 and it is used as a PAM4 evaluation pattern due to its features as a high-stress test signal. PrePRBS20, PreQPRBS13-CEI: The 1/(1+D) mod4 Precoding (defined in IEEE 802.3cd standard) pattern has been added to the PRBS20 and QPRBS13 patterns to reduce DFE burst errors at use by Tx. *Supported by G0376A 7

8 PAM4 Test Patterns (2/2) JP03A: This 0303 pattern string is used for evaluating Transmitter RJ. JP03B: This 62-symbol pattern has 15 repetitions of 03 followed by 16 repetitions It is used for evaluating Transmitter Even-Odd Jitter. Square: This pattern string is for Optical Modulation Amplitude (OMA) evaluation of optical interfaces. Transmitter linearity Test Pattern: This 160-symbol pattern is composed of blocks of 10 PAM4 symbols shown below forming a contiguous pattern each of 16UI. {0, 1, 2, 3, 0, 3, 0, 3, 2, 1} The Linearity Test in the latest standards uses a PRBS13Q pattern. RLM = min((3 x ES1), (3 x ES2), (2-3 x ES1), (2-3 x ES2)) ES1 = (V1 - Vmid)/(V0 - Vmid), ES2 = (V2 - Vmid)/(V3 - Vmid), Vmid = (V0 + V3)/2 PRQS10: PAM4 test pattern discussed by IEEE 802.3bs. Gray-xxxx Although PAM4 signals have four levels implemented as 2-bit pairs, sometimes a 2-bit change such as 01 to 10 is detected for a 1 level change. To prevent this, the Tx side uses a Gray code (00 00, 01 01, 10 11, 11 10) and the Rx side uses the opposite Gray decode. 8

9 G0376A 32G PAM4 BER Measurement Implements high-input-sensitivity PAM4 True BER measurement for more accurate design verification Combining CTLE and CDR (32G ED function) supports high-input-sensitivity BER measurement G0376A Features Baud rate of 10 Gbaud to 32.1 Gbaud High input sensitivity (Eye Height 40 Gbaud) Tunable CTLE (Gain 12 to 0 db) CDR Function (set with MU195040A-022) Signal Quality Analyzer-R MP1900A 32 Gbit/s 2 ch PPG, 32 Gbit/s 2 ch ED MSB LSB MSB 32 Gbaud Power PAM4 Converter G0375A DUT LSB 32 Gbaud PAM4 Decoder with CTLE G0376A 9

10 PAM4 BER Measurement using MP1900A Series G0375A/G0376A Combining 32G 2ch BERT (MSB/LSB) and PAM4 Converter/Decoder supports both PAM4 and NRZ BER measurements PPG1 PPG (MSB) (LSB) PPG1 (MSB) PPG2 (LSB) (PAM4 Encode: G0375A) PAM4 Encode: G0375A PAM Low Mid Upp (PAM4 Decode: G0376A) DF F DF F DF F PAM4 Decode: G0376A ED (MSB) ED (LSB) ED1 (MSB) ED2 (LSB) 10

11 Reference Setup for 32Gbaud PAM4 BER Solution True BER measurement of PAM4 signal J1741A cable x4 (80cm, skew <1ps) 32Gbaud Power PAM4 Converter G0375A 32G 2ch PPG MU195020A (Opt 001, 020, 021, 031) Synthesizer MU181000B Signal Quality Analyzer-R MP1900A Decoder Full-rate Clock (Rear Panel) (Front Panel) J1728A cable x2 (40cm, skew <1ps) (*1) cable x2 (skew <1ps) CTLE Input DUT Decoder Input 32G 2ch ED MU195040A (Opt 001, 020, 022) (Front Panel) (Rear Panel) J1728A cable x2 (40cm, skew <1ps) 32Gbaud PAM4 Decoder with CTLE G0376A (*1) J1728A or lower loss cable 11

12 Reference Setup for TOSA Evaluation Solution High-amplitude, low-jitter PAM4 signal generation with Linearity control 32G 2ch PPG MU195020A (Opt 001,020, 021, 031) x2 MU181000B Synthesizer J1742A cable x2 (84cm, skew <1ps) (direct connection) 32Gbaud Power PAM4 Converter G0375A (Rear Panel) (Front Panel) J1728A cable x2 (40cm, skew <1ps) DUT J1741A cable x4 (80cm, skew <1ps) Signal Quality Analyzer-R MP1900A J1735A Combiner x2 12

13 I/O Control using MX183000A software G0375A: PAM4 output level controlled by using control software to control output amplitude of connected PPG G0376A: Control CLTE gain and Pam4 Decoder input threshold voltage (Vref for each of Upper/Middle/Lower) via USB connection (MX183000A Control Software can be downloaded from download site at MP1900A home page) Control Software Screen Examples 13

14 Main Application (1) Evaluation of 28Gbaud PAM4 TOSA/ROSA High amplitude, low-jitter PAM4 signals PAM4 Linearity control Eye opening adjustment using CTLE function MP1900A MU195020A 32 G PPG(2 or 3 ch) MU195040A 32 G 2 ch ED 32 Gbaud Power PAM4 Converter G0375A LD Scope TIA PD 32 Gbaud PAM4 Decoder with CTLE G0376A 14

15 Main Application (2) Supports 400 GAUI-8, CEI-56G-VSR-PAM4 Electrical I/F Rx tests Low-Jitter PAM4 waveform 10Tap Emphasis function Jitter Addition function RJ/BUJ/SJ CTLE (14 GHz peak frequency) CDR function (as set with MU195040B-022) MP1900A MU195020A 32 G 2 ch PPG MU195040A 32 G 2 ch ED MU181500B Jitter MU181000B Synthesizer MX183000A JTOL software 32 Gbaud Power PAM4 Converter G0375A Artek ISI generator PAM4 Transceiver, Re-timer 15

16 Recommended 32G PAM4 BER Measuring Instruments Model Name Option Qty Remark G0375A 32Gbaud Power PAM4 Converter - 1 G0376A 32Gbaud PAM4 Decoder with CTLE - 1 MP1900A Signal Quality Analyzer-R 1 MU181000B 12.5GHz 4port Synthesizer - 1 MU181500B Jitter Modulation Source - 1 For Jitter Tolerance Test MU195020A 21G/32G bit/s SI PPG 001, 020, 021, 031 MU195040A 21G/32G bit/s SI ED 001, 020, J1439A Coaxial Cable (0.8m, K connector) - 1 J1728A MX183000A PAM4 Control MX183000A- PL001 Electrical Length Specified Coaxial Cable (0.4m, K connector) 1 - (2) Waveform monitoring cable PAM4 Control Software - 1 Standard software Jitter Tolerance Test - 1 For Jitter Tolerance Test 16

17 G0375A 32Gbaud Power PAM4 Converter main Specifications Item Specification Remarks Number of Outputs 2 (Data, xdata) AC coupling Baud-Rate 10 to 32.1 Gbaud Output Amplitude 0.3 to 1.95 Vp-p (Single-end, typ.) Data1 input 0.2 to 1.3 Vp-p, Data2 input 0.1 to 0.65 Vp-p Random Jitter (RMS) 200 fs (typ.) Tr/Tf (20-80%) 14 ps (typ.) Using MU195020A SI-PPG Eye Linearity(RLM) 0.6 to 1.0 adjustable from level ratio Number of Inputs 4 (Data1, xdata1, Data2, xdata2) Uses PPG Data3 and J1735A (two for differential) at 3 Eye independent level control Maximum Input Amplitude 1.5 Vp-p (Data1, xdata1) 0.75 Vp-p (Data2, xdata2) 17

18 G0376A 32Gbaud PAM4 Decoder with CTLE Main Specifications - PAM4 Decoder specification Item Specification Remarks Number of Inputs 2 (Data, xdata), 1 (External Clock) K (female) connector Baud-Rate 10 to 32.1 Gbaud (DFF On mode) 10 to 28.1 Gbaud (DFF OFF mode) Uses MU195040A with external clock Uses CDR of MU195040A-022 Data Input Amplitude 0.4 Vp-p (typ.), 0.5 Vp-p (max.) Single-end Data Input Sensitivity 40 mv (typ.) 28 Gbaud, Per Eye, Eye Height, Single-end at E-6 Clock Input Frequency 10 to 32.1 GHz (DFF ON mode) Full-rate clock Clock input amplitude 0.3 to 1.0 Vp-p External Clock Input Number of Outputs 3 (Data1, Data2, Monitor Data) K (female) connector Output Amplitude 0/-0.3 Vp-p (typ.) Internal DFF Selectable ON / OFF Uses external Clock for DFF ON mode - CTLE specification Item Specification Remarks Number of Inputs 2 (Data, xdata) K (female) connector Data Input Amplitude CTLE Gain CTLE Peak Frequency 0.4 V (max.) -12 to 0 db adjustable 14 GHz (typ.) Number of Outputs 2 (Data, xdata) K (female) connector 18

19 G0375A/G0376A Block Diagrams - G0375A Block Diagram xdata1 input xdata2 input Passive Combiner Linear amp. Data output Data1 input Data2 input Passive Combiner Linear amp. xdata output - G0376A Block Diagram Data input xdata input Clock input CTLE CTLE xdata output xdata input Data output Data input PAM4 Decoder Upper Middl e Lower Use Clock input for DFF On Monitor output (MSB) Data1 output (MSB) Data2 output (LSB) 19

20 公知 MJM No. MP1900A_G0375A_G0376A-E-L-1-(1.01)