How to overcome test challenges in 400G/PAM-4 designs

Transcription

1 How to overcome test 400G/PAM-4 designs Keysight Presenters: Rob Sleigh Steve Reinhold February 15, 2017

2 Agenda Introduction o Why use Pulse Amplitude Modulation 4-Level (PAM-4)? o Review Standards using PAM-4 Output (Transmitter) Characterization o Key Optical PAM-4 Measurements o Key Electrical PAM-4 Measurements Input (Receiver) Characterization Summary Q&A 400G/PAM-4 designs Page 2

3 Why does the industry need PAM-4? Enables higher data throughput NRZ > 28 Gb/s limits trace length or increases cost PAM-4 packs 2 bits / symbol Halves the channel BW needs Allows designers to develop products to fit cost structure of available channel technologies. 4 amplitude levels 2 bits of information in every symbol ~ 2x throughput for the same Baud rate 28 GBaud PAM-4 = 56 Gb/s Lower SNR, more susceptible to noise More complex TX/RX design, higher cost 400G/PAM-4 designs Page 3

4 Challenges moving from NRZ to PAM-4 Design and Measurement Packing 4 levels into amplitude swing of 2 lose 9.6 db SNR It is not just about timing jitter budgets anymore! Better management of noise and return loss Finite rise time creates inherent DDJ How to implement clock recovery? Closed eyes with lower SNR FEC often required G/PAM-4 designs Page 4

5 Current Draft Standards and IAs using PAM-4 Optical NEW! 200G/400G Ethernet (802.3bs) (Draft 3.0) 200GBASE-FR4/LR4 4 lanes of 26.5 Gbaud WDM on 1 SMF 2/10 km reach 200GBASE-DR4 4 lanes of 26.5 Gbaud PAM-4 on 4 SMF 500 m reach 400GBASE-FR8/LR8 8 lanes of 26.5 Gbaud WDM on 1 SMF 2/10 km reach 400GBASE-DR4 4 lanes of 53 Gbaud PAM-4 on 4 SMF 500 m reach 50G/100G/200G Ethernet (802.3cd) (Draft 1.2) 50GBASE-SR, 100GBASE-SR2, 200GBASE-SR4 1/2/4 MMF 50GBASE-FR, 50GBASE-LR 1 SMF CWDM 100GBASE-DR 1 SMF 64GFC Fibre Channel (PI-7) Several variants using both SMF and MMF 400G/PAM-4 designs Page 5

6 System Architectures - Optical Parallel vs WDM (Wavelength-division multiplexing) Parallel Fiber Architecture Reference: IEEE P802.3bs /D2.2, 28th Nov 2016, page 294. WDM Architecture Reference: IEEE P802.3bs /D2.2, 28th Nov 2016, page 246. WDM (right) only requires one fiber, but requires more complex Tx/Rx (WD Mux/Demux) Unless otherwise specified, all Tx optical measurements performed through a short patch cable (2m-5m) 400G/PAM-4 designs Page 6

7 Current Draft Standards and IAs using PAM-4 Electrical Chip-to-Chip (C2C), Chip-to-Module (C2M) Optical Internetworking Forum Common Electrical Interface (CEI-56G-xxx) CEI-56G-XSR-PAM-4 chip to nearby chip using forwarded ref clock 100 mm reach CEI-56G-VSR-PAM-4 chip to chip, chip to module 150 mm reach with 1 connector 400G Ethernet (802.3bs) (Draft 3.0) 200GAUI-4 / 400GAUI-8 chip 2 chip, chip 2 module (similar to CEI-56G-VSR-PAM-4) 64GFC Fibre Channel (PI-7) Chip to chip and Chip to Module 150 mm reach, based on CEI-56G-VSR-PAM-4 InfiniBand High Data Rate (HDR) 50/200/600 Gb/s Several variants based on IEEE 802.3bs/cd and OIF CEI-56G IAs 400G/PAM-4 designs Page 7

8 Current Draft Standards and IAs using PAM-4 Electrical copper cable, circuit board, and backplane Optical Internetworking Forum Common Electrical Interface (CEI-56G-xxx) CEI-56G-MR-PAM-4 chip to distant chip on same board 500 mm reach CEI-56G-LR-PAM-4 backplane/passive cable with 3 connectors 1 m reach NEW! 50G/100G/200G Ethernet (802.3cd D1.2) 50GBASE-CR, 100GBASE-CR2, 200GBASE-CR4 1/2/4 diff pairs of twinax 50GBASE-KR, 100GBASE-KR2, 200GBASE-KR4 1/2/4 lanes in backplane InfiniBand High Data Rate (HDR) 50/200/600 Gb/s Several variants based on IEEE 802.3bs/cd and OIF CEI-56G IAs 1, 4, and 12 lanes 400G/PAM-4 designs Page 8

9 IEEE P802.3bs / D3.0 Overview of IEEE P802.3bs /D3.0, 10th January 2017 PAM-4 used in 200 Gb/s and 400 Gb/s Operation Name # of lanes Channel (Medium) Reach Signaling Rate (each lane) Modulation Format Reference Receiver Defined in IEEE IEEE P802.3bs / D Gb/s PHY 400 Gb/s PHY Electrical Optical Electrical Optical 200GBASE-DR4 200GBASE-FR4 200GBASE-LR4 200GAUI-8 (formerly CCAUI-8) 200GAUI-4 (formerly CCAUI-4) 400GBASE-SR16 400GBASE-DR4 400GBASE-FR8 400GBASE-LR8 400GAUI-16 (formerly CDAUI-16) 400GAUI-8 (formerly CDAUI-8) 4 Parallel Fibres 4 WDM Lanes (1 Fibre) 4 WDM Lanes (1 Fibre) Parallel Fibres 4 Parallel Fibres 8 WDM Lanes (1 Fibre) 8 WDM Lanes (1 Fibre) 16 8 SM 2m to 500 m GBd PAM4 SM 2m to 2 km GBd PAM4 SM 2m to 10 km GBd PAM4 Chip-to-Chip and Chip-to-Module Chip-to-Chip and Chip-to-Module ~ 25 cm 10.2dB at GHz ~ 25 cm 10.2dB at GHz GBd NRZ GBd PAM4 MM 0.5 m to 100 m (OM4) GBd NRZ SM 2m to 500 m GBd PAM4 SM 2m to 2 km GBd PAM4 SM 2m to 10 km GBd PAM4 Chip-to-Chip and Chip-to-Module Chip-to-Chip and Chip-to-Module ~ 25 cm 10.2dB at GHz ~ 25 cm 10.2dB at GHz GBd NRZ GBd PAM4 TDECQ with 4th Order BT filter, BW GHz TDECQ with 4th Order BT filter, BW GHz TDECQ with 4th Order BT filter, BW GHz 4th Order BT filter, BW 33 GHz 4th Order BT filter, BW 33 GHz TDEC with 4th Order BT filter, BW 12.6 GHz Eye Mask BW GHz TDECQ with 4th Order BT filter, BW GHz TDECQ with 4th Order BT filter, BW GHz TDECQ with 4th Order BT filter, BW GHz 4th Order BT filter, BW 33 GHz 4th Order BT filter, BW 33 GHz Clause 121 Clause 122 Clause 122 Annex 120B/C Annex 120D/E Clause 123 Clause 124 Clause 122 Clause 122 Annex 120B/C Annex 120D/E Recent update (D3.0) includes changes to TDECQ and Jitter measurements Many compliant measurements require: o Clock Recovery, Loop BW 4 MHz (all PAM-4) o Reference Receiver with 4 th Order Bessel-Thomson frequency response 400G/PAM-4 designs Page 9

10 Name # of lanes Channel (Medium) Reach Signaling Rate (each lane) Modulation Format Reference Receiver Defined in IEEE 50GBASE-SR 1 Fibre MM Fibre 0.5 m to 70 m for OM3 0.5 m to 100 m for OM GBd PAM4 TDECQ with 4th Order BT filter, BW 12.6 GHz Clause 138 IEEE P802.3cd / D Gb/s PHY 100 Gb/s PHY Optical Electrical Electrical Optical 50GBASE-FR 1 Fibre SM Fibre 2 m to 2 km GBd PAM4 50GBASE-LR 1 Fibre SM Fibre 2 m to 10 km GBd PAM4 50GBASE-CR 1 Copper Cable > 3 m GBd PAM4 50GBASE-KR 1 Electrical Backplane 30dB at GHz GBd PAM4 100GBASE-DR 1 Fibre SM Fibre 2m to 500 m GBd PAM4 100GBASE-SR2 2 Parallel Fibres MM Fibre 0.5 m to 70 m for OM3 0.5 m to 100 m for OM GBd PAM4 100GBASE-CR2 2 Copper Cable > 3 m GBd PAM4 100GBASE-KR2 2 Electrical Backplane 30dB at GHz GBd PAM4 TDECQ with 4th Order BT filter, BW GHz TDECQ with 4th Order BT filter, BW GHz 4th Order BT filter, BW 33 GHz 4th Order BT filter, BW 33 GHz TDECQ with 4th Order BT filter, BW GHz TDECQ with 4th Order BT filter, BW 12.6 GHz 4th Order BT filter, BW 33 GHz 4th Order BT filter, BW 33 GHz Clause 139 Clause 139 Clause 136 Clause 137 Clause 140 Clause 138 Clause 136 Clause Gb/s PHY IEEE IEEE P802.3cd / / D1.2 D1.1 Overview of IEEE P802.3cd / D1.2, 3rd February 2017 PAM-4 used in 50 Gb/s, 100 Gb/s, and 200 Gb/s Operation NEW! Optical Electrical 200GBASE-SR4 4 Parallel Fibres MM Fibre 0.5 m to 70 m for OM3 0.5 m to 100 m for OM GBd PAM4 200GBASE-CR4 4 Copper Cable > 3 m GBd PAM4 200GBASE-KR4 4 Electrical Backplane 35dB at 12.9GHz GBd PAM4 TDECQ with 4th Order BT filter, BW 12.6 GHz 4th Order BT filter, BW 33 GHz 4th Order BT filter, BW 33 GHz New proposal: 802.3cd adds support for 50/100/200 Gb/s for MM / SM / Copper Cable / Backplane applications Many compliant measurements require: o Clock Recovery, Loop BW 4 MHz (all PAM-4) o Reference Receiver with 4 th Order Bessel-Thomson frequency response 400G/PAM-4 designs Page 10 Clause 138 Clause 136 Clause 137

11 Understanding the application space Typical implementation: Ethernet Switch using 400GBASE-FR8 Optical Link Both IEEE and OIF-CEI are used Switch Card Backplane Line Card 400G-FR8 Module Switch ASIC n Retimer n Retimer n Host ASIC 8 Retimer ROSA TOSA 400G-FR8 Module 8 Retimer ROSA TOSA CEI-56G-VSR PAM-4 or NRZ CEI-56G-LR PAM-4 or enrz CEI-56G-MR PAM-4 or NRZ 400GAUI-8 8 x 26 GBd PAM-4 (8 x 56 Gb/s) 400GBASE-FR8 8 λ WDM in SMF 400G/PAM-4 designs Page 11

12 Patterns Test patterns for PAM-4 encoded signals defined in IEEE P802.3bs JP03A - The JP03A test pattern is a repeating {0,3} sequence (clock) No longer used in 802.3bs/cd. JP03B - The JP03B test pattern is a repeating sequence of {0,3} repeated 15 times followed by {3,0} repeated 16 times (clock with a phase shift) - No longer used in 802.3bs/cd PAM4 Test Patterns Pattern Pattern Description Defined in Clause Square Wave Square wave (8 threes, 8 zeros) PRBS31Q PRBS13Q Scrambled Idle SSPRQ PRBS13Q - The PRBS13Q test pattern is a repeating 8191-symbol sequence formed by Gray coding pairs of bits from two repetitions of the PRBS13 pattern into PAM-4 symbols as described in (Note: PRBS13Q is different from QPRBS13 defined in IEEE (bj) Clause 94) PRBS31Q - The PRBS31Q test pattern is a repeating 2^31-1 symbol sequence formed by Gray coding pairs of bits from two repetitions of the PRBS31 pattern defined in into PAM-4 symbols as described in SSPRQ Short Stress Pattern Random Quaternary. The SSPRQ pattern is a repeating 2^16 1 PAM-4 symbol sequence. Comprised of 4 sequences, each based key stressors from PRBS31. Stressful pattern, but short enough to use advanced analysis tools available on today s T&M tools (e.g. Equalization, Jitter/Noise analysis, etc.) 400G/PAM-4 designs Page 12

13 Compliant Frequency Response (Reference Receiver) Receiver Frequency Response: Scopes have different frequency responses Typical RT Brick wall Response Typical SS Response Will result in different eye/waveform shapes and amplitudes > different measurement results! To achieve 33/40 GHz 4 th Order BT response on a RT scope, must start with > 60 GHz brick wall response To provide more consistency, most standards now specify BW and shape. 4 th Order Bessel-Thomson (BT) Response Step Response (red) Frequency Response (blue) Examples: IEEE P802.3bs /D3.0, 10th January 2017 Clause 120D GAUI-4 or 400GAUI-8 transmitter characteristics: A test system with a fourth-order Bessel-Thomson low-pass response with 33 GHz 3 db bandwidth is to be used for all transmitter signal measurements, unless otherwise specified. CEI-56G-VSR-PAM-4 Section Output Differential Voltage, pk-pk The waveform is observed through a fourth-order Bessel-Thomson response with a 3-dB bandwidth of 40 GHz using a QPRBS13-CEI pattern. 400G/PAM-4 designs Page 13

14 Clock Recovery for PAM-4 Designs Clock Recovery (CR) Recovers a clock for the Rx to use, tracks out some low-frequency jitter Scopes need to emulate CR used in Rx used to track out low-frequency jitter, trigger the scope PAM-4 adds potential complexity Data pattern affects transition density Transitions no longer only at 0V vdiff DSP and analog CDR solutions common OIF-CEI proposal: o 1 detector: 0V crossing o allow all edges that cross to be counted CR Loop BW reduced from 10 MHz to ~ 4 MHz (IEEE 802.3bs/cd and CEI-56G-PAM-4) Instrument Clock Recovery Real-time oscilloscopes use software CR Transition level qualified SW CDR will include 0-3/3-0 and 1-2/2-1 level transitions. Sampling oscilloscopes use hardware CR Existing Keysight HW clock recovery designs work on PAM-4 signals 400G/PAM-4 designs Page 14

15 Output (Transmitter) Characterization: Optical

16 A quick review of legacy 25 GBd NRZ Tx Test What are the key NRZ Tx parameters that get measured? OMA (optical modulation amplitude, difference between the 1 level and 0 level) Extinction ratio (ratio of 1 and 0 level) IEEE participants can access the latest specs on the IEEE website. Tx Eye mask Transmitter and Dispersion Penalty (TDP) IEEE 100GBASE-LR4/ER4 Tx Parameters Reference: IEEE _SECTION6 Clause 78-95, page G/PAM-4 designs Page 16

17 What is TDP and what are its challenges? Transmitter and Dispersion Penalty TDP is the primary spec that defines inter-operability, but it is complex, expensive and time consuming to perform. TDP is very often characterized on early units, and is then correlated to Reference: IEEE _SECTION4 Clause 44-55, page 513 Extinction Ratio, OMA, and Eye Mask. ER, OMA and eye mask are then tested in manufacturing. 400G/PAM-4 designs Page 17

18 Overview of Key Optical PAM-4 Measurements Used in multiple IEEE 802.3bs/cd Clauses What are the key PAM-4 Tx parameters that get measured? Outer Optical Modulation Amplitude Outer Extinction Ratio IEEE participants can access the latest draft specs on the website. Transmitter and dispersion eye closure for PAM-4 (TDECQ) Do you notice anything missing compared to legacy NRZ Tx Specs? No Tx mask test! IEEE 400GBASE-FR8/LR8 Tx Parameters Reference: IEEE P802.3bs /D3.0, 10th January 2017, page G/PAM-4 designs Page 18

19 PAM-4: OMA and Extinction Ratio Extinction ratio measurement is made on specific bits in a specific pattern (outer levels of PRBS13Q or SSPRQ) OMA is constructed from the same symbols and values as extinction ratio OMA = P 3 P o (Average Power) ER = Ave Power P 3 / Ave Power P o (Ratio measurement in db) Newer T&M software provides these optical measurements directly (Keysight 86100D-9FP/9TP, integrated into FlexDCA FW) Reference: IEEE P802.3bs /D2.1, 6th October 2016, page G/PAM-4 designs Page 19

20 Transmitter and dispersion eye closure for PAM-4 (TDECQ) TDECQ is a measure of each optical transmitter's vertical eye closure when transmitted through a worst case optical channel (TDECQ units = db) using SSPRQ pattern. Generate SSPRQ pattern (~ 2^16 symbols) Reference Receiver: 4 th order Bessel-Thomson low-pass filter (Oscilloscope noise measured and mathematically backed out per Standard). MM: 12.6 GHz BW (26.56 GBd) o No Pol. controller, fiber SM: GHz BW (26.56 GBd) 86100D DCA-X Scope SM: GHz BW (53 GBd) CR PLL BW 4 MHz, Slope 20 db/dec (1 st Order, no peaking) Equalizer (5 tap, T/2 spaced, FFE) Where: Qt = (target SER) R = noise term Targeted samples on PAM-4 eye diagram. Reference: IEEE P802.3bs /D2.2, 28th November 2016, Figure 121-5, Page G/PAM-4 designs Page 20

21 Keysight TDECQ implementation Option 9FP / 9TP (includes all PAM-4 measurements), Option TFP / TTP (only TDEC and TDECQ) TDECQ equalizer function: o Designed according to IEEE 802.3bs o Uses SSPRQ test pattern required by 802.3bs standard (but SW will operate on other patterns too) Automatically optimizes tap settings to minimize TDECQ value o Supports user tap values also Preserves uncorrelated signal content as required by IEEE 802.3bs 400G/PAM-4 designs Page 21

22 TDECQ measurement setup Simple and fast: Two clicks to execute the measurement OMA required for the TDECQ calculation: OMA is measured according to 802.3bs Alternatively, OMA can be made on a separate measurement and applied to the TDECQ calculation 400G/PAM-4 designs Page 22

23 TDECQ, OMA and ER all available from the TDECQ process Extinction ratio and OMA are derived from the 0 and 3 levels of the transmitter output Specific bit sequences are used Waveform at transmitter output TDECQ derived from the equalized waveform Uses OMA from the unequalized waveform (may change to equalized waveform) Waveform at equalizer output Keysight TDECQ solution: Simple, integrated, fast, accurate, and very repeatable. 400G/PAM-4 designs Page 23

24 Early TDECQ Findings TDECQ appears to be a valid method to predict BER performance Measured TDECQ vs. Tx BW Correlation between BER Penalty and TDECQ TDECQ degrades with a reduction in Tx BW Consistent trend in measured TDECQ change and BER penalty Results from a joint experiment performed by Keysight/Intel/MACOM reported to IEEE 802.3cd. 400G/PAM-4 designs Page 24

25 53 Gbaud (106 Gb/s/PRBS13Q) Optical PAM-4 analysis Measured using Keysight 86116C Optical Module (Option 041/IRC) 23 GHz with FRC (-3000) 25.8 GHz TX BW 14.5 GHz TX BW TDECQ = 0.73 db 33 GHz with FRC (-3000) TDECQ = 2.58 db TDECQ degrades with a reduction in Tx BW 400G/PAM-4 designs Page 25

26 Keysight Oscilloscope Solutions for Optical Test Full coverage for all optical PAM-4 applications (using existing DCA HW solutions). New N1092A/B/D DCA-M 86100D DCA-X with 86105D/86115D module 86100D DCA-X with 86116C module GBd optical channels Multimode and Single-Mode 1, 2 or 4 channels Highest sensitivity on the market (lowest noise receiver) Fastest sampling combined with 160fs typical trigger jitter Lowest cost solution Ideal frequency response (SIRC) PAM-4 analysis with TDECQ (Option 9FP/9TP) 8.5 GBd to 28 GBd Multimode and Single-Mode 1 or 34 GHz optical channels (1 to 4 optical per mainframe) 50 GHz Electrical Channel Ideal frequency response (SIRC) < 100 fs rms timebase jitter (86100D-PTB) PAM-4 analysis with TDECQ (Option 9FP/9TP) 25/26/28GBd or 53/56 GBd Single-Mode optical channel per module 80 GHz Electrical Channel Ideal frequency response (SIRC) < 100 fs rms timebase jitter (86100D-PTB) PAM-4 analysis with TDECQ (Option 9FP/9TP) N1077A CR provides compliant electrical/optical (SM/MM) clock recovery to 32 GBd. 400G/PAM-4 designs Page 26

27 Keysight Real-time oscilloscope with O/E front-end Keysight N7004A 33 GHz O/E converter A fully-integrated optical-to-electrical (O/E) converter for measuring up to 28 GBd optical signals using Infiniium real-time scopes. o Compatible with Infiniium V-Series, 90000X/Q, and Z Series. System level R&D debug and troubleshooting Reference receiver testing (filtered response) and unfiltered characterization of optical transmitters Scope SW includes built-in optical measurements 400G/PAM-4 designs Page 27

28 Output (Transmitter) Characterization: Electrical

29 Key Electrical Measurements IEEE 802.3bs Annex 120D 200GAUI-4 and 400GAUI-8 What are the key PAM-4 Tx parameters that get measured? Output waveform o Level Separation Mismatch Ratio Signal-to-noise-and-distortion ratio (SNDR) Output Jitter o Jrms o J4 o Even-Odd Jitter (EOJ) IEEE participants can access the latest draft specs on the website. Reference: IEEE P802.3bs /D3.0, 10th January 2017, page G/PAM-4 designs Page 29

30 Transmitter Linearity at TP0a (IEEE) 120D Level Separation Mismatch Ratio, R LM (200GAUI-4 and 400GAUI-8) How evenly spaced are the PAM-4 levels? Significant change in definition from IEEE 802.3bj (100GBase-KP4) Clause 94 Defined as a function of the mean signal level transmitted for each PAM-4 symbol level. Measurement Setup: Receiver: 4 th Order Bessel-Thomson low-pass filter with 33 GHz BW CR PLL BW 4 MHz and a slope of 20 db/decade Tested using PRBS13Q (no longer uses the stair-step pattern) Vmid V 3 V 2 V 1 V 0 ES = Effective Symbol Level R LM = min ((3 x ES1), (3 x ES2), (2 3 x ES1), (2 3 x ES2) 400G/PAM-4 designs Page 30

31 Signal-to-noise and distortion ratio (SNDR) IEEE P802.3bs /D3.0, 10th January 2017, Clause 120D Procedure: 1. Measured at the output of TX with all lanes enabled 2. Capture PRBS13Q waveform (lane under test) 3. Import into math program and perform matrix math a. Compute: i. Linear fit pulse response, p(k) ii. o Pmax is the max value of p(k) Linear fit error waveform, e(k) o σ e is the standard deviation of e(k) b. Measure RMS deviation from mean voltage on the flattest portion of at least 6 consecutive PAM-4 symbols i. Compute σ n c. Calculate SNDR Measurement Setup: Receiver: 4 th Order Bessel-Thomson low-pass filter with 33 GHz BW CR PLL BW 4 MHz and a slope of 20 db/decade Note - SNDR is very sensitive to noise measurement (ensure to use a low noise scope) 400G/PAM-4 designs Page 31

32 Output Jitter at TP0a 200GAUI-4 and 400GAUI-8 transmitter characteristics at TP0a New jitter measurement methodology Under o First defined in IEEE P802.3bs /D2.2, Development 28th November 2016 in ad hoc o Accounts for Tx designs that use different clock group buffers (uncorrelated jitter) for MSB and LSB J4 and JRMS jitter o Measure RJ/PJ on 12 specific transitions using a PRBS13Q pattern (exclude correlated jitter). o Rise: 0 to 3, 1 to 2, 0 to 1, 2 to 3, 0 to 2, 1 to 3 o Fall: 3 to 0, 2 to 1, 1 to 0, 3 to 2, 2 to 0, 3 to 1 PAM4 TX Amplitude Edge Model Amplitude-to-Time Sample 1 (Jitter) transfer function ~ 100% efficiency Jitter PAM4 Even-Odd Jitter (EOJ) o Measured on PRBS13Q (3 repeats) o Max from measurements on all 12 edges Measurement Setup: Receiver: 4 th Order Bessel-Thomson low-pass filter with 33 GHz BW CR PLL BW 4 MHz and a slope of 20 db/decade Keysight plans to implement an optimized test methodology after the Standard becomes more stable. Sample 2 Ideal edge position 400G/PAM-4 designs Page 32

33 Key Electrical PAM-4 Measurements at TP1a Annex 120E, Chip-to-Module, measured at TP1a (200GAUI-4 and 400GAUI-8) Key New/Updated Measurements: Eye Symmetry Mask Width Eye Height, differential Transition Time (20%-80%) IEEE participants can access the latest draft specs on the website. Reference: IEEE P802.3bs /D2.2, 28th November 2016, page 369 Measurement Setup: Receiver: 4 th Order Bessel-Thomson low-pass filter with 33 GHz BW Clock Recovery: 4MHz, slope 20db/dec 400G/PAM-4 designs Page 33

34 Eye symmetry mask width (ESMW) at TP1a C2m, 200GAUI-4 and 400GAUI-8 at TP1a, Reference 120E.4.2 ESMW verifies proper timing/alignment of all 3 eyes (skew) Upper, Middle, and Lower eye must extend beyond mask Determine center of middle eye (TCmid) using 10E horizontal openings of the middle eye at VCmid, the upper eye at VCupp, and of the lower eye at VClow must all extend beyond the EW5 mask. VCupp Measurement Setup: Ref Rcvr: 4 th order BT, 33 GHz BW CR: 4 MHz BW, 20dB/dec Use CTLE (3 pole) PRBS13Q pattern VCmid VClow 400G/PAM-4 designs Page 34

35 Host output eye height (TP1a) C2m, 200GAUI-4 and 400GAUI-8 at TP1a, EW Reference 120E E Host output eye width and eye height Measure EW of all 3 PAM-4 1E-5 using methodology outlined in 120E.4.2 Measurement Setup: Ref Rcvr: 4 th order BT, 33 GHz BW CR: 4 MHz BW, 20dB/dec Use CTLE (3 pole) defined in 120E PRBS13Q pattern 400G/PAM-4 designs Page 35

36 Transition Times at TP1a Defined in Annex 120E (120E.3.1.5) Gray Code Level 3 Use PRBS13Q pattern Measure on isolated 0 -> 3 and 3 -> (rise) and (fall) 20-80% transition times (rise and fall time) Measured using 33 GHz LPF ( such as Bessel-Thomson response ) PAM-4 Symbol /3 1-1/3 0-1 Use FlexDCA s Find Bit Sequence feature to quickly locate the correct edge 400G/PAM-4 designs Page 36

37 Key Electrical PAM-4 Measurements at TP4 Annex 120E, Chip-to-Module, measured at TP4 (200GAUI-4 and 400GAUI-8 ) Key New/Updated Measurements: Near-end and Far-end o Eye Symmetry Mask Width (ESMW) o Eye Width and Eye 1E-5 IEEE members can access the latest draft specs on the IEEE website. Measurement Setup: Receiver: 4 th Order Bessel-Thomson low-pass filter with 33 GHz BW Clock Recovery: 4MHz, slope 20db/dec Reference: IEEE P802.3bs /D2.2, 28th November 2016, page 373/4 400G/PAM-4 designs Page 37

38 Host output eye width and eye height (TP4) 120E Module output eye width and eye height Measure EW/EH of all 3 PAM-4 1E-5 using methodology outlined in 120E.4.2 o Measure Near-end EW5/EH5 (with Max 3dB CTLE peaking) o Measure Far-end after convolving with loss channel (~ 6.4 db loss at Nyquist defined in , use any CTLE per Table 120E-2 (max 9dB) Measurement Setup: o Reference Rcvr: 4 th order BT, 33 GHz BW o CR: 4 MHz BW, 20dB/dec Hupp Reference: Center of Middle Eye Hmid Hlow Vupp Vmid Vlow o Use CTLE (3 pole) defined in 120E Measure here (TP4) o PRBS13Q pattern CTLE Loss channel Input (TP4) Calculate EW5/EH5 spec here Post process 400G/PAM-4 designs Page 38

39 CEI-56G-VSR-PAM-4 Very Short Reach (VSR) Interface Working draft dated June 3, 2016 Overview: 56 Gb/s chip-to-module PAM-4 electrical interface (18.0 to 29.0 Gsym/s) Up to 10.0 db loss at the Nyquist frequency, including one connector. Drives 100 mm (min) of host PCB trace plus one connector and 50 mm (min) of module PCB trace. Raw BER of 1E-6 per lane; FEC corrects to 1E-15 or better. CEI-56G has similar PAM-4 measurements and methodologies to those defined in IEEE 802.3bs. Examples include: Eye Width (1E-6) Eye Height (1E-6) SNDR Transition Times Eye Symmetry Mask Width Eye Linearity (2 methods) 400G/PAM-4 designs Page 39

40 Eye Width and Eye Height test at TP1A, TP4 EW6 and EH6 for Host and Module output Reference Point for all EW6/EH6: Tmid = the midpoint of the maximum horizontal eye opening of the 1E-3 inner eye contour of the middle eye Xtalk required on all co-/counter-propagating lanes; use QPRBS13-CEI, or QPRBS31-CEI, or a valid CEI signal. Test Pattern = QPRBS13-CEI CRU = 1 st order with fb/6640 3dB BW (same as IEEE 802.3bs) e.g GBd/6640 = 4 MHz Apply Reference CTLE Near-end EW6, EH6 (CTLE TP1a max 9 db, TP4 max 2 db) Far-end EW6, EH6 convolves emulated test channel, ~7 db loss at fb/2 (CTLE max 9 db) Figure 16-7: TP1a and TP4 Eye Width, Eye Height and Eye Amplitude Reference: Working draft of oif , dated Nov 18, 2016, page G/PAM-4 designs Page 40

41 Transmitter Linearity Two Methods defined in CEI-56G-VSR-PAM-4, Nov 18, 2016 Eye Linearity (Section 16.C.4.2) ratio of min to max PAM-4 eye amplitudes Used at TP1A and TP4 Eye linearity = min(avupp, AVmid, AVlow) max(avupp, AVmid, AVlow) Transmitter Linearity defined as a function of the mean signal level transmitted for each PAM-4 symbol (CEI-56G-VSR-PAM-4 Appendix 16.C.4.3) Same equation as that used in IEEE P802.3bs /D2.2, 28th November 2016 (Refer to Level Separation Mismatch Ratio, R LM ) Used in other CEI Clauses (not VSR-PAM-4) RLM = min((3 x ES1), (3 x ES2), (2-3 x ES1), (2-3 x ES2)) Reference: Working draft of oif , Nov 18, 2016, page 32. ES = Effective Symbol Level Reference: Figure 16-7 from oif , dated Nov 18, 2016, page G/PAM-4 designs Page 41

42 Keysight Electrical Solutions Used to characterize/troubleshoot PAM-4 Electrical Tx Designs 400G/PAM-4 designs Page 42

43 Symbol Error Ratio Measurements (BER/SER) using RT Scope View waveform and locate errors. Troubleshoot Reed-Solomon FEC failures. Cumulative SER/BER Navigate easily to the occurrence of each symbol error Identifies Burst Errors in Captured Waveforms 400G/PAM-4 designs Page 43

44 Built-in PAM-4 Measurement Capability PAM-4 Analysis SW options for Keysight real-time and sampling scope platforms: 86100D-9FP for the 86100D DCA-X N8827A/B PAM-4 Analysis Software for RT scopes We are actively updating PAM-4 algorithms as the Standards evolve. Updates will be included in future FW releases. 400G/PAM-4 designs Page 44

45 PAM-4 Measurement Apps for Keysight Scopes Pre-Compliance SW Apps for emerging Standards using PAM-4 N1085A PAM-4 Measurement App for Ethernet and OIF-CEI (for the 86100D DCA-X) N8836A PAM-4 Measurement App for Ethernet and OIF-CEI (for Infiniium real-time scopes) We are actively updating PAM-4 algorithms as the Standards evolve. Updates will be included in future SW releases. 400G/PAM-4 designs Page 45

46 Keysight Oscilloscope Solutions - Electrical Electrical Sampling Scope (includes built-in clock recovery and precision timebase) Keysight 86100D DCA-X with 86108B Channels: 2 Bandwidth: 50 GHz Jitter: <45 fs rms typ. Electrical Clock Recovery integrated HW Clock Recovery works with PAM-N signals up to 32 Gbaud 86100D-9FP PAM-4 Analysis SW (works with any DCA module, optical or electrical) N1085A PAM-4 Pre-Compliance SW NOTE 75 / 85 / 100+ GHZ BW remote head modules also available. Electrical Real-time Scope Keysight DSO Z-Series Channels 2-4 Bandwidth: up to 63 GHz Sample Rate: Up to 160 GSa/s PAM-4 Serial Data Analysis Wizard Software Clock Recovery (specify transitions for CR) N8827A/B PAM-4 Analysis SW N8836A PAM-4 Pre-Compliance SW PAM-4 SER/BER Error Capture and Decode capabilities using single-shot capture 400G/PAM-4 designs Page 46

47 Comparing the impact of a scope s intrinsic random noise (RN) on 56 GBaud (112 Gb/s) PAM-4 signals Real-time scope (63 GHz Z-Series) RN = random noise S = Slew Rate, dv/dt Equivalent-time scope (86100D DCA-X) 400G/PAM-4 designs Page 47

48 System Board Level Chip Oscilloscope Solutions for 100G/400G R&D Verification Compliance Manufacturing Sampling Scopes (SS), DCA Best for validating/characterizing PAM-4 designs For applications that place top priority on waveform precision. Highest Fidelity Low noise Ultra-low jitter High Bandwidth Highest Resolution (14-16 bits) Modular Platform Electrical Optical TDR/TDT Lowest price for same BW 86100D-9FP PAM-4 Analysis SW N1085A PAM-4 Pre-Compliance SW Real-time Scopes (RT) Best for troubleshooting PAM-4 designs The most versatile tool for all areas of high-speed digital communications Best for troubleshooting Captures one-time (glitch) events No explicit trigger required Does not require repetitive signals for pattern waveform measurements. N7004A Optical-to-Electrical Converter N8827A/B PAM-4 Analysis SW N8836A PAM-4 Pre-Compliance SW PAM-4 SER/BER Error Capture and Decode capabilities 400G/PAM-4 designs Page 48

49 PAM-4 Receiver Test

50 PAM-4 Receiver Test Challenges Transmitter Equalization Level Non-linearity: Input Linearity Testing Linearity Margin Testing BER vs. Symbol levels Long (Q)PRBS(Q) patterns Stressed Input Test for Host & Module Receiver Interference Tolerance Loop Closure for RX Tolerance Testing NRZ and PAM-4 signaling on same RX input 400G/PAM-4 designs Page 50

51 Test Challenge: PAM-4 TX Equalization TX EQ pre-distorts the transmitter output to emphasize the high frequency portions of the signal and/or de-emphasize the low frequency portions PAM-4 signaling makes TX equalization even more important due to intrinsic DDJ and reduced SNR 32 Gbaud PAM-4 Eye before and after channel: Channel Channel 400G/PAM-4 designs Page 51

52 Test Challenge: PAM-4 Input Linearity Test CEI standard defines a new input test for PAM-4: ability to tolerate level non-linearities, current draft proposes eye amplitudes of up to 0.67 A Max. But when using a 2 channel pattern generator with PAM-4 combiner, the resulting levels cannot not be varied individually. What to do? This setup does not work here: PAM-4 eyes can show a level separation mismatch: 0.67 A Max A Max 400G/PAM-4 designs Page 52

53 Test Challenge: Linearity margin test Margin test steps through increasing degrees of stress until link failure (BER worse than target for FEC, - not error free) Design the stress to emulate the impairment Two general linearity impairment classes in PAM-4 1. DAC bit weighting error 2. Compression/Expansion in linear stage 400G/PAM-4 designs Page 53

54 Test Challenge: BER vs Symbol Level Receiver circuits can exhibit non-linearity effects similar to TX effects Understanding the BER vs. Symbol level performance of the receiver is important Varying PG TX signal levels to compensate for these RX effects can reduce the time to debug link BER issues 400G/PAM-4 designs Page 54

55 Test Challenge: Long (Q)PRBS(Q) patterns NRZ BERT architectures have memory-based pattern length limitations when applied to PAM-4 signaling QPRBS31/PRBS31Q will not fit in pattern memory 400G/PAM-4 designs Page 55

56 Test Challenge: Stressed Input Test for Host & Module Example: OIF CEI-56G-VSR-PAM-4 How to inject simultaneously and calibrate mix of What is UBHPJ? (BUJ) What is UUGJ? (RJ) SJ is multi-ui LF SJ and HF SJ up to 200MHz Challenges: How to emulate x-talk? Fast tr Asynchronous or synchronous with phase control? Challenges: Compensate loss TP4a Emulate TX de-emphasis PRBS31 for NRZ QPRBS13 or? for PAM-4 ISI channel (channel loss depends on distance) Reference: OIF VEI-56G-VSR-PAMR Very Short Reach Interface, draft Nov 18, 2016 p20 Generally: CEI G draft specs keep changing till finally released! Note: the validity of emulating the effect of the DUT s counter opposing output during test via TCB is questionable (the coupling is not defined)! 400G/PAM-4 designs Page 56

57 Test Challenge: Receiver Interference Tolerance COM Method referenced by OIF CEI-56G-LR/MR-PAM-4 (draft) The Channel Operating Margin (COM) is a figure of merit for a channel derived from a measurement of its scattering parameters. COM is related to the ratio of a calculated signal amplitude to a calculated noise amplitude = 20log 10 (A s /A ni ). Source: IEEE 802.3bj -2014, Annex 93A The channel noise source emulates crosstalk and nonequalize-able signal distortions introduced by a channel. Challenge: the transmitter output, as measured at TP0a, meets all transmitter specifications: Pre- and post- cursor peaking ratio The ISI channel emulates the frequency dependent loss of a backplane channel. It is Gaussian with a crest factor of at least 4. as of CEI-56G-LR-PAM Challenge: Differential adders cause loss +skew +reflections. Reference: IEEE Annex 93C Figure 93C-2 Interference tolerance test setup Challenge: get all data needed for MATLAB COM model input file to calculate desired eye height correctly. 400G/PAM-4 designs Page 57

58 Test Challenge: Loop Closure for RX Tolerance Loopback to BERT error detector is traditional method Some DUT s do not have loopback capability Some DUT s incorporate on-chip error detectors Some interfaces operate at high BER levels (e.g. 1E-5) and correct with FEC 400G/PAM-4 designs Page 58

59 Test Challenge: NRZ and PAM-4 on same RX input Some SERDES receivers have flexible RX inputs that can be used for both PAM-4 and NRZ signaling NRZ BERT architectures require significant recabling/recalibration when changing from NRZ to PAM-4 400G/PAM-4 designs Page 59

60 M8040A 64 GBaud High-performance BERT Key capabilities: - Highly integrated BERT, AXIe based - Accurate physical layer characterization and compliance test of next generation digital highspeed I/Os with NRZ and PAM-4 data formats - Control via M8070A system software for M8000 Where used: - 400GbE, 200GbE, CEI-56G - Input (RX) characterization and compliance test - For PAM-4 and NRZ signals up to 64 GBaud Pattern Generator (M8045A) Single or dual 32/64 GBaud NRZ/PAM-4 Built-in de-emphasis Clean and jittered data patterns and clocks Remote head for close connection to DUT NRZ and PAM-4 is switchable by software Error Detector (M8046A) 32/64* GBaud error detector for PAM-4 and NRZ * second release 400G/PAM-4 designs Page 60

61 Test Challenge: PAM-4 TX Equalization Solved Using M8045A Pattern Generator 4-tap TXEQ controls Channel Channel 400G/PAM-4 designs Page 61

62 Test Challenge: PAM-4 Input Linearity Test and Linearity Margin Test Solved Using M8045A Pattern Generator PAM-4 symbol 1 and 2 level controls 400G/PAM-4 designs Page 62

63 Test Challenge: BER vs Symbol Level Solved Using M8046A Error Detector BER vs. symbol level analysis window All errors found on level 3 400G/PAM-4 designs Page 63

64 Test Challenge: Long (Q)PRBS(Q) patterns Solved Using M8046A Error Detector native PAM-4 analysis M8046A samples all three PAM-4 thresholds simultaneously Detecting 1 0 Threshold V upp = 3 = 0 or 1 or 2? Threshold V Data mid = 2 or 3? = 0 or 1? In Threshold V low = 1 or 2 or 3? = 0 PAM-4 Vupp Vmid Vlow Gray Only a true PAM-4 error analyzer can provide a PAM-4 symbol error rate. Error ratios down to or errorfree can be measured even for long PRBS or QPRBS-31 patterns. Errored 0,1,2,3 symbols can be counted seperately for further debugging. 400G/PAM-4 designs Page 64

65 Test Challenge: Stressed Input Test for Host & Module Solved Using M8045A flexible jitter sources and second PG channel for crosstalk 400G/PAM-4 designs Page 65

66 Test Challenge: Receiver Interference Tolerance Solved Using M8195A or -96A AWG as RI/SI source in same chassis, same GUI Option to use AWG for RI/SI source, eye-skew Loopback to ED PAM-4 and NRZ Inpu RI/SI t (RX) + diff und PAM-4 or NRZ Remote er head test M8196A complements input test setup when used as: Random/ sinusoidal interference source with directional couplers PAM-4 generator to emulate horizontally skewed eyes Economic PAM-4 generator (see appendix for restrictions) 400G/PAM-4 designs Page 66

67 Test Challenge: Loop Closure for RX Tolerance Solved 1 Using M8046A Error Detector for DUT s with loopback PAM-4 or NRZ Loopback to ED 2 PAM-4 or NRZ Remote head 2 Input (RX) under test Key features analyzer: 1 analyzer channel per module (M8046A, 1U) Symbol rates: 2 to 32 Gb/s NRZ and 32 GBaud PAM-4 2 to 64 Gb/s NRZ and 64 GBaud PAM-4* Detects NRZ and PAM-4 signals without power splitters True real-time symbol error rate for PAM-4 without post-processing Full sampling even for long PRBS and low BERs, e.g Jitter tolerance measurements *64 Gbaud version comes in a second release 400G/PAM-4 designs Page 67

68 Test Challenge: Loop Closure for RX Tolerance Solved 2,3 Access via M8070A Software: 2: On-chip error counters: On chip ED can be used for integrated measurements, such as JTOL M8070A-1TP/-1NP are available as transportable and as network license Python-script based interface into M8070A software 3: Realtime Scope based error counters: For BERs 10-5, 10-6, 10-7 Unfold into waveform upon error Trigger on burst error Cumulative and per acquisition Unknown expected pattern by capture Requires Infiniium SW rev and N8836A DUT error counter Python Update Aug G/PAM-4 designs Page 68

69 Test Challenge: NRZ and PAM-4 on same DUT-Solved! Using M8040A Native NRZ/PAM-4 Capabilities switch PG/ED on the fly Custom coding too! 400G/PAM-4 designs Page 69

70 M8000 Series of BER Test Solutions Now: Extension to 400GbE: PAM-4 & NRZ, 64 GBaud Highly integrated and scalable for simplified, time efficient testing M8040A PAM-4 and NRZ 64 GBaud, 1-2 channel High-performance NRZ BERT M8000 Series of BER Test Solutions 16 / 32 Gb/s, 1-4 channels M8195A AWG, 4 channel Highly integrated 16 Gb/s J-BERT M8020A 1-4 channel 32 Gb/s J-BERT M8020A and M8062A M8030A 10 channel Master your next design 400G/PAM-4 designs Page 70

71 Summary Transition from NRZ to PAM-4 is revolutionary Many new both electrical and optical links Required Output (Tx) measurements and Input (Rx) stress types are changing New eye measurements for PAM-4 Output tests (e.g. TDECQ, JRMS, J4, ) Linearity added to stressed Input testing New tools are needed for characterizing and troubleshooting links using FEC Learn more on the web at: 400G/PAM-4 designs Page 71

72 400G/PAM-4 designs Page 72

73 Partnering with Keysight will speed your PAM-4 transition Keysight helps you master your PAM-4 designs by reducing the complexity of characterization and compliance testing with tools for: Simulation ADS and SystemVue software Output (Tx) Characterization - Oscilloscopes Keysight DSAX 63 GHz real-time oscilloscope o N8827A PAM-4 Measurement Tool With BER o N8836A PAM-4 Measurement Application for Ethernet and OIF-CEI NEW! NEW! Keysight 86100D DCA-X sampling oscilloscope o 86100D-9FP PAM-4 Analysis Software o N1085A PAM-4 Measurement Application for Ethernet and OIF-CEI Keysight N1092x DCA-M sampling oscilloscope Input (Rx) Characterization - BERTs: Keysight M8040A 64 GBaud High Performance BERT 400G/PAM-4 designs Page 73

74 Acronyms c2c = Chip-to-Chip c2m = Chip-to-Module BER = Bit Error Ratio BUJ = Bounded Uncorrelated Jitter (used to emulate crosstalk) DUT = Device Under Test EW = Eye Width EH = Eye Height FEC = Forward Error Correction FFE = Feed-Forward Equalizer NRZ = Non-Return to Zero (Refers to 2 level signaling or PAM-2) PAM-n = Pulse Amplitude Modulation, where n = number of levels RJ = Random Jitter RS = Reed-Solomon SER = Symbol Error Ratio SIRC = System Impulse Response Correction SJ = Sinusoidal Jitter SMF/MM F Single-mode fiber, Multimode fiber TDP = Transmitter and Dispersion Penalty TDEC = Transmitter and Dispersion Eye Closure TDECQ = Transmitter and dispersion eye closure quaternary (for PAM-4) 400G/PAM-4 designs Page 74

75 M8040A 64 GBaud High-performance BERT Master your 400 G design Highly integrated for simplified RX test setup True PAM-4 error detector for repeatable results Scalable NRZ/ PAM-4, 32/ 64 GBaud 400G/PAM-4 designs Page 75