Micram DAC10001 and DAC GS/s Digital to Analog Converter System. Data Sheet

Transcription

1 Micram DAC10001 and DAC GS/s Digital to Analog Converter Data Sheet 100 GS/s Sample rate per channel Single and Dual Channel s 35 GHz Analog Bandwidth (typical) Very fast (<7 ps) rise time Low (<100 fs) typical intrinsic RMS jitter 1.3 V maximum differential output voltage Pristine signal integrity

2 DAC10001 and DAC10002 Performance Silicon Germanium Technology Single and Dual differential channels 35 GHz Analogue Bandwidth (-3 db point) 6 bits vertical resolution Rise time (20%-80%) < 7 ps without frequency response compensation Ultra low intrinsic jitter (RJ< 100 fs) Sample Rate up to 100 GS/s on each channel Automatic channel to channel syncronization Output voltage up to 1.3 Vdiff pk-pk LAN controlled with simple Matlab Flexible, powerful and expandable Micram DAC 4 digial-to-analog Si-Ge converter - the heart of the DAC10001 and DAC10002 For visionary developers working to create the next generation of high speed communications technology, the Micram DAC10001 and DAC10002 s delivers truly ultrafast signal generator performance with the highest Analogue Bandwith in the market. Powered by the world record-setting Micram DAC4 UltraFastSiGe digital to analog converter, the DAC10001 and DAC10002 systems enable researchers and engineers to generate high order complex modulation, such as 32- QAM, 64-QAM, OFDM and advanced 4D formats, at data rates never previously achieved. Example DAC10001 system output at 64 Gb/s, PRBS-7 sampled at 64 GS/s (1 sample/symbol) Example DAC10001 system output at 128 Gb/s, PAM-4 showing fast rise and fall times and extremely low jitter. Signal generated with 64 GS/s Sample Rate (1 sample/ symbol) and optimized by simple 2-tap < 10% preemphasis Example: 50 Gb/s PRBS 7 generated at 100 GS/s (2 samples/symbol) with FIR filtering applied for channel precompensation Page 2

3 Target Applications: NRZ, PAM-4 and PAM-8 Signal Generation for: - Data rates up to 100 Gbps - 64G/112G Fibre Channel - 50 Gigabit Ethernet - Infiniband-HDR - OIF CEI - 56G Gigabit Ethernet: IEEE 802.3bj and 200 Gigabit Ethernet: IEEE 802.3bs Electrical 2-fold oversampled 50 GBd 64-QAM (300 Gb/s) generated by DAC Board Block Diagram Example: DAC10001 output of a 64 Gb/s PAM-4 sampled at 64 GS/s (2 samples / symbol) The DAC10002 includes electronical circuitry to facilitate a semi-automatic synchronization of 2 data output channels. Example: 150 Gb/s PAM-8 waveform generated at 100 GS/s sample rate (2 samples/symbol) and FIR filtering applied for channel precompensation DAC10002 board with two DAC4 modules on board for dual channel (I and Q) signal generation Page 3

4 DAC10001 and DAC10002 Specifications DAC10001 and DAC10002 Specifications Clocking requirement Clock Input Frequency Minimum Clock Power Input type Impedance Connector Trigger Output Maximum Output Frequency Half Rate, 12.5 GHz to 50 GHz 0 dbm Single Ended 50 Ω nominal, DC-coupled 1.85 mm Divide Ratio /1, /2, /4 Output type Impedance Amplitude Connector 50 GHz (fs/2), 25 GHz (fs/4), 12.5 GHz (fs/8) Differential 50 Ω nominal 400 mv typical 1.85 mm DAC10001 and DAC10002 Analogue Bandwidth plots Data Output Number of Channels Analogue Bandwidth (-3dB) Output Type Data Ouput Connectors Sample Rate DAC Resolution Data output ENOB Sample Memory Signaling 1 (DAC10001) or 2 (DAC10002) 35 GHz derived from full-scale Step Response Single ended or differential 1.85 mm (V connectors) GS/s 6 bits, non-interleaved Differential, DC coupled > GHz 524,288 Samples / channel NRZ and Multilevel PRBS patterns (NRZ) PRBS 2 n -1, n=7, 9, 10, 11 Multi level Channel to Channel Skew Resolution Channel to Channel Skew control Output Amplitude Vertical Resolution Rms Jitter Rise/fall times (20%-80%) Output Impedance PAM-4 & PAM-8 < 100 fs Manual or Channel to Channel Calibration Sequence with optional DUAL_DAC10002_ Ch2Ch Syncronization kit 400 mv to 1300 mv pk-pk differential 7.94 mv (= 500mV/(2^6-1)) < 100 fs typical on PRBS11 64 Gbps < 7 ps typical (uncorrected) DAC10001 and DAC10002 ENOB plot 50 Ohm, 100 Ohm differential (typical) DAC4 Frequency Response (positive edge top and negative edge bottom). Plots are derived from full-scale Step Response with sample rate set to 100 GS/s and 500 mv fullscale data output amplitude. Page 4 DAC4 ENOB plot calculated with Sine wave Synthesis Method and sample rate set to 100 GS/s. Note that Sinc Roll-off NOT de-embedded and ENoB=(SINAD-1.76)/6.02)

5 DAC10001 and DAC10002 Internal Memory Requirement Memory Length Memory Structure Minimum Waveform Length 524,288 points / channel 256 points x 2048 segments 256 points Record Length M M = (1, 2,..., 2048) x 256 Maximum Memory Length determines the following constraints PRBS Pattern PAM-4 Maximum order PAM-8 Maximum order PRBS7, PRBS 9 and PRBS General Control software Interfaces Included power supply Operating temperature Dimensions (W x H x D) Shipping Weight Warranty Included Accessories Requires PC running Windows OS Version 7 or later and Matlab version R2013 (no Matlab Tools box required) or later 10/100M Ethernet, USB 100 V to 240 V AC, 12 Volt DC, Hz, 10 C to 30 C Bench top mm H x 449 mm W x 435 mm D (5.25 H x W x D) 8.2 kg including hard transit case, power supply and power cord. 1 year Standard Limited Warranty. Matlab Application Programming Interface The DAC10001 and DAC10002 board level systems are fully controlled, programmed and calibrated via Matlab API. Micram's Matlab API included functions and sample scripts: AC 110/240 Volt, 12 Volt DC External Power Adapter User guide with Matlab programing API source code DAC4 calibration files for optimal DC characteristic. The provided files are DAC Serial Number specific. Calibration tables are generated from final module test and calibration procedure. Metal Base Plate Waveform Generator (NRZ and Multilevel signals) Waveform upload functions with automatic waveform memory's constrain adjustment Start and Stop waveform Generation Upload DAC calibration tables Duty Cycle control for even/odd Eye Symmetry Sample Rate and Output Voltage Control Channel to Channel Syncronization for multiple channel systems Slew Rate Control Upload and apply custom filter coefficients to waveforms for channel de-embedding Samples of board set up scripts Page 5

6 Ordering Information Other Micram products DAC10001 Single Channel 100 GS/s DAC4 board system. 1 year warranty included DAC7201 Single Channel 72 GS/s DAC3 DAC10002 DAC W DAC W CLK_DUAL_ DAC10002 CLK_QUAD_ DAC10002 Dual Channel 100 GS/s DAC4 Board system. 1 year warranty included 3 years total warranty for DAC10001 system 3 years total warranty for DAC10002 system Clock Distributor for Dual Channel DAC configuration (DAC10002). Clock Synthesizer is not included. Clock Distributor for Quad Channel DAC configuration (requires qty two DAC systems). Clock Synthesizer is not included. DAC7202 ADC3402 DAC3401 DAC3402 MX2180 CDR8086 DFF60/DFF30 CD3 Dual Channel 72 GS/s DAC3 Dual Channel 34 GS/s ADC acquisition system Single Channel 34 GS/s DAC2 Dual Channel 34 GS/s DAC2 80 Gbps 2:1 Multiplexer 80 Gbps 1:2 De-Mux and clock to data recovery Flip flop 30/60 GHz Clock Distributor/Divider DUAL_DAC10002_ Ch2Ch Optional Channel to Channel Syncronization Kit for Dual Channel DAC (DAC10002). Clock Synthesizer is not included. QUAD_DAC10002_ Ch2Ch Optional Channel to Channel Syncronization Kit for Quad Channel DAC (requires qty two DAC10002 systems). Clock Synthesizer is not included. About us Microsoft and Windows are registered trademarks of Microsoft Corporation. Matlab is a registered trademark of Math works. Beagle Board Black is a registered trademark of Beagle Bone.org. Micram Microelectronic GmbH is an independent fabless whole-service provider for high performance ASIC solutions. It is a privately owned company, located in the Technology Quarter, in close vicinity to the Ruhr-University Bochum. Micram Microelectronic GmbH Konrad-Zuse Strasse Bochum, Germany Tel: +49 (234) Fax: + 49 (234) Copyright Micram Microelectronic GmbH 2016 All rights reserved. Product specifications and descriptions in this document subject to change without notice. Information in this document supersedes that in all previously published material. DAC4_SYSTEM_EN V3.3_18_OCT_16