Verigy V93000 HSM DDR3 64 sites Memory Test System

Transcription

1 Verigy V93000 HSM DDR3 64 sites Memory Test System Technical Specifications CONTENTS 1. System overview 2 2. Timing Fast timing STD Timing 6 3. Digital channels FAST Driver STD Driver Programmable load FAST receiver STD receiver Parametric measurement Per-Pin PMU Per-Pin-TIA 14

2 1. System Overview Test Processor-Per-Pin architecture Maximum channel count Maximum test capability Parallel vector memory APG memory 1) 1920 digital pins Up to 16 sites for x32 single-ended devices (non-shared) Up to 32 sites for x16 single-ended devices (non-shared) 4MByte (32MVectors at x8 mode) 8MByte (64MVectors at x8 mode) optional 12MByte standard 56MByte optional 2200 Mbps Max. I/O data rate (FAST mode) Max. clock rate (FAST mode) Max. I/O data rate (STD mode) Max. clock rate (STD mode) 2) 2200 Mbps 1.10 GHz 1000 Mbps 625 MHz 1. APG memory is used for memory pattern generation and result capture. 2. Maximum data/clock rate with 1.65 V swing (into open) in a std-mode APG Capability Maximum APG speed 2200 Mbps (non-interleaved APG) Maximum APG address bus size 64 bits (in any combination of X, Y and Z) Maximum APG data bus size APG sourcing Unlimited in software (limited only by number of tester channels configured per site) APG able to source any address data or control information to any tester channel on any device cycle Scope of specifications Verigy specifies and verifies the specifications at the DUT interface pogo level. Using an adequate DUT board, valid system calibration and a fixture delay measurement (TDR), these specifications are valid at the device under test as well. Specifications describe warranted product performance. Characteristics are included as typical values to provide additional useful information by describing typical nonwarranted performance. 2

3 Calibration and operation Warm-up time Basic maintenance period Base calibration period (traceable calibration) Calibration period (system auto adjustment) DC update period 60 minutes 6 months 6 months 3 months 3) 2 weeks 3. Valid at ambient temperature within ±2.5 K of calibration temperature. For temperature requirements during calibration please see Maintenance Guide. Environmental Operating Specification guarantee temperature Maximum humidity at 30 C Storage (without water) 15 C to 30 C (59 F to 86 F) 20 C to 30 C (6 8 F to 86 F) < 70% R. H., non-condensin g 40 C to +70 C Maximum External Input Voltage Maximum range for external voltage applied to pin -2.0V to 5.0V 3

4 2. Timing 2.1 FAST timing Per-pin pair OTA / EPA Single-ended signal per drive receive pin pair 4) (t OTA ) Single-ended signal edge placement accuracy 4) (t EPA = t OTA / 2) < ± 75 ps, typical ± 60 ps < ± 38 ps, typical ± 30 ps Over Site / System OTA / EPA Overall timing accuracy 4) (t OTA ) Edge placement accuracy (t EPA = t OTA / 2) Pin to pin skew within whole system 5) Edge placement resolution ± 100 ps ± 50 ps ± 25 ps 1 ps Edge placement range 4 to 12 Sequencer periods 6) 4. Driver measured with tester receiver => it includes t SignalTotalJitter of the driver + t SignalTotalJitter of the receiver using PRBS 2^7 pattern and nominal swing V swing into 50 Ohm, verified with V swing = 250 mv, 825 mv and with speeds 2.2Gbps, 1.6Gbps, see also Fig. 1 and Fig Pin to pin skew within whole system = Overall timing accuracy Per-Pin Pair OTA. 6. Edge placement range max ns to ns. Vector period 2200 Mbps Minimum vector period Minimum sequencer period Maximum sequencer period Accuracy Resolution ps ps ns ±15 ppm of period setting fs Single-ended signal eye height at 2.2Gbps 7) Typical eye height V SignalEyeHeight of driver Typical eye height V SignalEyeHeight of driver + receiver pair 80% V swing 63% V swing at 1.6Gbps 7) Typical eye height V SignalEyeHeight of driver Typical eye height V SignalEyeHeight of driver + receiver pair 90% V swing 84% V swing 7. Using PRBS 2^7 pattern and nominal swing V swing into 50 Ohm, verified with V swing = 250 mv, 825 mv. See Fig.2. 4

5 T Bit overlay of the eyes of all pin pairs t OTA-EyeWidth t OTA =T Bit t OTA-EyeWidth Fig. 1: OTA specification T Bit V swing V SignalEyeHeight t SignalEyeWidth t SignalTotalJitter = T Bit t SignalEyeWidth Fig. 2: Eye diagram - timing and level specification 5

6 2.2 STD timing OTA /EPA Overall timing accuracy (OTA) ± 200 ps 8) Edge placement accuracy (EPA = OTA/2) Edge placement resolution Edge placement range ± 100 ps 8) 1 ps 4 to 12 Periods or 8000 ns to ns, whichever is smaller 8. OTA, EPA valid for pulse width 1 ns, tested at 3V and 1.65 V swing. Verification is done as in FAST mode with prbs 2^15 and into 50 Ohm. Characteristic: Between pins that are continuously driving clock signals (with 50% duty cycle) of the same frequency EPA is valid up to 625 MHz (800 ps pulse width) at 1.65 V swing (into open). Vector period 2200 Mbps Minimum vector period Minimum sequencer period Maximum sequencer period Accuracy Resolution 0.80 ns ns ns ±15 ppm of period setting fs Single-ended signal eye height Minimum eye height V SignalEyeHeight of driver + receiver pair at 1Gbps 65% V swing 9) Minimum eye height V SignalEyeHeight of driver + receiver pair at 800 Mbps 76% V swing 10) 9. Valid for pulse width 1 ns, tested at 3V and 1.65 V swing. Verification is done as in FAST mode with prbs 2^15 and into 50 Ohm. 10. Valid for pulse width 1.25 ns, tested at 3V and 1.65 V swing. Verification is done as in FAST mode with prbs 2^15 and into 50 Ohm. 6

7 3. Digital Channels 3.1 FAST driver AC performance Maximum transition time (20 to 80%) at 825 mv swing into 50 Ohm 150 ps (see also FAST Timing specifications) DC performance 11) Level range 0.95 V to 3.05 V 12) High voltage level resolution 1 mv High voltage level accuracy ±9 mv Minimum swing (V SE+,V SE- ) into 50 Ohm 50 mv 13) Maximum swing (V SE+,V SE- ) into 50 Ohm 825 mv Swing accuracy ±4 mv ± 1% Swing resolution 1 mv Dynamic high level shift High voltage level accuracy ±25 mv Swing accuracy ±10 mv ± 1% Impedance Source impedance 50 Ohm ± 2.5 Ohm 11. Specifications into open unless otherwise stated 12. Software allows programming up to 3.1V and down to 1V 13. Software allows programming to 0 mv swing, specification valid down to 50 mv 7

8 3.2 STD driver AC performance Maximum transition time (10 to 90%) at 1.65 V swing 600 ps 14) at 3 V swing 850 ps 14) DC performance (high and low level) 15) Level range 0.95 V to 4.25 V 16) Level resolution 2.5 mv Level accuracy ±10 mv Minimum swing 200 mv 17) Maximum swing 4.25 V DC performance (3 rd level) 15) Level range 0.95 V to 4.25 V 16) Level resolution Level accuracy 2.5 mv ±10 mv Impedance Source impedance 50 Ohm ±2.5 Ohm Z-Clamp mode Voltage range low clamp Voltage range high clamp Voltage resolution Voltage accuracy High-Z compliance range 0.95 V to 2.9 V 0.95 V to 4.25 V 2.5 mv ±100 mv 0.45 V to 3.75 V or vcl+0.5v to vch-0.5v 18) 14. Verification condition: half the noted voltage into 50 Ohm. 15. Specifications into open unless otherwise stated 16. Software allows programming up to 4.3 V and down to 1V. 17. Software allows programming to 0 mv swing, specification valid down to 200 mv. 18. With vcl := clamp low level and vch := clamp high level 8

9 3.3 Programmable load Currents (I oh, I ol ) 0 to 35 ma 19) Current resolution 12.5 µa Current accuracy ±75 µa ±1% of max (I ol, I oh ) 20) Commutation voltage range (V com ) Voltage resolution Voltage accuracy Impedance 0.95 V to 4.25 V 2.5 mv ±100 mv 50 Ohm ±5 Ohm to 5mA when using the Per-Pin-TIA 20. Accuracy valid at V ol < V com V - I ol * 50 Ohm, V oh > V com+0.7 V+I oh * 50 Ohm (see Fig. 3). V ol /V oh is the resulting voltage at the pin output. Programmable load /characteristics Idut vs. Vdut (for Vcom = 2.0V, Iol = 20mA, Ioh = 10mA) 20 Idut [ma] Vdut [V] Fig. 3: Programmable Load /Characteristics 9

10 3.4 FAST receiver AC performance Typical intrinsic rise time (20 to 80%) 100 ps DC performance Input Voltage and Threshold range (V SE+,V SE- ) 0.95 to 3.45 V Threshold Voltage accuracy ±5 mv 21) Threshold Voltage resolution Maximum leakage current with cross termination 1 mv ±300 µa with common mode voltage > 0.5 V 22) Termination Single ended / center tap differential impedance 50 Ohm ± 2.5 Ohm Termination level center tap range (V TERM ) 0.95 to 4.25 V 23) Termination Voltage accuracy ±6.5 mv 24) Termination Voltage resolution 1 mv 21. Valid for 0V voltage 2V, for -0.95V voltage 3.45V the accuracy is ±7 mv. 22. At common mode voltage of 0.75 V a typical leakage current is ±150 µa,, which increases as the common mode changes. 23. Software allows programming up to 4.3 V and down to 1 V. 24. Valid for voltage 3V, for voltage 4.25 the accuracy is ±10 mv. Z 50 Ω CROSS-TERM SWITCH + - V diff V SE+ Z 50 Ω V TERM V SE- Fig. 4: Digital Receiver DC voltages 10

11 3.5 STD Receiver Dual threshold comparators AC Performance Typical intrinsic rise time (10 to 90%) 50 Ohm termination Typical intrinsic rise time (10 to 90%) HighZ termination 200 ps 1600 ps DC performance 25) Single-ended compare Input Voltage and Threshold range (V SE+,V SE- ) Threshold resolution Threshold accuracy Input leakage current Maximum leakage current with cross termination 0.95 to 4.25 V 26) 2.5 mv ±10 mv ±25 µa (including leakage of driver in HZ and active load off) ±300 µa with common mode voltage > 0.5V 27) 25. Specifications into open unless otherwise stated. 26. Minimum high-low threshold difference: Software allows programming down to 0 mv difference, recommended difference 100 mv. 27. At common mode voltage of 0.75 V a typical leakage current is ±150 µa,, which increases as the common mode changes. 11

12 4. Parametric Measurement 4.1 Per-Pin PMU Voltage force/measure Range 1 V to 4.3 V Voltage force Resolution 5 mv Accuracy ± 20 mv (I a *R) ± 0.5% of setting 28) Voltage measure Compare mode Resolution 5 mv Accuracy ± 20 mv (I a *R) ± 0.5% of reading 28) Value measurement mode Resolution Relative accuracy Accuracy Accuracy 0.5 mv ± 3 mv 29) in range 0 V to 2 V ± 5 mv (I a *R) in range 0 V to 2 V ± 10 mv (I a *R) in range 1 V to 4.3 V 28. I a is the actual current, R is the wiring resistance of 0.5 Ohm. 29. In two consecutive voltage value measurements with different force currents, the accuracy of the calculated delta voltage. Current force/measure Range Resolution (force/measure) Measure accuracy Force accuracy Range 1 ±40 ma 20 µa ±50 µa ±0.5% of reading ±50 µa ±0.2% of setting Range 2 ±1 ma 0.5 µa ±1.25 µa ±0.5% of reading ±5 µa ±0.5% of setting Range 3 ±100 µa 50 na ±125 na ±0.5% of reading ±500 na ±0.5% of setting Range 4 ±10 µa 5 na ±100 na ±0.5% of reading ±100 na ±0.5% of setting 12

13 Current force for relative measurement Relative accuracy 30) ±20 µa ±0.3% of setting in range In two consecutive voltage value measurements with different force currents, the accuracy of the calculated delta of the forced currents. Voltage clamps (available in current force) Voltage range Voltage resolution Voltage accuracy -1 V to 4.3 V 2.5 mv ±100 mv 13

14 5. Per-Pin-TIA DC Performance STD Receiver specifications apply. AC Performance Maximum Input Frequency 1600MHz 31) Resolution Minimum Input Slope 1.5ps 0.1V/ns Time Measurement Accuracy (single measurement) ±100ps 32) ( = t, see Fig. 5 below) Time Measurement Accuracy (with averaging) ±30ps, typical 33) Frequency/Period Measurement Accuracy (using N cycles averaging, see Fig. 5 below) ±100ps/N 32) 34) Time Measurement Accuracy ±100ps + t EPA (see section 2.1 against internal reference (see Fig. 6 below) 35) FAST timing) 32) MHz when using i/o pin mode and driving 3 rd level, or when using the programmable load 32. condition: square wave 33. same slope; averaging over 100 samples 34. for <=450 MHz input; (±100ps + period)/n for >450MHz input 35. internal reference is generated by the driver of the pin that performs the measurement Fig. 5: N cycles averaging Fig. 6: Measurement against internal reference signal 14

15 Measurements between pins (propagation delay (PD), skew) are derived from individual measurements on each pin against the internal reference signal (see Fig. 7) Fig. 7: Measurement between two pins (propagation delay (PD) Other Measurement Functions Measurement Mode Maximum Sampling Rate Averaging Event Counter Sample Point Randomization Arming/Triggering time interval, frequency, period, pulse width, jitter, propagation delay, rise/fall time single ended or differential 125kSamples/s up to 32kSamples max 2 17 Events 0 100% of Sample Period internal (arming on event in the measurement signal) 15

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17 Related Information For more information about the Verigy V93000 HSM Series, please visit the following website: Contact Information For more information about the Verigy V93000 HSM2200, please contact your local Verigy sales representative. This information is subject to change without notice. Verigy Ltd July 19, EN Revision