DDR4 SI/PI Analysis Using IBIS5.0

Transcription

1 DDR4 SI/PI Analysis Using IBIS5.0 Socionext Inc. Yumiko Sugaya Asian IBIS Summit, Tokyo, Japan November 16, 2015

2 Outline Overview DDR4 SI/PI Analysis Issue Over Clocking issue DDR4 SI/PI Analysis Using IBIS5.0 Summary Expectation for future IBIS 2

3 Outline Overview DDR4 SI/PI Analysis Issue Over Clocking issue DDR4 SI/PI Analysis Using IBIS5.0 Summary Expectation for future IBIS 3

4 Overview Because of the Over Clocking issue, we could not use IBIS5.0 for high speed analysis, such as for DDR4. Modification of the EDA software has removed the Over Clocking issue. Therefore, the accuracy of IBIS5.0 at high speed has improved. IBIS5.0 can analyze DDR4 SI/PI with high accuracy in a short time! Simulation Time [h] 4

5 Outline Overview DDR4 SI/PI Analysis Issue Over Clocking issue DDR4 SI/PI Analysis Using IBIS5.0 Summary Expectation for future IBIS 5

6 Bandwidth(GB/s) Memory Trend DDR3 is replaced by DDR4. 64 Hi-Performance (DDR4) Mobile/Commodity (LPDDR4) 2133Mbps LPDDR2 x32 2ch DDR3 x64 1ch 1066Mbps LPDDR3 x32 2ch 2133Mbps DDR4 x64 1ch 2400Mbps 1600Mbps 1866Mbps LPDDR4 x16 4ch 3200Mbps 2667Mbps 3200Mbps 4266Mbps

7 Unit Interval [psec] Necessity of IBIS5.0 for DDR4 simulation IBIS5.0 can analyze SSO noise with high accuracy in a short time DDR4 Timing Budget Data Rate[Mbps] Decreasing Unit Interval Margin SDRAM Spec Package-Board Skew LSI Skew Must include SSO noise effect in Package-Board Skew with high accuracy SPICE Net: SSO accuracy :high Simulation Time: too long 7 IBIS5.0: SSO accuracy : high Simulation Time : short

8 IBIS5.0 issue We solved the Over Clocking issue in cooperate with EDA developer. Comparison of the simulation models. SPICE Net IBIS4.2 IBIS5.0 Simulation Time Longer Shorter Shorter SSO accuracy High Low High SI accuracy (~1600Mbps) High High High SI accuracy (1866Mbps~) High High Low High accuracy using IBIS5.0 Over Clocking issue!!! 8

9 Outline Overview DDR4 SI/PI Analysis Issue Over Clocking issue DDR4 SI/PI Analysis Using IBIS5.0 Summary Expectation for future IBIS 9

10 Voltage[V] Voltage[V] What is the Over Clocking? Old and new issue (Over Clocking) Input Controller IO SDRAM DIE VDE SDRAM IO IBIS5.0 Simulation (DDR4-2667Mbps) Input 750ps 375ps \ SDRAM DIE No 375ps pulses reproduced by Over Clocking. Time [ns] 10

11 IBIS Over Clocking mechanism(1/4) Voltage Waveform Transition Initial Delay Time Settled IBIS Low Speed Mode Pulse Width Initial Delay+ Transition Time Input Pulse Width Waveform Fall Endpoint of Falling waveform Rise Output Correct Fall Rise 11

12 IBIS Over Clocking mechanism(2/4) Voltage Waveform Transition Initial Delay Time Settled IBIS High Speed Mode(Over Clocking) Input Pulse Width Pulse Width < Initial Delay+ Transition Time Endpoint of Falling waveform Waveform Fall Initial Delay prevent switching Rise Output Fall Over Clocking Rise 12

13 IBIS Over Clocking mechanism(3/4) Voltage Waveform Transition Initial Delay Time Settled IBIS High Speed Mode(Initial Delay Cut) Input Waveform Cut Initial Delay Pulse Width Endpoint of Falling waveform Fall Rise Pulse Width = Transition Time Output It is good for IBIS4.2 (w/o SSO noise)... Fall Rise 13

14 Current Voltage IBIS Over Clocking mechanism(4/4) Waveform Transition Initial Delay Time Settled Composite Current IBIS High Speed Mode (IBIS5.0) Input Waveform Composite Current Current Changing Pulse Width Fall Fall Rise Rise Time Pulse Width < Initial Delay+ Transition Time Endpoint of (again) Falling waveform Output Traditional Engine Can not cut Initial Delay Fall Can not use IBIS5.0 at DDR4... Rise 14

15 Over Clocking modified in the EDA Software IBIS High Speed Mode (IBIS5.0) Input Pulse Width Move switching point of Fall=>Rise Waveform Fall Rise Pulse Width = Transition Time Output New Engine Composite Current Fall Falling Fall and Rise overlap Over Clocking solved Rise Rising Composite Current New Engine Fall+Rise current Fall Fall+Rise Rise 15 Regenerated Composite current

16 Voltage[V] Voltage[V] New Engine Simulation Result (Over Clocking solved) Over Clocking issue of IBIS5.0 is solved!! IBIS5.0 Simulation on New Engine (DDR4-2667Mbps) Input 750ps 375ps \ SDRAM DIE 375ps Pulses reproduced! Time [ns] 16

17 Outline Overview DDR4 SI/PI Analysis Issue Over Clocking issue DDR4 SI/PI Analysis Using IBIS5.0 Summary Expectation for future IBIS 17

18 DDR4 SI/PI Analysis Using IBIS5.0(1/3) Waveform of the SSO noise : Very Good!! Stimulus CK Toggle A/C, CNTL PRBS7 DQ Victim PRBS7 Aggressor PRBS7 DQS Victim Toggle Aggressor PRBS7 VDE Voltage waveform (Controller IO) Controller DIE Controller IO VDE VDE SDRAM IO SDRAM DIE VDE (Controller DIE) DQ wave(sdram DIE) Difference in peaks is less than 1mV!! 18

19 DDR4 SI/PI Analysis Using IBIS5.0(2/3) Stimulus CK A/C, CNTL DQ DQS Width of the EYE : Seems Good (see Expectation for future IBIS ) Toggle PRBS7 Victim Aggressor Victim Aggressor PRBS7 PRBS7 (Even/Odd 2pattern) Toggle Toggle DDR4 TX DQS-DQ EYE Waveform (@SDRAM DIE) 19

20 DDR4 SI/PI Analysis Using IBIS5.0(3/3) Simulation Time : Excellent!!! Transition Analysis Time:60ns(one cycle of PRBS7) Simulation Time [h] (9.2Days) Can not use for prototyping Better suited for prototyping (A number of What-If analyses in one day) 20

21 Outline Overview DDR4 SI/PI Analysis Issue Over Clocking issue DDR4 SI/PI Analysis Using IBIS5.0 Summary Expectation for future IBIS 21

22 Summary Because of the Over Clocking issue, we could not use IBIS5.0 for high speed analysis, such as for DDR4. Modification of the EDA software has removed the Over Clocking issue. Therefore, the accuracy of IBIS5.0 at high speed has improved. IBIS5.0 can analyze DDR4 SI/PI with high accuracy in a short time! Simulation Time IBIS5.0 result: High accuracy 22 Short simulation time

23 Outline Overview DDR4 SI/PI Analysis Issue Over Clocking issue DDR4 SI/PI Analysis Using IBIS5.0 Summary Expectation for future IBIS 23

24 Expectation for future IBIS Remaining issue on IBIS5.0 IBIS5.0 does not show IO Delay Penalty accurately IBIS5.0 modeling only final-buffer, pre-buffer Delay Penalty can not be considered. 22ps different For further simulation accuracy and capability, support of the pre-buffer delay penalty is strongly desired. 24

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