I Main coupling Sub- coupling

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1 High-speed, high-bandwidth DRAM memory bus with Crosstalk Transfer Logic (XTL) interface Hideki Osaka Toyohiko Komatsu Hitachi Ltd., Hitachi Ltd., Kanagawa, Japan Kanagawa, Japan hitachi. co.jp hitachi. cojp Abstract Crosstalk Transfer Logic (XTL) is a digital-signal interface that uses directional couplers to form parallel lines within a circuit board. An advantage of the XTL is that it provides a multi-drop and high-speed system that is a one-to-many connection that can be used as a memory bus. To evaluate the signal integrip of an XTL to be applied to a DRAM bus, a test chip and boards were developed. We describe the design of the bus and report the results of its evaluation in this paper. The test chip was designed using a 0.15-pm CMOS process and it had a controllable ojfet of the hysteresis receiver. A folding coupler was applied to the motherboard to condense the wiring and to reduce the noise from adjacent signals. The motherboard had only hvo coupler layers. with a fourbyte data width, and it was capable of having eight modules mounted on the bus. The experimental results showed that the WRITE and READ operation reached speeds of ut least 500 Mbps when eight modules were mounted on the bus. 1. Introduction The speeds of recent high-speed digital systems have been limited by the Inter Symbol Interference (ISI) effect [I]. The cause of the IS1 effect is the multi-reflection that occurs at impedance mismatch points in a bus line. The multi-reflection noise from each stub line on the memory module is not small, even if both ends of the bus and every entrance of the stub lines are terminated by a series resistor. This interface is called a Stub Series Terminated Logic (SSTL) and it is widely used as a double-data rate (DDR) SDRAM interface. In the SSTL case, the impedance mismatch or the coefficient of reflection at each entrance of a stub on a mainline is almost 25% and the multi-reflection between the stub lincs leads to the ISI. Crosstalk Transfer Logic (XTL) is an inter-chip interconnect technology that uses crosstalk generated within a printed circuit board (PCB) as a signal transmitter 121. Susumu Hatano Elpida Memoyy Inc., Kanagawa, Japan hatanosusumu@elpida.com I Controller niilcp (a) Topology of XTL Takeshi Wada Hitachi Ltd., Tokyo, Japan wadatakeshi@ic.hitachi.coljp mainline m I Main coupling Sub- coupling line line 1 2 A I Power plane Signal layer Ground plane Driver pulse Coupling pulse (b) Cross-sectional view of PCB; XTL coupler Figure 1. XTL configuration; (a) topology and (b) coupler on board A well-known phenomenon is that crosstalk in a digital system is generated in one line of parallel coupling lines or a directional coupler when a drive pulse is traveling on the other line. The crosstalk is also a directional pulse because only the backward end at the coupling line is generated while the forward end of the coupling line is not generated in a strip-line structure. The reason is the backward crosstalk is proportional to the sum of the coupling capacitance and coupling inductance, however, the forward crosstalk is proportional to the difference of the coupling capacitance and coupling inductance. In the strip-line structure case, the difference is theoretically zero [3,41. Figure 1 shows the typical configuration of an XTL system. One end of a mainline connected to a memory / IEEE 63

2 controller and one end of each stub lines connected to a DRAM are terminated. A driver within the controller and the DRAMS push and pull a pulse in the center of the termination voltage (Vtt). A directional coupler is formed between a main-coupling line and a stub line and the coupler appropriately transfers a polarized return to zero (RZ) signal from a non-return to zero (NE) signal driven from the driver. The RZ signal is called an XTL signal in this paper. The positive and negative XTL signals respectively correspond to the rising and falling transient parts of the NRZ pulse. The XTL signal must be demodulated at the receiver using a hysteresis fimction. A previous work [2] showed the possibility of a one giga-bit per second (Gbps) per pin data-transfer-bus made up of 16 modules on a back-plane bus based on an ECL technology. In this paper, we describe the design and report the experimental results of an evaluation of an XTL test system that will be applied to a DRAM memory bus system. This system includes a test chip fabricated using a 0.15-pm DRAM process and an eight-module mountable motherboard. 2. System Design A test chip (HS-TEG) and boards were developed to evaluate the signal integrity of the XTL. The HS-TEG was used in the DRAM process, however, it has no memory cell in and of itself Driver The XTL driver of the test chip drives a terminated single line. The length of the mainline is about eight times the coupler length. As described below, the coupler is 40- mm long and the mainline is over 320-mm long. Therefore, the edge rate of the data pulse becomes dull owing to the skin effect and the dielectric loss at the far-end coupler. To recover the pulse-edge rate, the driver contains the slewrate and impedance controllers Receiver The test-chip receiver has a hysteresis circuit (shown in Figure 2(a)). The challenge of designing the receiver was to achieve high-speed operation and have a built-in hysteresis function. In our installation, one receiver has two comparators and a RS-FF(see Figure 2(a)). The offset voltage of the comparator is controlled by a 3-bit signal (HST) and its offsets are f50, f100, and f150 mv. Each comparator outputs the result of a comparison signal and a Vref-added controllable-offset voltage (see Figure 2(b)). Each comparator detects the polarized XTL signal input to the receiver and outputs to the RS-FF. The positive XTL signal corresponding to the rising edge of the drive pulse in the mainline sets the RS-FF via the positive-offset receiver and the negative pulse corresponding to the falling edge resets the RS-FF. Therefore, the receiver output is demodulated to the NRZ signal and is equal to the drive signal. Vrcf HST RST 6 (a) Hysteresis receiver circuit (b) Controllable offset comparator Figure 2. XTL receiver (hysteresis) In other words, the XTL receiver detects changing-data not no-changing-data. Because the XTL signal is generated at only the edge of drive data, and the XTL signal comes back to the Vtt when no-change data were driven in a chain at a WRITE and a READ access or there is no datum driven during the idle cycle between a WRITE and a READ cycle in a memory. Therefore, even though noise generated by another signal, ground bounce, etc., is added to the XTL signal, the hysteresis receiver can absorb the noise during no-changing data Folding coupler In the XTL system, the directional coupler is a key component and the XTL signal level determines the hysteresis-offset voltage of the XTL receiver. As described in Ref.2, guard lines were inserted between couplers that were stacked vertically. Hence, the previous motherboard was costly because the signal line density in the motherboard was not high and many layers were needed. A folding mainline structure was adopted in the test board (Figure 3) to reduce the number of layers stacked on a board, the density of the lines, and to avoid noise from adjacent signals. The main coupling line was folded, as shown in the far end of the figure, and it was coupled to both sides of the sub-coupling lines. All lines are located on a signal layer and they are positioned between power and ground planes. A drive pulse from a controller always travels from one side to the other and the signal retums in the backward direction. The mainline connects the XTL signal to subcoupling lines 1 and 2 at the same level. The XTL signal at sub-coupling line 1 is transmitted to chip A, however, the XTL signal at sub-coupling line 2 is absorbed at the termination. The drive pulse on the backward part of the 64

3 mainline makes the XTL signal exist on both sides of the mainline, however, only the XTL signal of sub-coupling line 2 is transmitted to chip B. In this scheme, the XTL signal can be transmitted to the proper chip. What this means is that the folding mainline structure cancels the noise from adjacent signals even if the mainline and subcoupling line are adjacent to each other line by line in the same layer. I ; HalvedXTL signal ~... Output ofxtl receiver! I! (! Figure 4. Preamble added before DQ and DQS and internal reset signal of DRAM receiver Signal from controller To Rtt Figure 3. XTL coupler layout on a PCB The interval of the modules in the design is almost the same as the coupler length, however, by folding the mainline we can halve the interval and the home factor of the XTL bus is thus halved. We designed the length of the coupler to be 40 mm because the edge rate that becomes the XTL signal is saturated at 40 mm, even if the edge rate becomes as dull as 800 ps. Furthermore, another advantage of the folding main line is there is that there is not any simultaneous switching output noise generated by via holes because there is no via hole in the main line from the coritroller to the termination. This is an important aspect of the high-speed interconnection because the via-hole noise reduces the noise margin in a signal wiring which comes and goes between an upper layer and a lower layer [5]. The motherboard we designed had 8 layers, 75R characteristic impedance, and 25% of the backward crosstalk coefficient. The line width and minimum spacing were both 100 um. These technologies are used widely in PC server manufacturing Preamble of DQ / DQS During an idle cycle, the XTL signal of data (DQ) and the data strobe (DQS) comes back to VTT. The first transition pulse of DQ and the DQS following the idle cycle halves the XTL signal, because the output voltage of a driver is halved from Vtt to VohJ(Vo1). To avoid a halved XTL signal, a preamble that Low -state cycle is introduced before the DQ and DQS are driven. The RS-FF of the DRAM receiver is reset by a WRITE/READ command triggered at the preamble period (Figure 4) Evaluation system interface The controller and DRAMS signals are the XTL interface and every signal is connected as is shown in Figure 5. One HS-TEG chip has eight DQ, two DQS, and two clocks (CLWCLKB), and the die is packaged in a 54- ball chip-scale package (CSP). The HS-TEG plays both the DRAM and the controller roles. Controller (HS-TEC) $ 1 DIMMI I DlMM2 4eu svv A - CLK GEN. DQSI DQSB vemier t$ 2 -fl DQ L vemier 8- r. 1...( DIMMR 1 v 1 L~~~ Figure 5. Preamble added before DQ and DQS and internal reset signal of DRAM receiver A clock generator distributes CLK and CLKB with the same configuration as the coupler in the direction opposite to the DQiDQS, etc. The READ DQ from DRAM is captured by the DQS from the DRAM at the controller. Because the flight times of the DQ, DQS, and CLWCLKB are the same, the controller can capture in the same phase all the DQs driven by each module. This means that this system s READ-access latency is minimal, because the core clock without a re-synchronizing cycle captures the READ data. Therefore, the performance of the computer system would improve, because the frequency in the 65

4 READ access part of most computers is usually higher than that of the WRITE access. On the other hand, in the WRITE-access case, the controller drives the DQ and the DQS is subtracted from the delay to the module. The reason for this is that the directions of the CLK and the DQ/DQS are opposed and the delay difference between the CLWCLKB and the WRITE DQ is twice the traveling time to the module. A vernier delay circuit in the controller adjusts the phase delay of the WRITE DQ/DQS where the phase of the WRITE DQ/DQS equals the phase of the CLWCLKB at the DRAM. 3. Design validation We constructed the XTL signaling circuits described on a test chip fabricated using a 0.15-pm process (Figure 6). The test chip contained two XTL data ports: one was for data (DQ), which communicated with the XTL interface, and the DX was used to monitor the DQ or inputs to the DQ. We used a test board that could accommodate the mounting of eight modules to a bus (Figure 7). We used a surface-mount 240-ball socket device that could mount two modules. These surface-mount sockets Drovided the density reduction of the line under the socket. We measured the properties of the coupler in the test board and the properties of the receiver to evaluate the signal integrity of the XTL interface Coupler properties The impedance of the main lines was measured using the Time Domain Reflectometry (TDR) method when all modules were mounted, four modules mounted, and only one module mounted (Figure 8). The TDR dnve puke, which was applied at a via-hole near the ball of the HS- TEG, had about a 40-ps transient time generated by a digital TDR oscilloscope. The mainline was terminated at the far end by a 75-ohm resistor and it was 5 17-mm long. The stub line in the module was 14.3-mm long. Variations of impedance of the mainline were measured within 2 6 ohm when all modules were mounted vs. when only one was mounted. For this reason, the reflection in the mainline was very small and it could keep any IS1 effect minimal. The backward crosstalk coefficient (Kb) measured for a directional coupler was 24%, almost the same as the designed value. 025 p Figure 6. DIE photo of HS-TEG chip 1 HS:TEG 0. I ipacitive refl ctbn TIME [ns] Figure 8. TDR waveform; drive pulse applied to the ball of the HS-TEG of the mainline; number of modules mounted was Waveforms of XTL Figure 7. Test board; a mother board and mounted 8 modules;all modules mounted 4 HS-TEG chips. The drive pulse and the XTL signal were measured (Figure 9). The falling time (20-80%) of the drive pulses at the chip and at the termination were 18 1 ps and 947 ps, respectively. The amplitude of the XTL signals was equal to or larger than 197 mv. It was enough voltage to demodulate the XTL signal in the receiver. The causes of the dulling of the drive pulse were the skin effect, the dielectric loss of the mainline, and the 66

5 impedance mismatch of the couplers. r (b) Tcnnination point Figure 9. Drive pulse of mainline at the chip (a) and the termination (b), and XTL signal at I*' (c), 4'h (d), and 8'h coupler (e) The eye pattern of a 1-bit XTL signal at the 1'' (left), 4Ih (center) and Sth (right) modules were measured at 400, 600 and 800 Mbps (Figure IO). All waveforms were measured at the HS-TEG on the module. Because we wanted to leam the limitations of the coupler, the pulse generator was used, and not the HS-TEG. At 800 Mbps, the eye of the XTL signal at the 1'' module and 4Ih module were opened enough in the random-data pattern, however, the one at the 8Ih module was opened only very narrowly. The reason is that the XTL signal would not become saturated at the coupler and the tail of the XTL became longer than that of the Is' or 4Ih module, because the edge rate of the drive pulse became dull. Here, I would like to emphasize the XTL signal of the 4th module was eyeopened a large enough even if 800 Mbps operation. In the WRITE mode, the 1-bit maximum frequency of the lst, 4th, and 8th module were 631, 666, and 634 Mbps, respectively, as measured with a bit-error-rate tester. The adjacent noise from the controller chip caused the maximum frequency of the 8th module to be degraded to 523 Mbps, though the maximum frequency of the 1st and 4th modules were the almost same. It appears that adjacent noise in the 8th module would make the signal decrease because the signal tail of the 8th module was longer than that of the 1st and the 4th modules and the noise from adjacent signals was superimposed on the signal. This result means that the improvement of the edge rate of the drive pulse in the mainline led to the increase of the maximum frequency at the 8th module. The 1-bit eye pattem and the maximum frequency of the READ data were also measured. The eye-patterns at each frequency were almost same as those shown in Figure 10. When the adjacent signals were active, the maximum frequency of the 1st and 8th module was 540 and 525 Mbps, respectively. These frequencies were almost the same as those of the WRITE data. The hysteresis offset of the receiver was set at f 45 mv in these measurements and the f 100 mv offset did not cause the maximum frequency to change much. 4. Conclusion We described an XTL bus system design and reported the results of an evaluation to determine the signal integrity of the XTL. A test chip was designed, using a 0.15-pm CMOS process that had z controllable offset of the hysteresis receiver. The test motherboard had only two coupler layers and a folding coupler was applied to the motherboard in order to condense the wiring and reduce the noise from adjacent signals. The experiment results showed that a 500 Mbps WRITE and READ operation worked well when eight modules were mounted at the same time on a bus. References tl 1,) sw mps 3t ktll mudude Figure IO. E e pattern of the 1" (left), 4'h (center), and 8 coupler (right); random pulse was applied by a pulse generator (HP 8133A) The performance of the XTL interface was measured at the typical condition that the core and DQ voltages were typically 2.5 and 1.8 V, respectively, at room temperature. [I] K. Yam et al., "The Limi/ of Electrical Signaling", Hot Interconnect V [2] H. Osaka, et al., "I GT/s Back Plane Bus (XTL: Crosstalk Transfer Logic) using Crosstalk Mechanism", Hot Interconnecr V-1997, pp, [3] Clayton R. Paul, "Introdirction to Electromagnetic Computibili@", Wiley & Sons, 1992, pp [4] A Feller, et al., "Crosstalk and reflections in high-speed digital systems", Proc. Fall Joint Compter CUI$ 1965, pp [5] St. Rosser et al., "Measurement and Simulation of Simultaneous Switching Noise in the Multi-Reference Plane Package", 1996 Proc. ojectc, pp

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