DesignCon Signal and Power Integrity for a 1600 Mbps DDR3 PHY in Wirebond Package

Transcription

1 DesignCon 2011 Signal and Power Integrity for a 1600 Mbps DDR3 PHY in Wirebond Package June Feng, Rambus Inc. [ jfeng@rambus.com] Ralf Schmitt, Rambus Inc. Hai Lan, Rambus Inc. Yi Lu, Rambus Inc.

2 Abstract A DDR3 interface for a data rate of 1600MHz using a wirebond package and a lowcost system environment typical for consumer electronics products was implemented. In this environment crosstalk and supply noise are serious challenges and have to be carefully optimized to meet the data rate target. We are presenting the signal and power integrity analysis used to optimize the interface design and guarantee reliable system operation at the performance target under high-volume manufacturing conditions. The resulting DDR3 PHY was implemented in a test chip and achieves reliable memory operations at 1600MHz and beyond. Authors Biography June Feng received her MS from University of California at Davis, and BS from Beijing University in China. From 1998 to 2000, she was with Amkor Technology, Chandler, AZ. She was responsible for BGA package substrate modeling and design and PCB characterization. In 2000, she joined Rambus Inc and is currently a senior member of technical staff. She is in charge of performing detailed analysis, modeling, design and characterization in a variety of areas including high-speed, low cost PCB layout and device packaging. Her interests include high-speed interconnects modeling, channel VT budget simulation, power delivery network modeling and high-frequency measurements. Ralf Schmitt received his Ph.D. in Electrical Engineering from the Technical University of Berlin, Germany. Since 2002, he is with Rambus Inc, Los Altos, California, where he is a Senior Manager leading the SI/PI group, responsible for designing, modeling, and implementing Rambus multi-gigahertz signaling technologies. His professional interests include signal integrity, power integrity, clock distribution, and high-speed signaling technologies. Hai Lan is a Senior Member of Technical Staff at Rambus Inc., where he has been working on on-chip power integrity and jitter analysis for multi-gigabit interfaces. He received his Ph.D. in Electrical Engineering from Stanford University, M.S. in Electrical and Computer Engineering from Oregon State University, and B.S. in Electronic Engineering from Tsinghua University in 2006, 2001, and 1999, respectively. His professional interests include design, modeling, and simulation for mixed-signal integrated circuits, substrate noise coupling, power and signal integrity, and high-speed interconnects. Yi Lu is a senior systems engineer at Rambus Inc. He received the B.S. degree in electrical engineer and computer science from U.C. Berkeley in 2002 with honors. In 2004, he received the M.S. degree in electrical engineering from UCLA, where he designed and fabricated a 3D MEMS microdisk optical switch. Since joining Rambus in 2006, he has been a systems engineer designing various memory interfaces including XDR1/2 and DDR2/3.

3 Introduction The memory bandwidth requirement of multimedia consumer electronic products like HDTV systems is constantly increasing, driven by the adoption of advanced features like frame rate up-scaling and 3D projection. At the same time, consumer electronic products remain very cost sensitive, targeting low-cost package and system environment to reduce the overall bill of materials. This creates the need for high-speed memory interfaces implemented in low-cost system environments. In order to address this need we have designed a 1600 Mbps DDR3 memory interface PHY in a wirebond package targeting a low-cost system environment with a 4-layer PCB stack-up typical for cost-optimized consumer electronic products. Designing a DDR3 memory interface for such a high data rate is not trivial. The memory device itself requires more than 40% of the bit time for internal timing, leaving little more than half of the bit time for all channel and PHY timing errors. Meeting these requirements in a wirebond package, using a 4-layer PCB stackup, is a serious challenge. Bond wire coupling in the package and coupling in the PCB routing, which only allows a microstrip routing in a 4-layer stackup, lead to increased crosstalk in the interface system. Additionally, the bond wire inductance leads to higher supply noise, causing power supply induced jitter (PSIJ) as well as simultaneous switching output (SSO) noise in the interface system. The interface design therefore requires a careful optimization of signal and power integrity in the entire system, from the controller PHY to the DRAM component pin. In this paper we will present the signal and power integrity analysis used to optimize the interface design and assuring reliable operation at the target data rate in a low-cost system environment. First we will present the analysis of power supply induced jitter. For this, we analyzed the supply noise spectrum generated in the system and the sensitivity of the system to this noise. With this analysis we were able to predict and optimize the jitter in the PHY, making sure the PHY will meet the tight jitter requirements of the DRAM device. Next we analyze the channel margin loss due to ISI, crosstalk, and SSO. Special emphasize is given to crosstalk and SSO noise, since these are the major contribution to margin loss in the channel timing. A careful optimization of PHY floor plan, package design, and PCB routing was implemented to minimize the margin loss due to crosstalk and SSO. Finally, the system timing was verified for the full range of process variations of the controller PHY and channel parameter variations for low-cost system environments typical for cost-sensitive consumer electronics products. This analysis provides the confidence that the final system will meet the target performance with high yield under High-Volume Manufacturing conditions. The DDR3 PHY was implemented on a test chip and achieves reliable memory operation for a data rate of 1866 Mbps using DDR3 memories of a 1600 Mbps speed grade.

4 I. System Environment and SI/PI Challenges The design target of the DDR3 PHY described in this paper are high-performance consumer electronic systems with a bandwidth requirement of up to 6.4GB/s in a lowcost system environment. This bandwidth is achieved using a x32 PHY running at a data rate of 1600Mbps. In order to support a low system cost implementation, the PHY was designed in a 4- layer wirebond package. Such a package is significantly less expensive than flip-chip packages, however it poses challenges for signal and power integrity especially at higher data rates. Additionally, the PHY is designed for a PCB with only 4 layers, further reducing the final system cost. Finally, silicon area, pad count, and decoupling requirements are carefully optimized to minimize total system cost for the memory subsystem. The goal for this design effort was to achieve a PHY implementation that will reliable achieve the targeted data rate under high volume manufacturing (HVM) conditions using any DDR3 DRAM meeting the JEDEC spec at the targeted data rate. In order to meet this goal it was not enough to design and analyze the PHY alone. Instead, the PHY had to be analyzed in the targeted system environment, optimizing system and PHY implementation concurrently. Closing the voltage and timing budget on the system level resulted in PHY design requirements necessary to achieve the targeted interface system performance in the final implementation using a low-cost system environment. Creating a cost-efficient high-speed memory interface requires careful analysis of power and system integrity [1]. The bond wires in a wirebond package contribute significantly to the inductance of the power distribution network (PDN) of the interface. Inductance in the supply path causes supply noise when the current dissipation of the PHY is changing. This supply noise causes voltage distortions and timing variations, generating timing jitter on interface signals as well as internal PHY signals. The contribution of bond wires to the supply inductance can be reduced by adding additional supply pads to the design, but this would increase the PHY width and ultimately increase the PHY cost and is therefore not advisable. Instead, the number and placement of supply bond wires has to be carefully optimized to achieve the necessary supply noise targets in the design. Bond wires also lead to crosstalk between different signal lines. This is a severe signal integrity challenge especially at higher data rate as targeted for this design. Routing the signaling channel on a 4-layer PCB only allows for microstrips instead of striplines, which adds further crosstalk to the signaling channel. As a result, crosstalk is a major signal integrity challenge for the implementation of a high-speed DDR3 interface in this low-cost system environment, and the PHY design has to meet tight timing and voltage requirements to allow for the distortions added in the package and the PCB routing channel.

5 II. Power Integrity Analysis II.1. Power Integrity Challenges Power Integrity is an important design consideration for high-speed interfaces. Supply noise in the PHY causes waveform distortions and delay variations, resulting in jitter, on interface signals and internal signals inside the PHY. Designing a high-speed interface system in a low-cost 4-layer wirebond package is particular challenging, since the supply inductance of such packages is comparably high and the bond wires allow rail-to-rail coupling between noisy digital supplies and very noise sensitive analog supplies. In order to achieve a high data rate it is therefore necessary to carefully analyze supply noise and its impact on the PHY circuits and interface characteristics. In general, there are two Power Integrity challenges in the design of high-speed interface systems that are best analyzed separately. The first power integrity challenge in high-speed interfaces is the distortion of signal quality and timing of the interface signals during Simultaneous Switching Outputs (SSO) events. SSO noise is a common problem in interface systems using single-ended signaling like DDR3 and it is discussed in detail in previous works [5]. Since the impact of SSO is strongly influenced by the interaction of the interface PHY with the external channel implementation in package and PCB, we will discuss SSO impact as part of the channel analysis. It is analyzed using a signal and power integrity co-simulation model described in a later chapter. The second challenge is the supply noise inside the PHY cause by the circuit activity of the PHY itself. This activity generates noise on all supply rails inside the PHY, including sensitive analog supplies, due to self-induced current changes or noise coupling from other system elements. This supply noise affects the performance of circuits inside the PHY, and in particular, it creates jitter in the timing circuits controlling the internal and channel timing of the interface system. The impact of power supply induced jitter (PSIJ) on the system margin of the interface has to be carefully analyzed and optimized to ensure reliable operation at the target data rate. In a DDR3 interfaces the timing on the DQ data bus is most critical, since these signals are transmitted at the full (double) data rate. The critical timing parameters on this bus are defined relative to data strobe signals, DQS. As a result, jitter that is shared between the DQ data signals and the DQS strobe signal is not affecting the system timing margin. This is particularly helpful during WRITE access, when both the DQ and DQS signals are generated in the PHY. Only PSIJ components due to DQ and DQS mismatches have to be taken into consideration for this operation. This mismatch can be minimized with a careful design of the timing paths inside the PHY. The clock signal, CK, generated by the PHY acts as a timing reference source for the internal DRAM timing and has to meet various jitter requirements defined in the DRAM specification. It also acts as timing reference for the control and address signals on the CA bus, but timing requirements on this bus are less critical since the CA bus only operates at half the data rate of the DQ bus. Meeting the jitter requirements of the DRAM specification, however, is not necessarily sufficient to operate the DDR3 interface at high

6 data rates. Jitter on the CK signal increases the output hold time parameter tqh of the DRAM device, reducing system margin during READ operations. It is therefore advisable to keep jitter on the CK signal very low, if possible even lower than required by the DRAM specification, to gain system margin during READ access. In the following chapter we will present a detailed PSIJ analysis for the CK signal path inside the PHY. II.2. Power Supply Model and Simulation Results The prediction of power supply noise plays a vitally important role in defining the voltage and timing budget for this low-cost wirebond DDR3 PHY design targeting at 1600Mbps up to 1866Mbps. Besides the common concern on the dynamic range of the supply noise, it is also crucial to understand the supply noise impact on the system timing jitter, or, power supply noise induced jitter (PSIJ). Previously, a systematic approach for predicting PSIJ by combining the supply noise spectrum and the clocking circuit jitter sensitivity has been developed [2]. The methodology flow is shown in Figure 1. In order to estimate the supply noise impact on jitter, this method seeks to obtain the jitter spectrum, J(f), which in turn can be obtained by multiplying the supply noise spectrum, V(f), and jitter sensitivity profile, S(f), all in frequency domain. The jitter sensitivity profile is solely determined by the circuit realization and independent of the circuit activity. On the other side, the supply noise spectrum is determined by both the power delivery network and the current profile, a variable depending on different circuit activity and data pattern. The following sections will first describe the supply noise analysis to obtain V(f) and then discuss the jitter sensitivity results of S(f) so that the final prediction of PSIJ in the DDR3 system can be evaluated. Four supplies are used in the implemented DDR3 test system, including VDDP, VDDA, VDDIO, and VDDR. The PLL is supplied by the dedicated VDDP supply. The clock distribution circuits operate on VDDA. The I/O circuits use VDDIO. The rest of the circuits, mainly the digital logic circuits for the data path, operate on VDDR. Since the entire clocking circuits are on VDDP, VDDA, and VDDR, it is expected that the main jitter contribution comes from the noise on these three supplies. The following discussions will focus on these three supplies, which are highly jitter sensitive. Figure 1. Methodology for predicting supply noise impact on jitter (PSIJ) [2].

7 R VRM L VRM R PCB L PCB R PKG L PKG R on-chip R PCBdecap R PKGdecap C decap V VRM L PCBdecap L PKGdecap R decap R shunt I fb i(t) C PCBdecap C PKGdecap Off-Chip PDN On-Chip PDN Current Profile Figure 2. Power supply model for pre-layout supply noise simulation. Figure 2 shows the power supply model topology used for the supply noise analysis. As shown in the figure, three components are required including off-chip PDN, on-chip PDN, and supply current profile. The off-chip PDN is modeled by passive RLC components resulting from voltage regulator, PCB, and package parasitics as well as low and medium frequency decoupling capacitors. The on-chip PDN represents the physical power grids from die pads to rest of the chip, typically includes RC parasitics and very importantly, on-chip decaps. The third component is the current profile, which is extracted from the circuit simulation and applied as the stimulus to the PDN. In order to evaluate both the worst-case switching noise and the steady state supply noise, it is desired to have the current profile extracted under the DDR3 PHY operating condition for bus turn-around. Figure 3 shows the data waveform under a WRITE-NOP-READ bus turn-around condition as well as the corresponding current profiles for VDDR, VDDA, and VDDP supplies. As can be seen from the figure, the VDDA and VDDP current profiles are independent of the operation modes while average VDDR current shifts significantly between the active WRITE/READ mode and the NOP mode. WRITE NOP READ DQ Signal 80 back-to-back PRBS, BL=4 ~300ns 80 back-to-back PRBS, BL=4 ~300ns i(vddr) avg=163ma peak=638ma avg=115ma peak=622ma avg=165ma peak=655ma i(vdda) avg=102ma peak=599ma avg=102ma peak=597ma avg=102ma peak=596ma i(vddp) avg=21ma peak=32ma avg=21ma peak=32ma avg=21ma peak=32ma Figure 3: Supply current profiles for bus turn-around, representing 300ns of continuous WRITE and 300ns of continuous READ with 150ns NOP in between.

8 WRITE NOP READ vddr ~20mV DC shift 10.2 mv pp 10.4 mv pp Due to Standby/Active Power Mode Transition vdda 18.8 mv pp 18.7 mv pp vddp 4.4 mv pp 4.2 mv pp Figure 4: Overview of VDDR, VDDA, and VDDP supply noise for the DDR test system. The power supply noise analysis is performed by applying the above current profiles to the power supply model shown in Figure 2. The overview of the supply noise simulation results are summarized in Figure 4. As the dedicated supply to PLL alone, the VDDP noise, independent of the activity mode, is around 5mVpp and. Comparing to the VDDP noise, the VDDA noise is significantly higher at around 19mVpp due to the strong switching activity generated by the clock buffers in the clock distribution circuits. The VDDA noise is also independent of activity mode and it remains stable as long as the clock distribution stays on. The VDDR noise exhibits strong dependence on mode of operation. The VDDR supply experiences significant DC IR shift between the active WRITE/READ mode and the non-active NOP mode. What matter the most are the switching noise during the transitions between the active and non-active operation modes and the steady state noise during the normal active modes for continuous WRITE or READ operation. The former usually leads to the worst-case supply voltage collapse and the latter determines how much net jitter impact it has on the timing budget of the system. As shown by the figure, the bus turn-around switching noise is as high as 25mVpp and the steady state noise is around 10mVpp. As will be discussed shortly, VDDP has the highest jitter sensitivity followed by VDDA and VDDR while its supply noise is relatively small. The net jitter contributions from the supply noise on each of these domains are discussed in the following sections. Figure 5-7 shows the details of the simulated supply noise in time-domain and frequency-domain under WRITE and READ conditions. The VDDR simulation results are shown in Figure 5, where the time-domain results indicate that the peak-to-peak noise is around 10mV. The noise spectrum results show that the major component is at the 1066MHz data rate, with sub-harmonic at 533MHz, and its higher-order harmonics. The obtained noise spectrum will be used to compute the PSIJ impact. Similarly, the VDDA simulation results in Figure 6 show that the swing is around 19mV with major frequency components are at 533MHz and 1066MHz. The VDDP noise simulation results are shown in Figure 7. The peak-to-peak noise is around 5mV and the frequency components are the PLL reference clock, its output clock and their higher-order harmonics.

9 10.2 mvpp 10.4 mvpp 8.2 mvpp (a) (b) LF/MF noise Data TX/RX LF/MF noise Data TX/RX (c) Figure 5: Simulation results of VDDR supply noise. (a)supply noise during WRITE, (b)supply noise during READ, (c)spectrum of supply noise during WRITE, and (d)spectrum of supply noise during READ. (d) 18.8 mvpp 18.7 mvpp (a) (b) Data Data TX/RX HF TX/RX HF LF/MF noise LF/MF noise (c) Figure 6. Simulation results of VDDA supply noise. (a)supply noise during WRITE, (b)supply noise during READ, (c)spectrum of supply noise during WRITE, and (d)spectrum of supply noise during READ. (d)

10 4.4 mvpp 4.2 mvpp (a) (b) half CK half CK LF/MF noise VCO freq harmonics LF/MF noise VCO freq harmonics (c) Figure 7. Simulation results of VDDP supply noise. (a)supply noise during WRITE, (b)supply noise during READ, (c)spectrum of supply noise during WRITE, and (d)spectrum of supply noise during READ. (d) II.3. Jitter Sensitivity and Jitter Spectrum PSIJ sensitivity is defined in frequency domain as the system jitter response to sinusoidal supply noise. Its magnitude profile represents how much jitter is induced by the supply noise with one unit of swing. Its phase profile represents how much phase difference between the supply noise and its induced jitter sequence in the steady state. The PSIJ sensitivity is solely determined by the circuit implementation and is independent of different circuit activity. Therefore, it is a system transfer function for characterizing the jitter impact induced by the supply noise. It serves as a key linking parameter between the supply noise as the stimulus and the jitter impact as the output response. The PSIJ sensitivity extraction methodology has been previously reported in [2]. It is applied here to extract the CK PSIJ sensitivity profiles for the DDR3 test system. The PSIJ sensitivity results for VDDR, VDDA, and VDDP are shown in Figure 8(a)-(c), respectively. As seen in the figure, the PSIJ sensitivity of VDDR and VDDA are relatively lower than that of VDDP. This is expected since the most sensitive block in the entire clocking path is the PLL circuit, which is solely supplied by VDDP. The VDDP sensitivity, as shown in Figure 8(c), exhibits a band-pass behavior with its peak of about 1ps/mV at around 10MHz, which roughly corresponds to the PLL loop bandwidth. The VDDA sensitivity, as shown in Figure 8(b), exhibits a low-pass behavior. This is also expected because VDDA supplies the entire clock distribution circuitry, where the major jitter sensitivity characteristic is due to the clock buffer delay change caused by the supply voltage variation, up to the circuit bandwidth.

11 (a) (b) (c) Figure 8: Simulated DDR3 PSIJ sensitivity profiles for (a)vddr, (b)vdda, and (c)vddp The final PSIJ is derived by combing the PSIJ sensitivity, S(f), and the supply noise spectrum, V(f). Each of these two required components has been addressed as above. One can compute the jitter spectrum J(f) as follows: J ( f ) V( f ) S( f ) (Eq. 1) The above jitter spectrum is a comprehensive characterization on the supply noise impact on jitter. It reveals magnitude and location of all the jitter components and relates their sources to the supply noise frequency components. It quantifies what frequency components of the supply noise make the most significant contribution to the final jitter impact. Moreover, the jitter spectrum serves as the basis to derive many important aspects of the jitter. For example, the time-domain jitter sequence is computed as follows: j ( t) ifft[ J( f )] ifftv [ ( f ) S( f )] (Eq. 2) By applying the above procedure, the jitter induced by the supply noise is derived to estimate the PSIJ contribution to the total jitter in the test DDR3 system. The results are summarized in Figures Figure 9 shows the VDDR PSIJ prediction results for continuous WRITE and READ modes. Figure 9(a) is the simulated jitter spectrum due to the VDDR noise during WRITE, showing that the major jitter components are at the CK frequency and the data rate. The corresponding time-domain jitter sequence is computed by using Eq.2 and is shown in Figure 9(c). From the figure, the peak-to-peak jitter is found to be around 3.3ps. Figure 9(e) further shows the histogram of the jitter sequence so that the PSIJ statistical property can be revealed, e.g., distribution form, peak-to-peak value, and deviation, etc. Similarly, the VDDR PSIJ results under READ condition in terms of jitter frequency-domain spectrum, time-domain sequence, and statistical histogram are shown in Figure 9(b)(d)(f). The peak-to-peak jitter for READ is found to be around 2.9ps, which is slightly less than that in WRITE. Figure 10(a)-(f) show the VDDA PSIJ results. Although it is expected that the results are independent on WRITE or READ, the results under these two conditions are shown in the figure as a sanity check. As seen from the figure, the major jitter components are at the CK frequency at 533MHz and its 2 nd harmonic at 1066MHz. The peak-to-peak jitter is found to be around 2.4ps for WRITE and 2.2ps for READ. Figure 11(a)-(f) show the VDDP PSIJ results. Although the VDDP has the highest jitter sensitivity, the noise in its supply domain is not as big as those in VDDR or VDDA. As a result, the peak-to-peak jitter due to VDDP

12 noise is found to be about 1.8ps for WRITE and 2.0ps for READ. The major jitter contribution comes from the PLL reference clock at 133MHz as well as its 2 nd and 3 rd harmonics. (a) (b) (c) (d) (e) Figure 9: Simulated vddr PSIJ results for continuous WRITE and READ. (a) Spectrum of jitter induced by VDDR noise during WRITE, (b)spectrum of jitter induced by vddr noise during READ, (c)vddr PSIJ jitter sequence during WRITE, (d)vddr PSIJ sequence during READ, (e) VDDR PSIJ histogram during WRITE, and (f)vddr PSIJ histogram during READ. (f)

13 (a) (b) (c) (d) (e) Figure 10: Simulated vdda PSIJ results for continuous WRITE and READ. (a) Spectrum of jitter induced by VDDA noise during WRITE, (b)spectrum of jitter induced by VDDA noise during READ, (c)vdda PSIJ jitter sequence during WRITE, (d)vdda PSIJ sequence during READ, (e) VDDA PSIJ histogram during WRITE, and (f)vdda PSIJ histogram during READ. (f) (a) (b) (c) (d)

14 (e) Figure 11: Simulated vddp PSIJ results for continuous WRITE and READ. (a) Spectrum of jitter induced by VDDA noise during WRITE, (b)spectrum of jitter induced by VDDA noise during READ, (c)vdda PSIJ jitter sequence during WRITE, (d)vdda PSIJ sequence during READ, (e) VDDA PSIJ histogram during WRITE, and (f)vdda PSIJ histogram during READ. Although the above PSIJ results represent the steady state activity mode for continuous WRITE or READ, it is also important to estimate the worst-case pathological jitter impact. Since neither VDDA nor VDDP noise should be dependent on the activity mode, the major variable in noise source is the VDDR noise. However, the basis to construct such cases is not the supply noise spectrum itself. Instead, the determining factor is the peak jitter sensitivity frequency location. As suggested by the VDDR PSIJ sensitivity shown in Figure 8(a), the peaking occurs at 5~10MHz with about 0.5ps/mV. Therefore, the worst-case VDDR PSIJ should occur when the VDDR supply noise has major components at 5~10MHz. Such case can be emulated by stitching the active mode current profile with the non-active mode current profile with a repetition rate of 5MHz. Figure 12 shows the PSIJ results under such conditions. Figure 12(a) and (b) show the VDDR supply noise waveforms for pathological WRITE-NOP and READ-NOP cases. The DC shift is about 20mV between the active and non-active mode and the peak-topeak noise is about 25mV. The corresponding PSIJ jitter spectrum are plotted in Figure 12(c) and (d), showing jitter components as high as 10ps in magnitude at 5MHz. The resulting jitter sequences are plotted in Figure 12(e) and (f), where the significant 5MHz jitter component as well as its 10MHz harmonics can be clearly seen. Recall that the peak-to-peak supply noise for active mode is about 19mV during normal continuous WRITE or READ and the resulting PSIJ is about 3.3ps. In the pathological case, the peak-to-peak supply noise is about 25mV, which is 1.3x larger than that in the normal active mode. But the resulting jitter is about 34ps, which is 10x higher than that in the normal active mode. The constructed pathological case is thus useful to estimate the worst-case or upper bound of the PSIJ impact in the system. (f)

15 200ns NOP NOP NOP NOP NOP 100ns NOP 200ns NOP NOP NOP NOP 100ns 100ns ~20mV DC shift 100ns WR WR WR WR WR RE RE RE RE RE Figure 12: Worst-case vddr PSIJ estimation. (a)worst-case of WRITE-NOP with 5MHz repetition rate, (b)read-nop with 5MHz repetition rate, (c)vddr PSIJ spectrum for worst case WRITE-NOP, (d)vddr PSIJ spectrum for worst case READ-NOP, (e) VDDR PSIJ sequence under worst-case WRITE- NOP, and (f)vddr PSIJ sequence under worst-case READ-NOP. Table 1. Summary of PSIJ in DDR3 Test System Continuous WRITE Continuous READ Worst-Case WRITE Worst-Case READ Noise (mv, pp) PSIJ (ps, pp) Noise (mv, pp) PSIJ (ps, pp) Noise (mv, pp) PSIJ (ps, pp) Noise (mv, pp) PSIJ (ps, pp) VDDR VDDA VDDP Total PSIJ Impact (UI %) 1066Mbps Mbps Mbps With the above PSIJ results, it is now possible to understand the relative significance of jitter impact due to various supply noise sources as well as the net PSIJ contribution to the overall timing jitter. Table 1 summarizes the PSIJ impact in the DDR3 test system, including the simulated results for DDR3 at 1066Mbps as well as the extrapolated results

16 for DDR3 at 1600Mbps and 1866Mbps. For 1066Mbps operation, the net PSIJ impact to the overall timing jitter is about 0.81% and 0.73% of UI for normal continuous WRITE and READ modes, respectively. In each case, the VDDR noise has the biggest jitter impact, followed by VDDA and VDDP. Under the pathological cases, the VDDA and VDDP jitter impact remain the same but the VDDR jitter impact significantly increases. As can be seen in Table 1, the VDDR PSIJ impact increases from less than 0.35% of UI to as high as 3.5% of UI, a 10x increase over the normal active mode. By extrapolation, under the normal active mode the total PSIJ impact is predicted to account for 1.2% of an UI for 1600Mbps and 1.4% of an UI for 1866Mbps. Under the pathological cases, the total PSIJ impact is predicted to account for 6.1% of an UI for 1600Mbps and 7.1% of an UI for 1866Mbps. The results simulated or extrapolated here will be used for the overall timing budget analysis for the DDR3 test system, to be discussed in following sections. III. Channel Analysis and Signal Integrity The target of our design project was to generate a PHY that will reliably achieve the target data rate of 1600Mbps in a customer system. In order to achieve this target we have to analyze the performance of the PHY in the target system environment. It is common practice in the design of high-speed interfaces to define a voltage and timing budget (VT budget) that accounts for all timing and voltage uncertainties introduced by the various interface components in the system. The VT budget of the system is balanced at a given data rate if the sum of all timing errors is smaller than the bit time at the target data rate and the sum of all voltage errors is smaller than the initial voltage swing of the signaling system. Based on a balanced system VT budget, specifications can be derived for the different components of the interface system, assigning budgets of maximum voltage and timing error to each of the components. In a DDR3 interface system, the DRAM specification defines the voltage and timing uncertainty of the memory device at the target data rate. Additional voltage and timing errors are introduced by the passive channel between the controller and DRAM devices and by the controller PHY itself. The channel analysis of the target system allows us to quantify the voltage and timing error introduced by the channel and to define design specifications the controller PHY has to meet in order to close the system VT budget. Channel timing and voltage errors can be caused by many effects. We will break down our analysis into four separate analysis steps, each of them targeting a different source of channel errors that can be addressed and optimized separately. The first analysis investigates inter symbol interference (ISI) effects on a single data lane under nominal conditions. The second analysis targets crosstalk (Xtalk) between different data lanes. The third analysis investigates the impact of supply noise due to simultaneous switching outputs (SSO). Finally, the fourth analysis investigates the impact of parameter variations typical in high-volume manufacturing processes on the system margin. Each of these analysis steps uses the same channel model, which represents a reference implementation of a customer system using the developed PHY. We will focus on the analysis of the DQ channel, since this channel is operating at the highest data rate and has the most challenging VT budget to meet. A similar analysis was done for the RQ channel, but will not be presented in this paper.

17 III.1. Channel Model Overview Figure 13: Channel schematic of DDR3 SI/PI co-simulation analysis The DDR3 interface was designed in a wirebond package and a 4-layer PCB system for a data rate of 1600Mpbs. Signal and PDN models are shown in Figure 13 which includes driver, package, PCB, PDN models for both controller and DDR3 device. A detailed SI/PI co-simulation methodology was discussed in [4, 5]. First, transistor level driver models were used in the simulation for 5 DQ pins and strobe signals. The remaining signal drivers were modeled using current-controlled current sources, which limit the simulation complexity of the channel model but still maintain correct current waveforms on signal traces and the supply system. For wirebond package, both signal and power traces were modeled using a 3D EM solver tools to accurately model the coupling between signal and power rails. In order to reduce simulation complexity, the model was simplified using matrix reduction [6], combining the multiple supply traces for each supply rail. W-element model are commonly used for signal traces of the package substrate and PCB. 7 DQ lines, including 5 signal lines and 2 strobes, were modeled for the Xtalk and SSO analysis. Finally, lumped via and BGA balls models were used to stitch the channel together. III.2. Channel ISI Results In the targeted application, the DQ channel routes a point-to-point from the controller to a single DRAM device. Figure 14(a) and 14(b) show the passive channel AC response, and the single bit response. Since the channel is well terminated and the connection is point-to-point, channel distortion effects are small in the frequency range of interest. For 1600Mbps data rate, the attenuation S21 is -1.2dB, almost unaffected by the Ci loading of the channel, and reflection S11 is around -10dB. For frequencies beyond 1.4GHz Ci loading starts to limit

18 the channel performance. The single-bit response shows little ISI at the target data rate and only mild reflection. Read Write Figure 14(a): Channel transfer functions Figure 14(b): Channel signal bit response III.3. Crosstalk Analysis and Routing Optimization Crosstalk in the wirebond package and the PCB is a major margin loss for high performance and low-cost DDR3 system. In order to find out the main crosstalk contributors, we isolated the impact of each component for the write access case. Fig 15 shows the Xtalk breakdown for the whole passive channel. In this simulation the DQ victim line, located at the center of the five lines, is kept quiet while a single bit pattern is transmitted on the four aggressor lines surrounding the victim. The noise is observed at the DRAM pad of the victim line. Fig 15 shows the crosstalk simulation results for the package and several PCB routing options. Special care was taken during the design of the wirebond package to minimize the crosstalk contribution of the bond wires, as described in [8]. The remaining crosstalk in the package (+/- 6% of Vnom) was considered unavoidable given the technology constraints of the package design and the pad limitation of the PHY. The goal was to limit the contribution of additional crosstalk in the PCB routing of the channel. The signal routing on the 4-layer PCB was done using microstrip lines. All the trace routing examples are shown in Fig 16(a). Starting from an earlier routing strategy (Figure 16(b)) the impact of trace spacing on crosstalk of the channel was analyzed. Figure 15 shows the crosstalk impact for different routing implementations. We can see that both 2W and 3W spacing result in significantly higher crosstalk than that of the package alone. For 100mm microstrip line length, crosstalk are +/-13% and +/-10% for 2W and 3W spacing, respectively. It would have been difficult to close the system VT budget at the target data rate under these conditions. Therefore, we changed the routing strategy for the PHY, shortening the DQ bus and at the same time providing more space between DQ traces to add ground guards (Figure 16(c)). This reduced the crosstalk impact on the victim to +/-8%, only marginally higher than the package crosstalk alone. The new routing strategy required a change in the floor plan and pad-out of the PHY, giving an example of the feedback between channel analysis and silicon design in order to optimize the system performance of the final PHY.

19 Figure 15: Channel xtalk contribution breakdown (a) (b) (c) Figure 16: PCB trace routing optimization. (a)trace spacing study, (b)initial routing topology, (c)final routing topology III.4. SSO Analysis The channel model introduced earlier is an accurate model of the power supply network for the silicon, the package, and the PCB. This supply model covers the VDDR and VDDQ supplies used for the output driver and pre-driver circuits of the PHY. Correspondingly, the transistor-level driver models used in the SI/PI co-simulation contain the pre-driver and main driver circuits, generating accurate current profiles on these rails during SSO analysis. The analysis is extended to VDDR to cover the impact of VDDR noise on the pre-driver and the resulting jitter during SSO. This SSO contribution can be significant at higher data rates [4].

20 Since supply noise during SSO is strongly dependent on the data pattern transmitted by the output drivers, the impact of different pattern on the system margin was tested to identify the worst-case pattern. The tested patterns were PRBS, pattern targeting the package-chip resonance on VDDR-VSS and VDDQ-VSS, and pattern targeting the highest impedance between DQ signals and VDDQ/VSS supply traces, which is the return path loop for push-pull drivers used in DDR3. Figure 17 shows the eye opening for the different pattern. It shows that the smallest eye opening was achieved using PRBS pattern. This pattern was therefore used for further SSO margin loss analysis. Figure 17: SSO Margin Loss for Different Data Pattern III.5. High volume manufacturing sensitivity analysis To ensure high performance under high volume manufacturing variations, statistical and sensitivity analysis has been widely used. Taguchi method has been introduced and discussed before [7]. Table 2 lists all the parameter manufacturing variations which dominate the channel performance. Other channel parameters have small impact on VT budget and are not listed in this paper. Channel Parameters Variation Tx driver impedance ( ) 34 +/- 10% On-die-termination ( ) 60 +/- 20% CTR Ci (pf) 2.5 +/-10% DRAM Ci (pf) 2 +/- 10% CTR pkg trace impedance ( ) 70 +/- 15% PCB trace impedance ( ) 55 +/- 15% Table 2: Channel parameter manufacturing tolerance Figure 18 shows the impact of each parameter on the system margin during ISI analysis, as these parameters are varied. It shows that Ci, PCB trace impedance, and driver impedance have the largest impact on system margin.

21 Figure 18: PCB trace routing optimization Assuming homogeneous distribution of all parameters and no interactions among parameters, margin loss due to channel variation is found to be 10%, shown in Figure 19. This margin loss is included in the finial VT budget. (a) Figure 19: Distribution of total margin for Write and Read operation III.6. Channel Simulation Summary Figure 20 shows the eye diagrams during write access, simulated at the DRAM pin, for the cases of ISI alone, ISI and crosstalk, and ISI and crosstalk and SSO noise. It shows that crosstalk and SSO both have a significant impact on the eye opening, but there is still significant eye opening at the DRAM pin at 1600Mbps. (b)

22 Figure 20: Eye Diagrams at 1600Mbps during Write Operation for Nominal Channel In order to verify that the interface meets the system VT budget at this data rate, the eye passing range was extracted based on the definition of V AC and V DC in the DDR3 specification [3]. For the write access case, ISI alone results in a passing window of 74% UI, including channel variation effects. Worst-case crosstalk reduces this passing window by 10% UI, another 13% UI is reduced by SSO. From this passing window range, the setup and hold time (ts, th) of the receiver, the timing uncertainty of the transmitter (tq), and the worst-case timing mismatch of strobe and signal traces (tskew) has to be subtracted, as shown in Figure 21. The system meets the system VT budget if the passing range of the eye diagram is equal or larger than ts+tq+tcal+th. This condition was used to define the tq (for Write access) and ts/th (for Read access) requirements of the PHY. The PHY meets these conditions for all PVT corners and can operate in a system at the target data rate of 1600Mbps for any DRAM device meeting the specification for this speed grade. III.7. Channel Model Correlation Figure 21: System Timing Parameter Breakdown In order to verify the model accuracy and simulation methodology, DDR3 PHY and system board have been implemented and tested at 1600Mbps and higher. Since controller and DRAM packages and other components are placed on the top of the PCB, the probing points are visible and accessible for measurements on the back side of PCB,

23 shown in Figure 22. Same channel topology has been constructed and simulated to compare with the lab results. Figure 22: System level measurement setup As an example, write operation step and single-bit response have been measured and correlated in Figure 23. Measured results were recorded at probe A and B, CTR and DRAM side respectively. All the channel impedance and trace length were adjusted based on channel TDR results. Good correlation was achieved between measured and simulated results for step and single bit response, as well as the eye diagram probed at the DRAM PCB via side shown in Figure 24, verifying the channel model and simulation setup. (a) Step response Figure 23: Step and single bit response correlation for Write case (b) single-bit response (a) Measured eye Figure 24: Channel eye diagram correlation at 1600Mpbs (b) Simulated eye

24 IV. Summary A DDR3 interface PHY for data rate of 1600Mbps targeting consumer electronic products was implemented. The interface was designed to operate reliably in a low-cost system environment using a wirebond package and a 4-layer PCB. In this environment, supply noise, crosstalk, and clock jitter are serious challenges and have to be carefully optimized in order to close system-level timing at this high data rate. In this paper we presented the signal and power integrity analysis supporting this design. First, we analyzed the supply noise inside the PHY and predicted the jitter caused by this noise. The analysis shows that power supply induced jitter can contribute up to 6.1% of jitter to the clock signal forwarded to the memory device, causing margin loss especially during read access. Next, we analyzed the channel performance in this environment and identified the margin loss due to ISI, crosstalk, SSO effects, and parameter variations under highvolume manufacturing conditions. We showed that crosstalk in the PCB in the targeted environment can have significant impact on signal integrity and how this was addressed in the design through routing optimization and PHY floor plan changes. Using the analysis results for jitter and channel we analyzed the system timing budget to verify that the PHY will operate reliably at the target data rate using any DRAM device meeting the DDR3 specification for this speed grade. The DDR3 PHY was implemented on a test chip and a memory interface was designed using the low-cost system environment using a 4-layer wirebond package and a 4-layer PCB board. The system achieves reliable memory operation at 1866 Mbps using DDR3 memories of 1600 Mbps speed grade, demonstrating the headroom of this design at nominal conditions. V. References [1] C. Yuan, W. Beyene, N. Chang, and H. Shi, Design and modeling of a 3.2Gbps/pair memory channel, 11 th Topical Meeting on Electrical Performance of Electronic Packaging, pp , Oct.2002 [2] H. Lan, R. Schmitt, and C. Yuan, "Prediction and measurement of supply noise induced jitter in high-speed I/O interfaces," in Proc. of DesignCon 2009, Feb. 2009, Santa Clara, CA. [3] DDR3 SDRAM Specification, JESD79-3B, JEDEC Solid State Technology Association, April 2008 [4] D. Oh, W. Kim, J.-H. Kim, J. Wilson, R. Schmitt, C. Yuan, L. Luo, J. Kitzer, J. Eble, F. Ware, Study of Signal and Power Integrity Challenges in High-Speed Memory I/O Designs Using Single-Ended Signaling Schemes, DesignCon 2008, Santa Clara, CA, Feb., 2008

25 [5] R. Schmitt, JH Kim, C Yuan, J Feng, WP Kim and D Oh, Power Integrity Analysis of DDR2 Memory Systems during Simultaneous Switching Events, DesignCon 2006, Feb. 6-9, 2006, Santa Clara [6] M. Ha, JH Kim, D. Oh and M. Swaminathan, A Study of Reduced-Terminal Models for System-Level SSO Noise Analysis, 19 th Topical Meeting on Electrical Performance of Electronic Packaging, pp 49-52, Oct.2010 [7] W Beyene, N Cheng, J Feng and C. Yuan, Statistical and Sensitivity Analysis of Voltage and Timing Budgets of Multi-Gigabit Interconnect Systems, DesignCon, 2004, Jan. 29-Feb. 1, Santa Clara, CA [8] Y. Lu, R. Dhat, D. Dressler, J. Feng, T. Giovannini, M. Katakwar, R. Schmitt, D. Secker, A. Vaidyanath, R. Vu, Low Cost DDR HDTV/STB Memory Interface Co-design Approach, DesignCon 2011, Jan. 29-Feb. 1, Santa Clara, CA