Impact of NFSI on the clock circuit of a Gigabit Ethernet switch

Transcription

1 Impact of NFSI on the clock circuit of a Gigabit Ethernet switch Massiva Zouaoui, Etienne Sicard, Henri Braquet, Ghislain Rudelou, Emmanuel Marsy and Gilles Jacquemod

2 CONTENTS 1. Context 2. Objectives 3. Methodology 4. Experiments 5. Modeling Approach 6. Conclusion

3 CONTEXT HARSH ENVIRONMENT Industrial Electronic Control Harsh environment Temperature, Vibration, Humidity Industrial noise, voltage overstress Systems must be highly robust to Electromagnetic Interference But Increased system performances

4 CONTEXT - SUPPLY DECREASE Less supply, less power dissipation Less noise margin Supply (V) Increased performances Qualcomm Snapdragon X50 10-nm I/O supply 0.7 V inside, 1.2V outside Core supply 0.35µ 0.18µ 130n 90n 65n 45n 32n 20n 14n Technology node 10n 7n

5 CONTEXT - MORE GIGA BITS Multi-Giga-Bit link between processors & memories UHD video, object recognition, 3D capture Less noise margins (reduced voltage swing) Less delay margin (shorter symbols) Data Rate per pin (Gb/s) 100 Gb/s DDR3: 1.5 ns 1.5 V swing DDR4: 300 ps 1.0 V swing DDR4x: 250 ps 0.30 V swing 4-PAM 0.15 V swing Graphics trends 10 Gb/s GDDR2 LP2 DDR2 GDDR3 LP3 DDR3 GDDR4 LP4 DDR4 GDDR5 LP4x DDR4x GDDR6 LP5 DDR5 Low power trends DDR trends 1 Gb/s

6 OBJECTIVES Question: EM field margin? Sensitive function? Any possibility to predict the EM margin in new products? At Schneider Electrics, a 3-years research project has been setup to investigate immunity simulation of systems Until now Post verification Goal - Prediction Cooperation with Polytech Nice & INSA Toulouse

7 CHALLENGES & OPPOORTUNITIES Challenge: Complete system, very difficult to isolate a single device from its environment Little knowledge of the IC Complex susceptibility criteria (loss of function) Opportunities EMC labs Schneider for compliance to standards NEXIO for IC-level measurements Technology analysis form SERMA IBIS models from IC manufacturer CST Studio tool for 3D EM prediction Support for NFSI (A. Boyer, S. Serpaud) IC-EMC software (A. Boyer, E. Sicard) Test-bench Schneider Electrics, radiated immunity

8 IMMUNITY MEASUREMENT METHODS IEC standards 47A WG2, WG9 (O. Wada, F. Klotz ) Almost no other choice

9 NEAR FIELD SCAN IMMUNITY Local No need for specific board Wide band Low cost A. Boyer, Characterization of the Electromagnetic Susceptibility of Integrated Circuits using a Near Field Scan, Electronics Letters, 2006

10 NEAR FIELD SCAN IMMUNITY Pros: Test-bench NEXIO, France Possibility to inject significant perturbation in 3D structures Localized energy to detect weak points Wide band (1 MHz-6 GHz) More than 10 publications Cons: Coupling probe to DUT not very efficient No standardized probe design Probe developed by S. Serpaud, NEXIO

11 EXPERIMENTAL RESULTS 500 MHz 628 MHz 880 MHz GES immunity to Hy, 2mm above the IC, Prototype 1 Technology analysis by SERMA Clock area seems sensitive One IO port seems sensitive Similar results in Hx orientation

12 MODELING APPROACH RF generator model Injection model Coupling path model Functionnal model Susceptibility criterion model Perturbation source Extraction of power injection Injection device model PCB model DUT input structure model, protection diodes Passive Decoupling Network Internal Behavior Behaviour of sensitive & nonlinear parts Power limit Voltage threshold Overcurrent

13 MODELING THE CLOCK-GES LINK Radio Frequency Interference VDD Injection probe Fly over the GES VDD PHY Clock Distance to PCB GES P5_GTXCLK PCB model Sensitive input pin QFP Package model BGA Package model GND GTXCLK Immunity simulation GND PHY

14 3D RECONSTRUCTION OF THE GES Use GES IBIS information Add some physical parameters Reconstruct 3D view in IC-EMC Package cavity 10 x 10 mm Near-magnetic field injection probe Package pitch 0.4 mm Bonding wire between the silicon die and package Silicon die 8 x 8 mm Package height 26 mm VDD pins VSS pins NC pins

15 PROBE COULING TO PCB Very low efficiency below 50 MHz (<<1%), on a 50-Ω calibration probe Very near field but NOT a d 3 law : more or less linear Around 1% coupling at D=1mm, 500 MHz J. Raoult Electromagnetic Coupling Circuit Model of a Magnetic Near- Field Probe to a Microstrip Line, EMC Compo 2015 D=0,1 mm D=3 mm

16 USE OF IC-EMC IRF NFSI Probe Clock generator PCB GES Freeware tool for simulation of EMC of ICs

17 MODELING THE CLOCK Power signal : 100 V range Victim signal: 100 mv range Criteria Simulated power (dbm) Real measured failure Power (dbm) +/- 200mV /-350mV /- 1V 41 33

18 SYSTEM SIMULATION Built a link between NFSI and far-field illumination What if simulations at system level using CST studio With/without shielding: forecast EM margins

19 CONCLUSION The immunity of industrial Giga-Bit Ethernet Switch has been analyzed Near-Field Scan in Immunity has been used to identify sensitive zones Comparative immunity measurements were made for 2 versions of IC A modeling approach has been conducted to estimate injected power to failure System EM has been conducted to evaluate margins in different situations A bridge could be made between IC, PCB and system level immunity

20 MORE ABOUT IC-EMC

21 Thank you for your attention M. Zouaoui, Study and modelling of electromagnetic susceptibility in complex digital systems, PhD report, 2017, Nice University, France

22 TEST BOARD DEVELOPPED EMC test boards 10 x 10 cm Main IC isolated on one side Other ICs, IOs, Clocks and Ethernet ports on the other side Easy scan by NFSI Whole control remain complex In case of packet losses, function losses, the whole system must be reset