ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS MEASUREMENT, MODELLING AND DESIGN TECHNIQUES I. EMC ISSUES

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1 TOULOUSE ELECTROMAGNETIC COMPATIBILITY OF INTEGRATED CIRCUITS MEASUREMENT, MODELLING AND DESIGN TECHNIQUES Etienne SICARD Professor INSA/DGEI University of Toulouse Toulouse - France Etienne.sicard@insa-toulouse.fr Best place to study in France ( rankings) (heavy responsibility) Founded in -120 B.C (heavy history with 4 golden periods) Airbus A380 (heavy airplane) Cassoulet (heavy food) Rugby (heavy efforts) 1 2 SUMMARY I. EMC ISSUES II. EVOLUTION OF ICS AND CONSEQUENCE ON EMC III. MEASUREMENT OF IC EMISSION AND SUSCEPTIBILITY IV. MODELS FOR EMC SIMULATION V. DESIGN GUIDELINES FOR IMPROVED EMC VI. CONCLUSION I. EMC ISSUES 3 4 EMC ISSUSES INDUSTRIAL PRESSURE EMC OF ICS IS 50 YEARS OLD Air Force Weapon Laboratory, USA SPECTRE SUSCEPTIBILITY EMISSION Carbon airplane Equipements Personal entrainments Mobile phone Effects of the electromagnetic fields trigged by nuclear explosions on electronic devices Simulation software developed at IBM (Sedore, 1965) Correlate simulations and experimental measurements obtained on an electromagnetic impulse test-bench. Radar Components Boards Safety systems Control Systems 10/25/2013 System-on-chip Floorplanning - EMC

2 EMC MARGIN EMC MARGIN Emission MIXING EMISSION and AND IMMUNITY LEVELS immunity levels (db) Immunity Security margin Emission Interference risk Small margin Frequency (MHz) Emission Immunity 7 LINK BETWEEN MARGIN AND Why APPLICATIONS a margin Acceptable noise level Security Process variations Measurement error Ageing Environment Required noise level Ioff/Ion MOS 32-nm Margin depends on application Immunity vs. ageing (LTOL) Domain Life time Margin Aeronautics 30 years 40 db Automotive 15 years 20 db Mobile phone 1 year 0 db PhD A. C. Ndoye, INSA, LOW EMISSION = DIFFERENTIATOR THE IC IS AN ANTENNA EMC IS THE 3RD CAUSE OF IC REDESIGN UNINTENTIONAL ELECTROMAGNETIC SOURCES Power HF VHF UHF SHF xhf THF dbµv Supplier A A FM RF GSM Not EMC compliant Customer's specified limit 1GW 1MW 1KW 1W Thunderstorm impact TV VHF TV UHF 2-4G BS 4G 2G 3G Radars Weather Radar Fields radiated by electronic devices Continuous waves & pulsed waves 40 B 1mW Frequency 3 MHz 30 MHz 300 MHz 3 GHz 30 GHz 300 GHz 20 EMC compliant 25m 2.5m 0.25m 25mm 2.5mm 0.25mm λλ/4 (idealantenna) TECHNOLOGY GIGA-DEVICE ICS II. EVOLUTION OF IC TECHNOLOGY AND CONSEQUENCE ON EMC Technology Complexity 130nm 100M 90nm 250M 45nm 500M 32nm 2G 22nm 7G 5nm 150 G Packaging Embedded blocks 2004 Core+ DSP 1 Mb Mem 2006 Core DSPs 10 Mb Mem 2008 Dual core Dual DSP RF Graphic Process. 100 Mb Mem Sensors 2010 Quad Core Quad DSP 3D Image Proc Crypto processor Reconf FPGA, Multi RF 1 Gb Memories Multi-sensors ?

3 HIGHER PARASITIC EMISSION INCREASED SWITCHING DEVICE PERFORMANCES Current drive (ma/µm) Strain to increase mobility High K Metal Gate to increase field effect Tri-Gate for increasing drive current and reducing leakage EVOLUTION TO 3D TERRAZON PROCESS WITH DBI & FLIP CHIPS Process accessible by CMC, CMP and MOSIS for academics, SME and industries Gate material Strain Direct bond interconnect 0.0 Intrinsic performances 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 17 nm Technology node From CMP annual users meeting, 3D-IC Integration, January 20th 2011, PARIS October HIGHER PARASITIC EMISSION SUSCEPTIBILITY ISSUES WHY TECHNOLOGY PROGRESSES INCREASE EMISSION DECREASED NOISE MARGIN IN ICS Volt Old process The current amplitude is a little reduced The switching is faster Supply (V) mv margin 100 mv margin New process Time Vdd 3.3 I/O supply di/dt Current New process Old process Time Vss i V = L t The noise is increased Core supply 0.5µ 0.35µ 0.18µ 130n 90n 65n 45n 32n 22n 17n Technology Adapted from ITRS roadmap for semiconductors, IC VULNERABILITY IC VULNERABILITY FROM SUSCEPTIBILITY TO VULNERABILITY THE 7 STAGES TO DESTRUCTION Current IESD IEMC Destruction Destruction Critical thermal effect Thermal stress Avalanche IC operation area Safe ESD protection window IC Reliability constraints VESD VEMC Early effect Saturation IC linear susceptibility IC non-linear susceptibility IC vulnerability Voltage Adapted from Lowering Component Level HBM/MM ESD Specifications and Requirements, Industry Council on ESD Target Levels, White Paper nm CMOS, L=60nm, W=66µm, VDD=1.2 V, TOXE=2 nm, VTO=0.24 V Nominal linear behavior Gain compression Adapted from «Approche topologique de la complexité», P. Hoffmann, CEA Gramat, AREMIF

4 MEASUREMENT OF EMISSION STANDARD EMISSION MEASUREMENT METHODS IEC III. MEASUREMENT OF IC EMISSION & SUSCEPTIBILITY IEC (TEM : 1 GHz) IEC /6 (Near-field Scan, 5 GHz) IEC (1/150 Ω, 1 GHz) IEC (Mini-stripline) IEC (Mode Strirred Chamber : 18 GHz) Ext : IEC (GTEM 18 GHz) MEASUREMENT OF EMISSION MEASUREMENT OF SUSCEPTIBILITY SMALL MAGNETIC PROBE (IEC , -6) A Zoom on Near-field Scan IEC STANDARDS FOR SUSCEPTIBILITY Y axis 32 MHz scan High IEC (Bulk Current Inj. 1 GHz) IEC (Direct Power Inj.1 GHz) IEC (TEM/GTEM) X axis Emission IEC (Ministrip 5 GHz) IEC : (LIHA : 10 GHz) IEC (NFS 10 GHz) Low 32 MHz Frequency ZOOM ON DPI ZOOM ON NEAR-FIELD IMMUNITY SUSCEPTIBILITY CHARACTERIZATION Much more complex and time consuming than emission : example of one DPI Signal generator Device under test Oscilloscope SUSCEPTIBILITY CHARACTERIZATION Near-field immunity coupling upto 6 GHz using a small loop (IEC ) Coupling Capacitance DUT Dout Good signal Magnetic loop IEEE Bus 10W Amplifier PC Monitoring Printed Circuit Board Power increase loop until failure Frequency loop 1 MHz 3 GHz or Failure signal Result example

5 EMC-AWARE DESIGN CYCLE EMC VALIDATED BEFORE FABRICATION IV. MODELS FOR EMC SIMULATION Architectural Design DESIGN Tools Training Design Guidelines Design Entry Design Architect EMC Simulations Compliance? NO GO FABRICATION EMC compliant IBIS STANDARD IBIS LINK TO EMC IBIS ELECTRICAL IC BEHAVIOUR FOR SIGNAL INTEGRITY Version Ibis v2 V3 V4 V5 Features I/O model with simple R,L,C, I/V Differential Ios, high speed Macromodels, preemphasis Non-ideal supply, statistical approaches for SerDes Macrolanguage IBIS LINK TO EMC I V 180 Parameters Z(Ω) I/O C_comp Lpack Keywords v1 v2 v3 v4 v5 Sub-params Selections IBIS 5.0, Aug. 29, 2008, on line at MHz 1 GHz Rpack Freq I/V curves [-VDD..+2VDD] range Key parameters for Z(f) of each IO Package R,L,C Ccomp Starting IBIS v5: non ideal supply, resourcing params 28 IEC STANDARD MODEL APPROACH GENERIC FLOW IEC EMISSION (ICEM) AND IMMUNITY (ICIM) MODELS Conducted mode models in industrial use EMC SIMULATION FLOW AT IC LEVEL The DUT is isolated on a simple EMC board to minimize modeling effort 1. ICEM-CE - Conducted RF emission 2. ICEM-RE - Radiated RF emission Test bench Test board Package Core I/O Simulation 4. ICIM-CI - Conducted RF immunity 4. ICIM-RI - Radiated RF immunity EMC for the circuit Measurement Electrical Simulation

6 EMISSION CASE STUDY EMISSION CASE STUDY INFINEON TRICORE - TEM CELL MODEL Capacitance coupling to the TEM cell Conversion to Win-SPICE INFINEON TRICORE - TEM CELL EMISSION Infineon TriCore measurement/simulation comparisons Radiated noise in GTEM cell (dbµv) Test board 1.0A 0.5A Probe 6.6ns (150MHz)) 0A Core current model Analog Time-Domain Simulation Fourier Transform Measure Correct envelop Reasonable match Simulation 15 db above measurement starting 700 MHz Manual fit leads to 5 db max difference Package Core db vs Freq (log) conversion IEC STANDARD MODEL APPROACH IMMUNITY SIMULATION IEC ICIM CONDUCED IMMUNITY Based on ICEM, add non-linearities ICIM immunity model Package RF disturbance Coupling path Monitoring of the failure IB S12X CASE STUDY DPI ON AN INPUT External pins Package Close to ICEM- CE IC Silicon die = Passive Distribution Network Internal Behaviour IB Close to ICEM Add Diodes (camp, back-toback, ESD, EOS) detection New! Package 16 bit micro-controller Direct power injection Input buffer aggression Sinusoidal mode Simulation criterion: Logical change of input buffer From A. Boyer s PhD, INSA, DOWN-SCALING TO MULTI-DIES package Integrated Circuit (ICEM, ICIM) Sub-component Silicon Die/ Intellectual property Passive Distribution IA Network Internal activity Integrated Circuit (ICEM, ICIM) Sub-component VI. DESIGN GUIDELINES FOR IMPROVED EMC Embedded passives IB Immunity Σ,Π behavioral Silicon die Other silicon die Other sub-component

7 GUIDELINE 1 : REDUCE THE INDUCTANCE Why: because inductance is a major source of resonance Where is the inductance: in each conductor, worst is far from ground VDD GUIDELINE 2 : PLACE VDD/VSS CLOSE TO STRONG DI/DT Tools required to forecast strong di/dt effects Multiple VDD, VSS IC VDD VSS L=1 nh/mm VSS GUIDELINE 3 : PLACE VDD-VSS CLOSE GUIDELINE 4 : USE ONE VDD/VSS FOR 10 I/OS to reduce current loops that provoke magnetic field to increase decoupling capacitance that reduces fluctuations Added contributions Canceled contributions Canceled (-20 db) EM wave current 9 I/O ports Lead Die Lead Added Correct Fail GUIDELINE 4 : USE ONE VDD/VSS FOR 10 I/OS FPGA CASE STUDY Same power, same IO characteristics. The pin assignement and power supply strategy differ; GUIDELINE 4 : USE ONE VDD/VSS FOR 10 I/OS FPGA CASE STUDY Good design: moderate noise during IO switching Poor design: x 5 mode switching noise Dr. Howard Johnson, "BGA Crosstalk", Dr. Howard Johnson, "BGA Crosstalk",

8 GUIDELINE 5 : BALANCE VDD/VSS PINS GUIDELINE 5 : PLACE ON-CHIP DECOUPLING CLOSE TO STRONG DI/DT 1nF added close to the core More than 15 db noise reduction Fail Fail Correct 43 10/25/2013 Graduate Student Meeting on Electronic Engineering - Tarragona B.Vrignon CESAME test-chip IEEE Trans EMC GUIDELINE 5 : PLACE ON-CHIP DECOUPLING CLOSE TO STRONG DI/DT Filler-cap at the output buffer area GUIDELINE 6 : ADD JIITTER ON THE CLOCK Pad High speed port Highest core activity Noisy charge pump Protection circuit VDD Protection circuit VSS -8 db Low noise, no decap High speed port Core Filler-cap B. Vrignon, Freescale SAS GUIDELINE 7 : ADD RC FILTERING AT WEAK POINTS GUIDELINE 8 : CLAMP ELECTRICAL OVERSTRESS RC filtering works both for emission and immunity Susceptibility level RC Code +/- 10 V RFI +5 V -5 V LOW ENERGY EMI 1000 V/m, 1 cm antenna 10 V RFI Diodes turned on Parasitic currents Signal faults Thermal effects Minor instability Isolated Core Ali ALAELDINE, PhD Eseo France Normal Core Frequency (MHz)

9 CONCLUSION GUIDELINE 9 : NEVER TRUST YOUR R,L,C 1 Ohm resistance Capa 47 pf Higher complexity and frequencies, technology scale down make EMC more and more challenging EMC starts to be investigated in the design flow Mature standard measurement methods dedicated to ICs New standards for EMC modeling at IC level Good prediction of emission and susceptibility up to 2 GHz Research need to extend these methods to 18 GHz REFERENCES REFERENCES Books Workshops Standards Trainings Tools EMC Compo in Dec Nara Japan IEC 61967, 2001, Integrated Circuits emissions IEC 62132, 2003, integrated circuits immunity IEC 62433, 2006, Integrated Circuit IEC 62215, 2009 Transcient immunity Sept 23-27, Merci beaucoup à Prof. Dr. Dirk JANSEN Hochschule Offenburg The MPC Family 53 9