Chip and Package-Level Wideband EMI Analysis for Mobile DRAM Devices

Transcription

1 DesignCon 216 Chip and Package-Level Wideband EMI Analysis for Mobile DRAM Devices Jin-Sung Youn, Samsung Electronics Inc. Jieun Park, Samsung Electronics Inc. Jinwon Kim, Samsung Electronics Inc. Daehee Lee, Samsung Electronics Inc. Sangnam Jeong, Samsung Electronics Inc. Junho Lee, Samsung Electronics Inc. Hyo-Soon Kang, Samsung Electronics Inc. Chan-Seok Hwang, Samsung Electronics Inc. Jong-Bae Lee, Samsung Electronics Inc.

2 Abstract In this paper, we develop a near-field scan (NFS)-based electromagnetic interference (EMI) analysis methodology for mobile dynamic random-access memory (DRAM) applications. As data rates of mobile DRAM from low-power double data rate2 (LPDDR2) to LPDDR4 continuously increases, their radiated energy could affect the sensitivity for GHz wireless communications such as GSM, LTE, GPS, Bluetooth, and WLAN. To overcome sensitivity degradation issue, EMI analysis and design techniques should be conducted in the product development process, and furthermore, the analysis should be validated for wideband spectrum up to GHz. In this paper, we focus on the development of chip and package-level EMI analysis methodology for mobile DRAM devices. The simulation results have correlation with the NFS measurement results less than 3 db over wideband frequency up to 2.5 GHz. With this methodology, EMI performance of chip and package design would be evaluated in early design stages so that improvement design techniques could be explored and design re-spins could be prevented through the simulation.

3 Author(s) Biography Jin-Sung Youn received the B.S. degree in Information and Telecommunication Electronics Engineering from Soongsil University, Korea, in 27. He received the M.S. and Ph.D. in Electrical and Electronic Engineering from Yonsei University, Korea, in 214. His doctoral dissertation concerned the high-speed and power-efficient 85-nm Si optoelectronic integrated receivers for optical interconnect applications. In 214, he joined the Samsung Electronics, Gyeonggi-do, Korea, where he is currently a Senior Engineer. His current research interests include the area of design methodology that include signal integrity (SI), power integrity (PI), electromagnetic interference (EMI), and electrostatic discharge (ESD). Jieun Park is working as an Assistant Engineer in Samsung Electronics, Korea. Jinwon Kim is working as a Senior Engineer in Samsung Electronics, Korea. Daehee Lee is working as a Principal Engineer in Samsung Electronics, Korea. Sangnam Jeong is working as a Senior Engineer in Samsung Electronics, Korea. Junho Lee is working as a Senior Engineer in Samsung Electronics, Korea. Hyo-Soon Kang received the B.S., M.S., and Ph.D. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, Korea, in 22, 24, and 29, respectively. His doctoral dissertation concerned CMOS-based Si optoelectronic devices and their applications to microwave/millimeter-wave photonics systems. In 29, he joined the Samsung Electronics Ltd., Hwasung-si, Gyeonggi-do, Korea, where he is currently a Principal Engineer. His research interests are in the area of signal integrity (SI), power integrity (PI), electromagnetic interference (EMI), and electrostatic discharge (ESD) of semiconductor packages. Chan-Seok Hwang received the M.S. degree in Electronics from Hanyang University, Korea, in 1997 and the Ph.D. degree in Electrical Engineering from the University of Southern California, CA, in 26, respectively. From 199 to 21, he was with the Semiconductor Business, Samsung Electronics, Korea. In 26, he joined Samsung as a Principal Research Engineer, where he works on memory chip and package design methodology. Jong-Bae Lee is working as a Vice President in Samsung Electronics, Korea.

4 Introduction As operating speed of today s various electronic systems such as mobile phone, tablet, and notebook continuously increases, an electromagnetic interference (EMI) becomes a critical issue [1-5]. Especially, it could be more considerable problems in mobile system since various chips, components and sockets/connectors are densely mounted in a smallsize printed circuit board (PCB) as shown in Fig. 1. Thus, there are many concerns about radio-frequency interference (RFI) because EM noises generated by various chips, components, and antennas are highly coupled to the each other, and consequently, it may exacerbate sensitivity of the received signal for various wireless communications such as GSM, LTE, GPS, Glonoss, Bluetooth, and WiFi as shown in Fig. 1. Camera Module emmc PMIC EM Radiation AP+LPDDR Glonoss Receiver WiFi Module GPS /Glonoss WiFi LTE LTE LTE GSM GSM Bluetooth Figure 1. Example of mobile phone system [6]. Frequency bands for wireless communications. To understand above phenomena and find root causes, a system-level EMI analysis is required. However, it is difficult since many chips, components, cables, and connectors are densely packed as well as the generated EM noises are complicatedly related to the each other. Thus, to classify EM noise clearly and find solution, a component-level EMI evaluation is strongly required. So far, however, most EMI evaluation and verification rely on measurement which often causes additional cost and time to fix. To overcome these issues, component-level EMI analysis methodologies have been investigated [7-1]. Although EMI characteristics were defined and simulation methodology was provided in

5 Voltage Voltage previous investigations, there are still requirements for correlation with measurement for wideband frequency range. In addition, it is also required for chip and package-level EMI solution for advanced stackable packaging technology such as package-on-package (PoP) and through-silicon via. In this paper, we present a near-field scan (NFS)-based EMI simulation methodology for PoP-type mobile DRAM devices. Especially, we provide chip and package-level EMI solution for wideband analysis methodology. We present the detail strategies to increase accuracy of EMI analysis and correlation with measurement results. EMI Noise in Memory Chip On-Chip EMI Radiation (Direct) Off-Chip EMI Radiation (Power Path) Package Chip DRAM Cell VDD Sig2 Sig1 VSS Off-Chip EMI Radiation (Signal Path) Signal Path Power Path Time Time Figure 2. EMI noise sources in a memory chip. Fig. 2 shows the predicted EMI noise sources in a memory chip. It can be divided into two categories: on- and off-chip EMI radiations. On-chip radiation occurs owing to the direct emission from chip surface. It is originated an on-chip interconnection because it could act as an antenna. However, its emission level may relatively lower than the offchip radiation since on-chip metal wire length is shorter than off-chip conductors [11]. Therefore, in our investigation, we mainly concentrate on an off-chip radiation, and it is divided by two factors such as signal and power paths. Since memory uses parallel interface, EMI radiation is mainly occurred by a signal path when data are switched zero to one and vice versa. However, radiation due to power path cannot be ignored because a simultaneous switching noise (SSN) by data transition may also significant. Thus, EMI radiation by both signal and power paths should be included in EMI simulation. The key factors for signal and power path will be presented following sections.

6 Near-Field EMI Simulation Methodology Step1: EMI Source Extraction Fast Fourier Transform Time Domain Freq. Domain Step2: EM Modeling & Full-Wave Simulation Wirebond BGA Current Source Hot Spot Step3: Embedding of Measurement Effects H-Field Probe/Cable Effects Noise Floor of Equipment Moving Average Figure 3. Proposed near-field EMI simulation flow. Fig. 3 shows the proposed NFS-based EMI simulation flow. It consists of three steps as follows: an EMI source extraction, a modeling/full-wave simulation, and an embedding process of measurement effects. The detail strategies to increase accuracy are introduced follow sections. Stage I: EMI Source Extraction Input Stimulus Power Distributed Network (PDN) VDD AP Model Memory Package AP Package Power Distributed Network (PDN) VSS Figure 4. Simplified block diagram for EMI source extraction.

7 Voltage [V] toggle toggle toggle 416bit 32bit 32bit 32bit. 12bit 16bit 4bit Figure 5. The used input stimulus for EMI source extraction. Fig. 4 shows the simplified block diagram for EMI source extraction. It is composed of a DRAM buffer, a power distributed network (PDN), a memory/ap package models, and a capacitive loading. An input stimulus for this simulation is extracted by the direct package probing as shown in Fig. 5. The overall period of input stimulus is about 832 bits which is composed of a non-toggle ( ) and a toggle (11 ) patterns operated at 16 Mb/s. SPICE Model IBIS Model IN PMOS NMOS ESD Diodes Cap. OUT IN Pull Up Pull Down I(V) I(V) Cap. OUT IBIS SPICE Time [ns] Figure 6. Comparison of models and transient simulation results. As first, we compare two buffer models. One is SPICE model and the other one is Buffer Information Specification (IBIS) model. As shown in Fig. 6, the SPICE model is composed of transistors, diodes, and passive components. Meanwhile, the IBIS model consists of tables to describe rise/fall transitions. Fig. 6 shows the transient simulation results in time-domain. Although, the slope at rising/falling transition is nearly the same for both cases, signal distortions such as overshoot and ring-back resulted from impedance mismatch can be accurately modeled when SPICE model is used. Although IBIS model is convenient to use as well as it reduces simulation time, the SPICE model should be used for extracting an EMI source to increase its accuracy. Fig. 7 shows the extracted EMI noise sources at signal and power, respectively. After circuit simulation,

8 Figure 7. Extracted EMI noise source at signal and power path in frequency domain. time-domain waveform is converted to the frequency-domain results using the Hanningwindowed Fast Fourier Transform (FFT) [12] with a resolution bandwidth of less than 1 MHz. As shown in Fig. 7, it can be observed that the spectrums have various frequency components at the fundamental (8 MHz) and its harmonics (16, 24 MHz). From these results, we observe that odd harmonics (8, 24 MHz) are more dominant in signal source, and even harmonic (16 MHz) is more dominant in power source. R-Network RC-Network Power Plane Power Plane Ground Plane Ground Plane Figure 8. Power distribution networks based on R-network and RC-network. We compare two PDN models based on R- and RC-network as shown in Fig. 8, respectively. In R-network, the R value is calculated by using the sheet resistance of onchip metal. The decoupling capacitance value of buffer is added in SPICE model. For RC-network, resistance and capacitance are entirely extracted by the layout. Thus, it includes parasitic components as well as decoupling capacitance. In particular, the exact position of buffers can be expressed in the RC-network. Thus, accurate power effect

9 DQ DQ2 DQ4 DQ6 DQ8 DQ1 DQ12 DQ14 DQ DQ2 DQ4 DQ6 DQ8 DQ1 DQ12 DQ14 DQ DQ2 DQ4 DQ6 DQ8 DQ1 DQ12 DQ14 Magnitude [db] Magnitude [db] Magnitude [db] PDN (R-Network) PDN (RC-Network) Memory Output Capacitive Loading MHz 16MHz 24MHz -5-5 R-network -55 RC-network R-network RC-network ~13dB R-network RC-network Figure 9. Comparison of simulation result at time domain and frequency domain. can observe using a PDN model based on RC-network. Fig. 9 shows time-domain simulation results monitored at the memory output and the capacitive loading. As shown in these figures, for both cases, there is no significant difference, and they have nearly the same eye opening. Fig. 9 shows frequency-domain simulation results for the each data line at 8, 16, and 24 MHz. As mentioned earlier, the magnitude at odd harmonics (8, 24 MHz) are nearly the same since these harmonics are mainly affected by signal. However, at even harmonic (16 MHz), there is significant gap of about 13 db by changing PDN from R-network to RC-network. In other words, in order to describe power noise accurately, the PDN model based on RC-network should be used for EMI source extraction. Stage II: Full-Wave EM Simulation For full-wave EM simulation, structural modeling of the package is done such as stackup, wirebond, solderball, and etc. Such material properties as relative dielectric constant, loss tangent, and conductivity are set to the values at 1 GHz. For wideband analysis, material properties are extrapolated by the Djordjevic-Sarkar model [13]. The extracted EMI source from circuit simulation are attached by a current source, and then, full-wave EM simulation is done using an EM solver. The H-field emission is observed at above 1 mm from the memory. The simulated frequency range is from 7 MHz to 25 MHz.

10 Setting & Acquisitions H-Field [dba/m] H-Field [A/m] H-Field [A/m] H-Field [dba/m] H-Field [A/m] H-Field [A/m] -2-4 Signal only Power only Signal+Power Figure 1. Full-wave EM simulation results when signal and noise source are applied individually and simultaneously. Fig. 1 shows the EM simulation results when signal and power source are individually attached. Similar to the FFT result of EMI source in Fig. 7, EM emission by signal source is larger than for odd harmonic region (8, 24 MHz). Otherwise, EM emission by power source is more dominant for even harmonic region (16 MHz). Fig. 1 shows the EM simulation results when signal and power source are applied simultaneously. It takes maximum value of both simulation results in Fig. 1. From these results, we observe that signal and power EMI noise source should be included simultaneously for wideband EMI analysis. Stage III: Embedding Effects of Probe/Amplifier/Cables Electrical Cable External Amplifier Spectrum Analyzer Current Trace H-Field Memory H x,h y Probe (R=2mm) 1mm Desktop Computer Probe XYZ Positioning Figure 11. Near-field scan measurement setup. Fig. 11 shows experiment setup for NFS measurement. The device under test (DUT) is a mobile DRAM which is surrounded by absorbing materials to minimize undesired reflection. H-field was captured by H x, H y probes having a diameter of 2 mm located at above 1 mm from a DUT. The captured H-field was amplified by an external amplifier having about 41 db to meet input sensitivity of the spectrum analyzer with 5-Ω load.

11 H-Field [dbm] H-Field [A/m] H-Field [A/m] Figure 12. Measured probe factor and noise floor. Unlike the simulation setup, the used probe has frequency-dependent characteristics as well as electrical cable loss and external amplifier gain also have frequency-dependent values. Thus, to minimize difference between simulation and measurement results, their effects should be embedded in simulation results. Fig. 12 shows the measured frequency characteristic of a field probe, an external amplifier, and an electrical cable. By adopting this factor and converting to power with 5-Ω reference, simulation results have frequency dependent characteristics as well as the unit of simulation and measurement can be matched to dbm. In addition, in order to include noise effects generated by test environment, we measure noise floor when DUT was turned off. Fig. 12 shows the measured noise floor using the spectrum analyzer. The measured noise floor is added to the simulation results. Correlation with NFS Measurement Results Measurement Simulation Figure 13. Comparison of simulation and measurement spectrums.

12 To evaluate our analysis methodology, simulation result is compared with measurement result with frequency range from 7 MHz to 2.5 GHz as shown in Fig. 13. The gray line shows the measured H-field, and the blue line shows the simulation results when mobile DRAM operated at 16 Mbps. As shown in Fig. 13, both curves have a good agreement for wideband frequency range with difference less than 3 db. Summary We develop a NFS-based EMI analysis methodology for mobile DRAM applications. We firstly present an EMI analysis methodology including a chip/package-level solution as well as the detail analysis strategies for wideband EMI characteristics. The simulation results have correlation with measurement results less than 3 db up to 2.5 GHz. With this methodology, we evaluate EMI variation and dependency by changing design parameters. We believe that our simulation methodology has a great potential to evaluate EMI performance and detect risk factors in early design stage. Consequently, it is expected that our methodology could be applied to various applications. References [1] M. Gonser, et al., Simulation of Automotive EMC Emission Test Procedures Based on Cable Bundle Measurements, Int. IEEE Microwave Theory and Techniques, pp. 1-3, 212. [2] T. Sudo, et al., Electromagnetic Interference (EMI) of System-on-Package (SOP), IEEE Trans. on Advanced Packaging, vol. 27, no. 2, pp , May 24. [3] B. Vrignon, et al., Characterization and Modeling of Parasitic Emission in Deep Submicron CMOS, IEEE Trans. on Electromagnetic Compatibility, vol. 47, no. 2, pp , 25. [4] P. J. Doriol, et al., EMC-aware Design on a Microcontroller for Automotive Applications, Conf. on Design, Automation and Test, pp , 29. [5] M. Ramdani, et al., The Electromagnetic Compatibility of Integrated Circuits Past, Present, and Future, IEEE Trans. on Electromagnetic Compatibility, vol. 51, no. 1, pp. 78-1, 29. [6] About Chipworks: Inside the Samsung Galaxy S3. [7] T. Steinecke, et al., EMI Modeling and Simulation in the IC Design Process, Int. IEEE Electromagnetic Compatibility, pp , 26. [8] E. Diaz-Alvarez and J. P. Krusius, Package and Chip-Level EMI/EMC Structure Design, Modeling and Simulation, Electronic Components and Technology Conference, pp , 212. [9] S. K. Kwak, et al., Modeling and Co-Simulation of interconnects for On-Chip and Off-Chip EMI Prediction, Asia-Pacific International Symp. on Electromagnetic Compatibility, pp , 212. [1] R. Murugan, et al., System-level SoC Near-field (NF) Emissions: Simulation to Measurement Correlation, Electronic Components and Technology Conference, pp , 212.

13 [11] S. Hayashi, et al., EMI-Noise Analysis Under ASIC Design Environment, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 11, pp , 2. [12] W. Pan, et al., Power Harmonics Measurement Based on Windows and Interpolated FFT (I) Study of Windows, Trans. of China Electrotechnical Society, [13] R. M. Djordjevic, et al., Wideband Frequency Domain Characterization of FR-4 and Time-Domain Causality, Int. IEEE Electromagnetic Compatibility, pp , 21.