Efficiency of Embedded On-Chip EMI Protections to Continuous Harmonic and Fast Transient Pulses with respect to Substrate Injection

Transcription

1 Efficiency of Embedded On-Chip EMI Protections to Continuous Harmonic and Fast Transient Pulses with respect to Substrate Injection Ali Alaeldine, Nicolas Lacrampe, Jean-Luc Levant, Richard Perdriau, Mohamed Ramdani, Fabrice Caignet, Marise Bafleur, Etienne Sicard and M hamed Drissi ESEO - 4, rue Merlet-de-la-Boulaye - BP Angers Cedex 01 - France ( ali.alaeldine@eseo.fr) IETR - INSA de Rennes - 20, avenue des Buttes de Coësmes Rennes Cedex - France LAAS-CNRS - 7, avenue du Colonel Roche Toulouse Cedex 04 - France ATMEL Nantes - La Chantrerie - Route de Gachet Nantes - France LESIA - INSA de Toulouse - 135, avenue de Rangueil Toulouse Cedex 04 - France Abstract This paper presents a comparative study of the efficiency of several embedded EMI protections for integrated circuits (ICs) with respect to direct power injection (DPI) and very fast transmission-line pulsing (VF-TLP) into the substrate of the IC. This study involves three functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate, meshed power supply network) which were initially designed for low-emission design guidelines. Through extensive measurements, a classification between these strategies is established for both injection methods, leading to the introduction of design guidelines for the minimization of conducted susceptibility to substrate injection. I. INTRODUCTION Within the recent years, many digital and analog integrated circuits (ICs) have become more and more susceptible, due to an increased number of interfaces, higher data rates, decreased node capacitance, and a steady reduction in power supply voltage and, consequently, noise margin. In particular, substrate noise generated in an IC by either internal logic or external sources can dramatically disturb the operation of other analog or digital blocks [1] [2]. Therefore, the characterization of their behavior is a topical demand.for that purpose, several measurement methods have been developed. Some of them are related to the electromagnetic compatibility (EMC) field, including direct power injection (DPI) [3], the others,including very fast transmission-line pulsing (VF-TLP [4], to the electrostatic discharge (ESD) field. The use of both DPI and VF- TLP methods on the same IC with similar injection systems makes it possible to characterize the behavior of integrated circuits towards many kinds of perturbations. Many embedded protection strategies for ICs have been designed, but either for EMI or ESD protection. In this paper, a comparison between the efficiency of some of these strategies with respect to substrate injection, using both measurement methods, is introduced. This comparison was achieved by the means of an IC including several logic blocks, which are identical from a functional point of view and are located on the same die, but differ only by their protection strategies. This paper is organized as follows. First of all, the building blocks of the test chip used in this study are presented. In Sect.III, both measurement methods (DPI and VF-TLP) are introduced, with an emphasis on their setups. Sect. IV deals with measurement results and the comparison between the immunities of the basic cores involved in this study, for each injection technique. Finally, Sect. V points out some design guidelines helping to minimize IC susceptibility to substrate injection. II. TEST CHIP AND EXPERIMENTAL SET-UP The integrated circuit (CESAME) used in this study was designed and fabricated by ST-Microelectronics in 0.18 µm CMOS technology, 1.8 V supply voltage and was initially intended for the validation of low-emission design techniques. It consists of six logic cores (Fig.1). Fig. 1. CESAME test chip and the three cores under test (NORM, ISO and RC) in red frames All these cores have an identical functional structure based on D flip-flops, a clock tree and standard gates, and are intended to reflect the activity of a typical logic core [5]. Each core includes 240 identical synchronous base cells, and each base cell consists of 400 transistors (5 D-flip-flops, 25 NAND gates and 4 buffers). The current consumption of each core depends on the switching activity, which is user-programmable. In this study, maximum switching activity (100 %) is used.

2 These cores only differ by their EMI protection strategies (Fig. 1) : NOR core : bare core without any protection NORM core : with 1.7 Ω series resistors on both supply rails ISO and ISV cores : with 1.7 Ω series resistors and a substrate insulation layer RC core : with 1.7 Ω series resistors and an on-chip decoupling capacitor GRID core : with 1.7 Ω series resistors and a meshed power supply network In this paper, three cores out of the six are studied : a) NORM core: The only EMI protection strategy used in the NORM core consists of two small 1.7 Ω series resistors, one on each power supply rail. These resistors, along with the metal and MOS capacitances of the logic core, build up a RC filter, with a high cutoff frequency (about 200 MHz). b) ISO core: Another protection strategy is used for the ISO core. This core is embedded in its own local substrate, isolated from the rest of the chip thanks to a triple-well technique (Fig.2). Fig. 3. Comparison between NORM and RC core architectures Fig. 4. DPI method set-up Fig. 2. Comparison between NORM and ISO core architectures c) RC core: In this core, an additional 1-nF integrated decoupling capacitor is included between both supply rails (Fig.3). This distributed on-chip capacitor is made from several poly1/poly2 capacitors, and increases the area of the RC core by 40 % compared with the NORM core. By lowering the cutoff frequency of the RC filter (about 40 MHz), this technique allows reducing the power distribution noise arising from multiple drivers switching simultaneously [6]. III. INJECTION METHODS In this paper, two different injection methods are successively used in order to characterize the immunity of the CESAME IC to either EMI or ESD disturbances. A. Direct power injection (DPI) method To characterize the behavior of the test chip under electromagnetic aggressions, several measurement methods are currently under standardization process under the supervision of the International Electrotechnical Commission (IEC), one of which is Direct Power Injection (DPI) [3]. An example of DPI setup is displayed in Fig. 4. Continuous sine-wave RF power (from 10 MHz to 1 GHz) is fed into an amplifier and then injected into a pin of the IC under test (which could be either a power pin or a signal input pin) through a capacitor blocking the DC voltage coming from the power supply (hence the name of the test). A directional coupler allows the measurement of incident and reflected powers by the means of two power meters. The IC under test works under normal operating conditions, and the data output of the circuit under test is connected to an oscilloscope (adapted to 1 MΩ) through a 1 MΩ passive probe, which makes possible to observe a malfunction of the circuit during the experiment. The measurements described in this article are performed while injecting power into the substrate of the test chip (via the V ss power pin). The transmitted power P Trans to the whole device under test (DUT) can then be expressed from the measured incident power P Inc : P Trans = (1 S 11 2 ) P Inc (1) when S 11 is the reflection factor and P Inc the incident power injected into the system under test.

3 By replacing the reflection factor by its expression, Eq. 2 is obtained : ( P Trans = 1 Z DUT Z 0 2) P Inc (2) Z DUT + Z 0 when Z DUT is the impedance of the device under test and Z 0 the characteristic impedance of the sine-wave generator (50 Ω). By separating the real and imaginary parts of Z DUT, the exact expression of the transmitted power can be obtained : P Trans = 4 Z 0 Re(Z DUT ) Z DUT + Z 0 2 P Inc (3) The expression in Eq. 3 is well suited to the calculation of P Trans from measurements, owing to the use of power meters in DPI experiments. B. Very fast transmission line pulsing (VF-TLP) method An electrostatic discharge is the sudden and momentary electric current that flows when an excess of electric charge stored on an electrically insulated object finds a path to an object at a different electrical potential (such as ground), which may cause damage to electronic equipment. Many ESD tests allow the characterization of the immunity of integrated circuits. Notably, the IEC standard defines immunity requirements for ESD which can be coupled into equipment in conducted or radiated mode [7]. Electrostatic discharge phenomena are represented by several models depending on the kind of electrostatic source : the Human Body Model (HBM) simulating the discharge of a human being onto an electronic device : unique pulse with 2 to 10 ns rise time, 130 to 170 ns time delay, and 0.25 to 0.30 A peak current for a 400 V voltage. the Machine Model (MM) simulating the discharge of metallic equipment onto a grounded electronic device : damped 12 MHz sine-wave signal with 6 to 8 ns rise time and 4.6 to 7.0 A peak current for a 400 V voltage. the Charged Device Model (CDM) representing the selfdischarge of a charged integrated circuit through its package : unique pulse with 300 to 500 ps rise time, 0.5 to 1.5 ns time delay, and 1.7 to 2.5 A peak current for a 400 V voltage. In particular, the CDM is well-suited to IC immunity testing due to the frequent advent of such events in product assembly lines. However, CDM tests only provide "pass-fail" results which do not output any information about the behavior of the circuit under test. Therefore, the VF-TLP method [4] was designed as a characterization tool of the dynamic behavior of the circuit under test under a CDM stress. It consists in injecting very fast square current pulses (with a rise time lower than 500 ps and a width between 1.25 ns and 10 ns) through a transmission line, by the means of a high-power time-domain reflectometer (TDR), and extrapolating voltages and currents related to the device under test through the measurement of incident and reflected pulses. The frequency spectrum of VF- TLP pulses is richer than the one of other ESD tests and belongs to the Ultra Wide Band (UWB) category. It includes the 100 MHz - 1 GHz band which seems to be critical for ICs [8] [9]. In this study, the VF-TLP signal is fed into the V ss pad of the active circuit under test by an injection probe and a 1 nf injection capacitor, in order to mimic the DPI measurement setup as closely as possible. Fig. 5 illustrates the VF-TLP measurement setup with the injection system and the device under test. It includes a 4-channel digital oscilloscope with selectable input impedance. Fig. 5. Simple description of the VF-TLP method The 3-way TDR box of the VF-TLP system makes it possible to visualize the incident and reflected pulses injected into the device under test. The input signal of the TDR box is viewed on a 50 Ω input of the oscilloscope through a coaxial cable; the main output signal of the TDR box is connected to the injection probe, while the third port of the box is connected to another 50 Ω input of the oscilloscope, making it possible to observe incident and reflected pulses. Finally, the data output of the circuit under test is connected to the third input of the oscilloscope in the same manner as for the DPI test. A. Immunity criterion IV. MEASUREMENT Every susceptibility study must define a criterion that the integrated circuit should meet to be considered immune to EMI for a given aggression. In this experiment, an ubiquitous criterion, described in the Bulk Current Injection (BCI) standard proposal [10], is used : a failure in the IC is characterized by the ripple of the output signal reaching 20 % of one given steady logic voltage level, or by the jitter of this output signal reaching 10 % of the period. B. DPI measurements The DPI experiment consists in injecting continuous power into the substrate pin of the NORM core. Since this core is implemented in the global substrate of the integrated circuit, the injected power is dissipated in the whole substrate. This substrate noise has an influence, not only on the NORM core itself, but also on the other cores of the circuit.

4 DPI measurements were performed from 10 MHz to 1 GHz in 10 MHz frequency steps. For each frequency, the injected power at which the integrated circuit becomes susceptible is recorded. The whole frequency plot is represented in Fig. 6 for each core. path. The circuit becomes susceptible when the peak amplitude of the resulting pulse reaches the criterion, that is 0.4 V. These results are illustrated in Fig NORM ISO RC 35 Injected power (dbm) DPI into the substrate of CESAME test chip: Output signal susceptibility Frequency (MHz) Fig. 7. Comparison between the immunities of the NORM, ISO and RC cores using the VF-TLP injection method Fig. 6. Comparison between the immunities of the NORM, ISO and RC cores using the DPI method Different protection strategies were initially used to decrease the parasitic emission of these cores, but can be useful to increase their immunity as well. The deep N insulation layer between the global substrate and the local substrate of the ISO core (Fig. 2) lowers the coupling capacitance between both substrates. Hence, the susceptibility of the ISO core is generally lower than the one of the NORM core, particularly from 10 MHz to 210 MHz. However, it can be noted that the ISO core is less immune than the NORM core between 400 and 500 MHz ; this may be due to an antiresonance of the coupling capacitor with the passive elements of the power supply network. The RC core (Fig. 3) includes an on-chip decoupling capacitor between the V dd and V ss power supply rails. This on-chip decoupling capacitor enhances the immunity of the RC core in comparison with the others, except between 500 MHz and 650 MHz where the RC core is less immune than the ISO core ; likewise, an antiresonance of the capacitor with the power supply network may explain this behavior. In high frequency (above 650 MHz), the ISO and RC cores have similar susceptibility levels except at 780 MHz. C. VF-TLP measurements As far as VF-TLP is concerned, the same criterion is used, but the measurements performed are of course different. Variable-amplitude pulses are injected into the substrate of the NORM core, with a 180 ps rise time and a 5 ns width. This pulse flows towards the output signal through the coupling It can be seen that the NORM core begins to be susceptible at 20 V, while 30 V are required to disturb the operation of the ISO core. The RC core is less susceptible : logic errors appear at the output of the RC core only when the amplitude of the injection pulse reaches 40 V. Finally, this shows that the NORM core is the least immune, followed by the ISO core and finally the RC core. To confirm these results, another VF-TLP test was then performed : a series of 100 pulses with a 70 V amplitude (hence, higher than the susceptibility levels of all cores) were injected into the substrate, then, the logic errors induced in the output of each core by these pulses were visualized and counted. Tab. I shows the percentage of logic errors for each core. It can be noticed that this test confirms the classification Injected pulse Core Amplitude Width % of logic errors NORM 70 V 5 ns 9 % ISO 70 V 5 ns 6 % RC 70 V 5 ns 5 % TABLE I LOGIC ERRORS TRIGGERED ON EACH CORE UNDER TEST already established for the three cores. The logic behavior of the output signals of the three cores will then be investigated accurately in future studies for power and pulse injection into the substrate and the power supply rails of these logic cores. V. DISCUSSION An interesting result of the aforementioned measurements consists of the susceptibility classification of the three cores,

5 which is the same for both aggression techniques. This classification demonstrates that the integrated decoupling capacitor seems to be the most efficient protection method to increase the immunity of logic cores, while it is the best solution to lower emission as well [5]. Nonetheless, the implementation of an insulation layer (ISO core), while not increasing the size of the die significantly, limits substrate coupling and leads to clean field cancellation on supply pairs. Various authors [11] have investigated substrate noise influence on circuit performance as a function of the number of substrate contacts, without significant differences. They advise to increase the resistivity of the global substrate in order to decrease the substrate noise by the addition of an external resistance, or increase the resistivity of a given region of the substrate. This last solution is costly and difficult, however, the existence of this multiple resistivity favors the implementation of many mixed-signal devices on the same substrate. As far as the RC protection method is concerned, most multi-chip modules (MCMs) rely on surface mount capacitors for decoupling [12] [13]. However, surface mount devices are bulky and have large parasitics which reduce their efficiency. Therefore, the interest of embedded capacitors for low emission has already been addressed in [6]. This study confirms that the low emission design rules edicted in these previous papers are valid for high immunity as well : whenever possible, the integrated decoupling capacitor technique should be adopted. VI. CONCLUSION This work focuses on the susceptibility levels of several identical logic cores with different protection methods initially designed for low emission. Both tests applied in this paper (DPI and VF-TLP) demonstrate that the integrated decoupling capacitor is the best solution to increase the immunity level while decreasing parasitic emission (up to 15 dbm in DPI in low frequency, 20 V in VF-TLP). However, this technique is expensive due to the significant increase in die area ; therefore, many studies are focused on the development of new cost-effective integrated capacitors with small area and low parasitics. In case this solution can not be implemented, this paper shows that the implementation of a triple-well insulation layer is a valuable improvement, yet less efficient, to the immunity of an integrated circuit (5 to 10 dbm in DPI, 10 V in VF-TLP). In the future, near-field injection will be applied to the same cores in order to extend this study to the case of radiated immunity, and another test chip will be specifically designed and fabricated, with several analog and digital integrated blocks and new shielding methods, in order to study the efficiency of these techniques on external and internal immunities. VII. ACKNOWLEDGEMENTS The authors would like to thank Bertrand Vrignon (Freescale, Toulouse), Sonia Ben Dhia (LESIA-INSA Toulouse) and Nicolas Nolhier (LAAS-CNRS, Toulouse) for their valuable discussions and support, as well as Alexandre Boyer (LESIA-INSA Toulouse) and Olivier Maurice (EADS- CCR, Suresnes) for their help. REFERENCES [1] R. Rossi, G. Torelli, and V. Liberali. Model and verification of triple-well shielding on substrate noise in mixed-signal CMOS ICs. In ESSDERC, Portugal, September [2] J.L. Levant, M. Ramdani, R. Perdriau, and M. Drissi. Solving internal immunity issues in ICs. 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