An analog to digital converter ICIM-CI model based on design

Transcription

1 An analog to digital converter ICIM-CI model based on design Jean-Baptiste Gros 1, Geneviève Duchamp 1, Alain Meresse, Jean-Luc Levant 2, Christian Marot 3 1 Université Bordeaux1, Laboratoire IMS 2 ATMEL, Route de Gachet, NANTES, France 3 EADS, 18 rue Marius Terce BP 13050, TOULOUSE France jean-baptiste.gros@ims-bordeaux.fr

2 Presentation Outlines Introduction Analog to Digital Converter (ADC) Presentation Immunity study ADC ICIM-CI model ICIM-CI methodology Immunity control block Immunity results Conclusion EMC Compo

3 Introduction Integrated Circuit as microcontrollers Proximity between analog and digital parts Working frequency rising Supply voltage falling Decrease of margin voltage Risk of EM interference Analog function failure Critical for security equipment EMC Compo

4 Introduction Integrated Circuits Electromagnetic Compatibility (EMC) improvement To limit disturbance emission To avoid of functional failures EMC standards for Integrated Circuits Emissivity : ICEM-CE [1] (November 2008) Immunity : ICIM-CI [2] (New proposal) Industrial partner ATMEL Nantes [1] IEC Integrated Circuit Emission Model Conducted Emission [2] Integrated Circuit Immunity Model Conducted Injection EMC Compo

5 Presentation Outlines Introduction Analog to Digital Converter (ADC) Presentation Immunity study ADC ICIM-CI model ICIM-CI methodology Immunity control block Immunity results Conclusion EMC Compo

6 Analog to Digital Converter (ADC) Presentation Specifications: ADC ATMEL SAR register Accuracy: 10 bits Dedicated supply Featuring: Successive Approximation Register (SAR) Digital to Analog Converter (DAC) Comparator Conversion: Input Voltage Vin Approximation Voltage Vdac 10 steps 10 bits Natural error : ±1 LSB Voltage (V) 4,0 3,0 2,0 1,0 Vrefp =5V Vrefn Vin SAR 10 Vdac DAC Vref Comparator ADC functional diagram 10 digits Binary result 0,0 0,0E+00 2,0E-06 4,0E-06 6,0E-06 8,0E-06 1,0E-05 Time (s) EMC Compo

7 Analog to Digital Converter (ADC) Immunity study Failure mechanism Sensitive circuit : Comparator -Analog Inputs - Low voltage margins - Comparison errors Comparison error example - Transient simulation - Positive DAC reference disturbed - Vref over Vdac - Last step error (Vdac is increased) Voltage (V) 2,510 2,505 2,500 2,495 11,9 12,1 12,3 12,5 12,7 12,9 13,1 Time (µs) EMC Compo

8 Analog to Digital Converter (ADC) Immunity study Immunity parameters How the disturbance is propagated to the sensitive nodes? - Transfer functions estimation - From disturbance sources to comparator inputs 2,510 What is the margin voltage between comparator inputs? Voltage (V) 2,505 2,500 Vmargin Vmargin - Vmargin - Transient analysis of the conversion stage 2,495 11,9 12,1 12,3 12,5 12,7 12,9 13,1 Time (µs) EMC Compo

9 Presentation Outlines Introduction Analog to Digital Converter (ADC) Presentation Immunity study ADC ICIM-CI model ICIM-CI methodology Immunity control block Immunity results Conclusion EMC Compo

10 ADC ICIM-CI model ICIM-CI methodology ICIM-CI Model ICIM-CI standard methodology Power Distribution Network (PDN) Model - Package Model (pins, bonding, pads) - Coupling path model Immunity Behavioral Component (IB) -Functional Model - Immunity Control Block PDN Component Coupling Path Model Residual disturbances Package & power network Model I/O Pins RF Disturbance sources Functional Model Immunity Control Block Immunity Criterion IB Component Sensitive parameters Immunity results EMC Compo

11 ADC ICIM-CI model Immunity control block Comparator input voltages are estimated Transfer function DC voltages Comparison error if the two comparator are equal V MARGIN [ H sin( ωt ) H sin( ω )] = A( ω ) M P t0 + 0 φ The minimum disturbance amplitude could be calculated A( ω) = H 2 M 2H V M MARGIN H P cos( Φ) + H 2 P ( ) ω Three immunity behaviors: - Vmargin - Transfer function gain - Relative phase between the inputs EMC Compo

12 Presentation Outlines Introduction Analog to Digital Converter (ADC) Presentation Immunity study ADC ICIM-CI model ICIM-CI methodology Immunity control block Immunity results Conclusion EMC Compo

13 Immunity results ADC ICIM-CI Model Functional Model pure Complete transient analysis Estimation of each step DC voltage Coupling path model Estimation of transfer functions Hm, Hp Immunity controlled block Immunity curves calculation from the immunity parameters EMC Compo

14 Immunity results Whole conversion stage analysis ADC ICIM-CI model Immunity of each conversion step (10 curves) Vin=1.253V AREF=5V Critical step pointed out (2, 9 and 10) Only 10mV to loose 2 LSB 30mV to loose 4 LSB Minimum Disturbance Voltage (V) ,1 0,01 Step 3 to 9 Step 10: 1.253V Step 1 Step 2: 1.250V 0,001 1,0E+04 1,0E+05 1,0E+06 1,0E+07 1,0E+08 1,0E+09 Frenquency (Hz) Good immunity for high frequencies Decrease of immunity if Vmargin is low Critical step, even for the first steps (N 2) EMC Compo

15 Immunity results Critical step analysis for different Vin Minimum Disturbance Voltage (V) Immunity behavior Last conversion step error Vdac depends of Vin ,1 0,01 DAC output depends of Vin Middle output : Vin=2.5V Local fall of the immunity Good immunity for low frequency Top or bottom output: Vin=0 Vin=5V Bad immunity for low frequencies Good for HF 0,001 1,0E+04 1,0E+05 1,0E+06 1,0E+07 1,0E+08 1,0E+09 1,0E+10 Frequency (Hz) EMC Compo

16 Presentation Outlines Introduction Analog to Digital Converter (ADC) Presentation Immunity study ADC ICIM-CI model ICIM-CI methodology Immunity control block Immunity results Conclusion EMC Compo

17 Conclusion Internal ICIM-CI model of the ADC is working Good immunity estimation Critical step are pointed out Indirectly Immunity control block (Calculation) Low calculation time Next steps Package model Allowing chip external disturbing Analysis with ICEM-CE model of the core Immunity degradation with the internal core activity Integration of ICIM methodology in the ATMEL design flow EMC Compo

18 Thank you for your attention