ROBUSPIC Workshop. ESSDERC 06 Montreux, Switzerland Friday 22 nd of September. ESSDERC 06, Montreux ROBUSPIC Workshop A.

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1 ROBUSPIC Workshop ESSDERC 06 Montreux, Switzerland Friday 22 nd of September ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 1

2 Vladimir Ceperic, Adrijan Baric - University of Zagreb, Croatia Renaud Gillon - AMI Semiconductors, Belgium ESSDERC 06 Montreux, Switzerland Friday 22 nd of September ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 2

3 Contents 1 Introduction 2 PCB modelling 3 SMD components 4 Chip packaging 5 On-chip circuit 6 Results 7 Conclusion ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 3

4 Introduction We would like to achieve: Deal with EMC issues in a simple way Use conducted EMC standards Achieve good agreement between simulations and measurements!!! ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 4

5 Introduction Conducted EMC standards: IEC : Integrated circuits Measurements of electromagnetic emissions, 150 khz to 1 GHz Part 4: Measurements of conducted emissions 1 Ohm/150 Ohm direct coupling method IEC : Integrated circuits - Measurement of radiated immunity Part 4: Direct RF power injection method ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 5

6 Introduction IEC : conducted electromagnetic emissions (to check EMISSIONS) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 6

7 Introduction IEC : direct RF power injection method (to check IMMUNITY) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 7

8 Introduction To achieve good agreement between simulations and measurements we deal with the following models: PCB tracks (including connectors) SMD components on a PCB Chip packaging (lead-frame, bond-wires,...) Chip, i.e. circuit itself (including parasitics) e.g. ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 8

9 Introduction ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 9

10 Contents 1 Introduction 2 PCB modelling 3 SMD components 4 Chip packaging 5 On-chip circuit 6 Results 7 Conclusion ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 10

11 PCB modelling Various approaches: 1. Simulate by using 3D EM field solvers (or 2D and a half EM field solvers) hmmmm?!?!?! 2. Build PCB, measure and model hmmmm?!?!?! ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 11

12 PCB modelling Ansoft Q3D Extractor: it generates a Spectre compatible netlist next slide ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 12

13 PCB modelling EM field solver Not a bad solution: It just: takes substantial time does not necessarily get to the solution does not necessarily produce accurate result Problems: vias are generally a huge problem because of the number of nodes that they generate during discretization of the simulated space (PCB trace is a relatively small issue) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 13

14 PCB modelling Build measure model This approach seems to be simpler It may also include the influence of SMD components (something that is simply hard to estimate exclusively from simulations!!!) we ll deal with this issue later (in Section 3) PCB can be built, measured and modelled concurrently while designing a chip/circuit (it is not necessary to wait for the chip to be processed!!!) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 14

15 PCB modelling Modelling of a short and medium line on a PCB Various lines have been produced and measured to model SMD components ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 15

16 PCB modelling Short line (15 mm between SMA connectors) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 16

17 PCB modelling Medium line (30 mm between SMA connectors) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 17

18 PCB modelling Long line (147 mm between SMA connectors) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 18

19 PCB modelling The model parameters are obtained by simultaneous optimization of model parameters for all three lines (short, medium, long) Model parameters of the mtline (Spectre model): r = Ohm/m l = 2.67 uh/m c = pf/m g = 8.83e-14 S/m rskin = 3.75e-7 Ohm/(m*sqrt(f)) gdloss = 2.17e-12 S/(m*Hz) (rskin and gdloss model skin effect resistance and dielectric loss conductance as a function of frequency) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 19

20 Contents 1 Introduction 2 PCB modelling 3 SMD components 4 Chip packaging 5 On-chip circuit 6 Results 7 Conclusion ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 20

21 SMD components SMD components are modelled based on the measurements of various structures/pcbs and by assuming (or not) various simplifications ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 21

22 SMD components Approach 1 includes: Modelling of PCB traces by Ansoft Q3D (3D/2D quasi-static EM field solver that produces a Spectre sub-circuit netlist) Measurement of the PCB Modelling through the optimization procedure in order to extract the equivalent circuit elements of the SMD components on the PCB (this is an obviously slightly confusing approach) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 22

23 SMD components Approach 1: - PCB traces are modelled by an EM field solver ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 23

24 SMD components Approach 1: - various SMD components are modelled by using the following equivalent circuits ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 24

25 SMD components Approach 1 example: - the network consisting of two resistors used in conducted EMC tests is shown below - Two measurements are performed: the first for P2 left OPEN, and the second for P2 shorted to the ground ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 25

26 SMD components Approach 1 example: - based on 2 measurements the parameters of the equivalent circuit models for R1 and R2 are extracted ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 26

27 SMD components Approach 1 example: - the equivalent circuit parameters for R1 and R2 are shown in Table 1 SMD resistor Ls Rp Cp R1, 1 Ω 0.86 nh 0.94 Ohm 31 pf R2, 48.7 Ω 1.01 nh Ohm 0 pf ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 27

28 SMD components Approach 2: - firstly, PCB lines including SMA connectors are measured (short line, medium line, long line) (no SMD components are present) - secondly, PCB lines that contain SMD components are measured - thirdly, the de-embedding of the lines is indirectly performed by taking into account the influence of the lines when determining the values of the equivalent circuit parameters ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 28

29 SMD components Approach 2: - two types of circuit structures are used P1 Z2 P2 P1 Z2 P2 Z1 PCB1 PCB2 - PCB2 network is used to model either a resistor or a capacitor ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 29

30 SMD components Approach 2 Example 1: - modelling of a 4.7 nf capacitor ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 30

31 SMD components Approach 2 Example 2: - modelling of a 48.7 Ohm resistor ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 31

32 SMD components Approach 2 Example 2 (continued): - modelling of a 48.7 Ohm resistor ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 32

33 SMD components Tolerance of SMD components is a separate issue: - a family of 10 curves for the capacitor C = 4.7 nf (10% tolerance) -15 C=4.7 nf ( ) Maximum difference = 6.38 db -1 C=4.7 nf ( ) Maximum difference = 1.16 rad S11 [db] S11 [rad] Frequency [Hz] x Frequency [Hz] x 10 9 ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 33

34 SMD components Tolerance (continued): - a family of 10 curves for the capacitor C = 4.7 nf (10% tolerance) 0 C=4.7 nf ( ) Maximum difference = 0.14 db 1 C=4.7 nf ( ) Maximum difference = 0.09 rad S12 [db] -0.4 S12 [rad] Frequency [Hz] x Frequency [Hz] x 10 9 ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 34

35 SMD components Tolerance (continued): - a family of 10 curves for the capacitor C = 4.7 nf (10% tolerance) produces the following variation of the model parameters: Max C=5.17e-09 F (+10% of nominal value of 4.7nF) Min C=4.23e-09 F (-10% of nominal value of 4.7nF) Max Rp=8.18e+11 Ohm, Min Rp=1.47e+11 Ohm Max Ls=5.08e-10 H, Min Ls=2.84e-10 H Max Rs=0.517 Ohm, Min Rs=0 ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 35

36 SMD components Tolerance of SMD resistors: - a family of 10 curves for the resistor R = 48.7 Ohm (1% tolerance) -7.5 R=48.7 Ohm ( ) Maximum difference = 0.70 db 0 R=48.7 Ohm ( ) Maximum difference = 0.13 rad -8-1 S11 [db] S11 [rad] Frequency [Hz] x Frequency [Hz] x 10 9 ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 36

37 SMD components Tolerance of SMD resistors (continued): - a family of 10 curves for the resistor R = 48.7 Ohm (1% tolerance) -3 R=48.7 Ohm ( ) Maximum difference = 0.47 db 0 R=48.7 Ohm ( ) Maximum difference = 0.10 rad S12 [db] S12 [rad] Frequency [Hz] x Frequency [Hz] x 10 9 ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 37

38 SMD components Tolerance of the family of 48.7 Ohm resistors - a family of 10 resistors of R = 48.7 Ohm (1% tolerance) produces the following variation of the model parameters: Max R1=48.7 Ohm (+0.03% of nominal value of 48.7 Ohm) Min R1=46.9 Ohm (-3.6% of nominal value of 48.7 Ohm) Max Cp=5.04e-14 F, Min Cp=0 Max Ls=1.88e-09 H, Min Ls=1.35e-09 H ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 38

39 Contents 1 Introduction 2 PCB modelling 3 SMD components 4 Chip packaging 5 On-chip circuit 6 Results 7 Conclusion ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 39

40 Chip packaging Ansoft Q3D Extractor is used to extract the parasitics from the 3D model of the package Three different packages are modelled: JLCC 84 pin CLCC 84 pin PLCC 84 pin ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 40

41 Chip packaging The 3D model of the JLCC 84 package consists of: Bondwires Leadframe Ceramic case Pins Silicon chip ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 41

42 Contents 1 Introduction 2 PCB modelling 3 SMD components 4 Chip packaging 5 On-chip circuit 6 Results 7 Conclusion ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 42

43 On-chip circuit There is nothing special about this stage (almost nothing) Cadence Spectre is used as a circuit simulator Normally, an RC extraction of the circuit is performed to check the influence of parasitics HERE, as the conducted EM emissions are measured at the ground pin of the chip (i.e. packaged chip), a separate extraction of the on-chip power/ground (PWR/GND) lines is performed by using Ansoft Q3D Extractor Thus, when using the description RC extracted circuit, these words denote the RC extracted circuit without the PWR/GND lines ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 43

44 Contents 1 Introduction 2 PCB modelling 3 SMD components 4 Chip packaging 5 On-chip circuit 6 Results 7 Conclusion ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 44

45 Results EMC models EMC models and simulation strategy The following levels of modelling are used Complete model Without packaging model (all other models included) Without RC extraction of the circuit layout (PWR/GND lines are included as they are extracted separately) Without SMD parasitics Withouth extracted PWR/GND lines Without extracted PCB tracks ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 45

46 Results Simulation time LIN interface is selected as a test circuit Low Voltage part LIN ver. opt. Low VoltageLIN ver. non-opt. part High Voltage part M1 High Voltage part M1 ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 46

47 Results Simulation time The simulations are performed on Pentium GHZ PC Table presents the influence of various EMC models on the simulation time of the reflected and injected power according to the DPI method (IEC ) next page ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 47

48 Results Simulation time EMC Model Simulation time (CPU time) Simulation time w.r.t. full model simulation time Complete model 1 min 9 s 100 % Without packaging model 44 s 64.2 % Without RC extraction of the layout 20 s 28.3 % Without SMD parasitics model 1 min 9 s 100 % Without extracted PWR/GND 57 s 82.6 % Without PCB tracks model 48 s 69.9% NOTE: 1. RC extracted layout consumes most of the simulation time 2. Packaging and PCB tracks introduce approximately the same load 3. PWR/GND extraction has relatively minor influence, while SMD components on the PCB practically present no effort to simulate ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 48

49 Results Simulation time Table on the next page presents the influence of various EMC models on the simulation time of the conducte EM emissions according to IEC ) Here, the model of the input signal generator is added to correctly reproduce the input signal as it is measured next page ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 49

50 Results Simulation time EMC Model Simulation time (CPU time) Simulation time w.r.t. full model simulation time Complete model 13 min 31 s 100 % Without packaging model 6 min 40 s 49.3 % Without RC extraction of the layout 2m 53.3s 21.3 % Without SMD parasitics model 11 min 23 s 84.2 % Without extracted PWR/GND 7 min 55 s 58.6 % Without PCB tracks model 5 min 35 s 41.3 % Without model of the input signal generator 5 min 48 s 42.9 % NOTE: 1. RC extracted layout consumes most of the simulation time again 2. Packaging and PCB tracks contribute similarly to the simulation load, as well as the input signal generator model 3. SMD parasitics have the smallest influence on the simulation time ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 50

51 Results - Accuracy Accuracy of simulations is also checked on the LIN circuit ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 51

52 Results - Accuracy Transmitted and reflected power according to (complete model) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 52

53 Results - Accuracy Transmitted and reflected power according to (without RC extraction of the layout) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 53

54 Results - Accuracy Transmitted and reflected power according to (without PCB parasitics) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 54

55 Results - Accuracy Transmitted and reflected power according to (without on-chip PWR/GND parasitics) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 55

56 Results - Accuracy Transmitted and reflected power according to (without packaging parasitics) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 56

57 Results - Accuracy Transmitted and reflected power according to SUMMARY Model MSE_transmitted MaxE_transmitt ed MSE_reflected MaxE_reflected Complete model Without PCB tracks model Without packaging model Without extracted PWR/GND Without SMD parasitics model Without RC extraction of the layout NOTE: SMD components, packing and PCB tracks are of great importance ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 57

58 Results - Accuracy Transmitted and reflected power according to SUMMARY for LIN2 (second version of the LIN interface) Model MseR_transmitte d MaxE_transmitt ed MseR_refl MaxE_refl Complete model Without PCB tracks model Without packaging model Without extracted PWR/GND Without SMD parasitics model Without RC extraction of the layout NOTE: SMD components, PCB tracks and PWR/GND parasitics are of great importance (as well as RC extracted circuit) ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 58

59 Contents 1 Introduction 2 PCB modelling 3 SMD components 4 Chip packaging 5 On-chip circuit 6 Results 7 Conclusion ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 59

60 Conclusion - 1 This presentation shows the importance of various models that can be used in conducted EMC tests: SMD components: It is shown that SMD components mounted on the PCB are of paramount importance for the accuracy of simulations It is also shown that modelling SMD components introduces a minimum load on the simulation time On the other hand, the extraction of SMD parasitics has to be performed separately for various families of SMD components; variations of the model parameters have to be known ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 60

61 Conclusion - 2 PCB tracks: Correct modelling of PCB tracks is equally important PCB model does consume more time than SMD model, but it is still not the major load during simulations Similarly to modelling SMD components, it does not seem that there is a simple and accurate approach to modelling PCBs exclusively by simulations It seems that it is difficult to build an accurate PCB model without previously manufacturing a PCB 3D EM field simulations, if possible at all for more complex PCB layouts, do not seem to be simple and accurate enough ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 61

62 Conclusion - 3 Packaging: Correct model of the package can be built and simulated relatively easily Defining the model for the 3D EM simulations is time consuming Power/ground extraction: This extraction is of great importance for the accuracy of simulations RC circuit extraction: Although RC extracted circuit consumes a lot of simulation time, this step has to be performed ESSDERC 06, Montreux ROBUSPIC Workshop A. Baric Slide 62