NAND Structure Aware Controller Framework
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1 NAND Structure Aware Controller Framework Santa Clara, CA 1
2 Outline The Challenges of NAND Flash Adaptive Error Mitigation by means of NAND Structure Aware Noise Cells Repair Dynamic Cell Levels Retirement Adaptive RAID Santa Clara, CA 2
3 The Challenges of NAND Flash Increased Error Rate 1.00E-01 Decreased P/E Cycles RBER vs PE Cycle for a 2x nm NAND Flash Device 3D TLC 1.00E-02 Error Rate 2D TLC 2D MLC 3D MLC 2D MLC Bit Error Rate 1.00E E-04 10th Percentile 90th Percentile Bits per mm 2 2D TLC 3D MLC 3D TLC Avg 1.00E P/E Cycle x1000 Trends: Smaller process; Multi-level cell; Stacking cell vertically The factors impact reliability: Fewer electrons in cell; Larger inter-cell interference and disturbance Controller plays key role for conquering challenges Santa Clara, CA 3
4 Methods 2-pass Programming Shadow Program Sequence Randomization Error characterization, mitigation, and data recovery techniques P/E Cycling Data Retention Read-Retry X X X Auto Read Calibration X X X Vth Optimization X X X RAID Refresh X X Error Type Read/Program Disturb Cell to Cell Interference Adaptive Error Mitigation X X X X X X Media Defects X Some ways to improve data recovery: - Advanced error correction algorithms and more credible soft information. - Obtain more optimal Vref by read-retry, calibration and Vth scan. - Flash management mechanism. Santa Clara, CA 4
5 NAND Structure Aware Chip c-1 Chip 0 Plane 0 Block m Page n Chip c-1 Chip 0 Die d-1 Die 0 Die 0 Die 0 Plane p-1 m n RAID Group RAID Group Block m RAID Group Page n Physical structure à the throughput and parallelism. Logical structure à efficient flash management and I/O pipeline. Form parity protection groups across multiple channels, chips, dies together into a RAID Group. Ensure the reliability at all structure levels. Channel 0 Channel h-1 BL WL Santa Clara, CA 5
6 Noise Cells Repair-identify it # of cells -δ Vopt +δ Read as 1 Read as 0 Original distribution F -fast-leakage cell S -slow-leakage cell Hard data Hard data Soft data1 Decoding OK Corrected data Bit flip map After retention time Noise Cell Identifier Hard bit Soft bit 0 Bin 0 Bin RBER, Noise Cells Vth Noise Cells location recorder and cache Filter Noise Cells formula: Hard/soft bit:11 && corrected bit:0 Hard/soft bit:01 && corrected bit:1 Noise Cells: Overlapping after retention. In overlap region à RBE. If the number of Noise Cells is over the decoding capability à UBE. Identify there Cells in the correctable period. Obtain bit flip vector after ECC decode OK. Identify each bit flip whether a Noise Cells by the key formula. Recorder and cache the significant Noise Cells location. When Noise Cells bring out uncorrectable error, ECC manager repair it and re-decoding again. Highly effective at reducing the error bit rate of failed pages. Using more soft bit data and bin area for accurately classifying Noise Cells. Similarly, disturb issues can also apply this method. Santa Clara, CA 6
7 Noise Cells Repair-repair it Skip Noise Cells Predict Noise Cells normalization ECC frame repaired ECC frame Page size spare ECC frame N ECC frame 0 Insert dummy byte on Noise cells, before trans to NAND program Hard data Soft data1n Noise Cells Location Search Table Noise Cells Repairer LDPC Decoder restored ECC frame Strip dummy byte on Noise cells, before decoding spare ECC frame N ECC frame 0 Search Noise Cells on this page. Repair LLR value on the location It is transparent to the processing data path for Firmware. Skip Noise Cells: Filling the Noise Cells with dummy data before trans to NAND, and striping dummy data on Noise Cells, before decoding, the impact of it on the data decoding is avoided. Predict Noise Cells: When starting LDPC soft decoding, the Noise Cells Repairer Engine search the location of Noise Cells, then repairing those LLR s value to a prediction one. The efficiency and space considerations of Noise Cells Location Search Table is a challenge in implementation. Santa Clara, CA 7
8 Dynamic Cell Levels # of cells TLC Page ER (111) ER (111) ER (111) XP P1 (011) P1 (011) P1 (011) UP P2 (001) P2 (001) P2 (001) XP P3 (101) P3 (101) P3 (101) LP P4 (100) P4 (100) P4 (100) XP P5 (000) P5 (000) P5 (000) UP P6 (010) P6 (010) P6 (010) XP P7 (110) P7 (110) P7 (110) Vth The more states are encoded within the same voltage range, the more likely Vth distribution overlap, the more RBER. Increase the margins between the states Vth distributions. The states which are figured by solid line are easier to identify than others. Reading XP is greater difficult than LP/UP, especially in case of disturb/retention issues. The methods of Dynamic Cell Levels: - Tracking blocks P/E and Cell levels. - Downgrade weak one to just use LP/UP to store useful data. - Downgrade weak one to SLC mode. OP was reduced, but endurance and reliability was extended. # of cells SP SLC Mode Block ER (1) P1 (0) Vth Santa Clara, CA 8
9 Retirement Monitor and Statistic page/block errors in runtime Eliminate potential troubles in advance. Reduce the overhead of error handle and the risk of data loss. Retirement Scale Page Block Trigger Condition Graded by bit error count that occurred on page. Statistic error grade and frequency. Define threshold according to different page type Reach threshold à retire page. tprog > MAX à retire this block Statistic retired page count and type. When retired count reach a threshold, we can choose to retire this block or switch to SLC mode block. tbers > MAX à retire block Operation Written dummy data to the retired page, to avoid risk of damage on user data Reduce the cost of data recovery Use the reserved good block to replace the retired one. Reduce the overhead of GC on those blocks, which has too much invalid dummy page. Santa Clara, CA 9
10 Adaptive RAID ECC and E2E data path protection à Bit/Byte level data protection. RAINà Page/Block/Die level protection RAID group number N+1 is a parameter à Balance between performance, failure rate and capacity. RAID stripe size is adjusted dynamically once bad element appears à Enhance the fault-tolerant capability Parity data element rotate on multiple channels à Reduce the impact on reading. Santa Clara, CA 10
11 Welcome to you! Santa Clara, CA 11
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