WAFTL: A Workload Adaptive Flash Translation Layer with Data Partition

Size: px
Start display at page:

Download "WAFTL: A Workload Adaptive Flash Translation Layer with Data Partition"

Transcription

1 WAFTL: A Workload Adaptive Flash Translation Layer with Data Partition Qingsong Wei Bozhao Gong, Suraj Pathak, Bharadwaj Veeravalli, Lingfang Zeng and Kanzo Okada Data Storage Institute, A-STAR, Singapore National University of Singapore MSST 2 May 26, 2

2 Introduction Outline Flash Fills the Performance Gap IOPS,,, s Processor DRAM memory Much faster than Disk(X-X) Non-volatile (Disk like) Low power consumption Light weight Resistance to shock,, s, s s Flash memory Hard Disk Picoseconds Nanoseconds Microseconds Milliseconds Latency

3 Introduction Outline NAND Flash Memory Different access unit Read/write in pages (us) Erase in blocks (very slow, ms) Out-place-Update: Does not allow overwrite. Limited number of erase per cell. -3K for SLC and -3K for MLC. Poor random write performance. Page Block Block Page Block n- m=64/28/256 Page m- Flash Memory

4 Low-level Flash Controller Introduction Outline Flash Translation Layer (FTL) in SSD Embedded Processor SRAM Control Bus NAND Flash NAND Flash NAND Flash LBA PBA Host Host Interface Data Bus Data Buffer Data Bus Flash Bus SATA, SCSI, FC, PCI etc Host I/F Layer Flash Translation Layer NAND I/F Layer NAND Flash NAND Flash NAND Flash

5 State-of-the-Art Outline Page-based FTL + High performance + High space usage + Low garbage collection overhead - Large mapping table - Not scalable Address Mapping table Flash LPN PPN Host Logical Page No (LPN) Block Block Physical Page No (PPN) LPN: Block 2 Block 3

6 State-of-the-Art Outline Block-based FTL + Small mapping table - Low performance - Low space usage (internal fragmentation) - High garbage collection overhead Host Logical Page No (LPN) Logical Block NO (LBN) Physical Block No (PBN) LPN: 7 LBN: 7/2=3 Offset: Address Mapping table LBN PBN PBN: Offset: Flash Block Block Block 2 Block 3

7 State-of-the-Art Outline Log-buffer based Hybrid FTL + Small mapping table + Improved performance comparing to Block-based FTL - Poor performance for random writes because of expensive merge operations Association One to one (BAST) One to Many (FAST, LAST) Many to Many (KAST) Data Block B B B2 B3 B4 L L Log Block Block-level mapping Page-level mapping Merge Operations

8 State-of-the-Art Outline : Demand-based FTL + Partial buffered page-based FTL + Good Performance (but lower than pure page-based FTL) + Reduced memory requirement - Large mapping table Page-based Mapping

9 State-of-the-Art Outline Page-based FTL Block-based FTL Hybrid FTL Performance High Good Low Middle Garbage Collection Overhead Low Low High Middle Favored Workload Random Random Sequential Sequential Mapping table Size Large Large Small Small Workload adaptive No No No No Scalable with SSD capacity No No Yes Yes Generally limited in one way or another, either in memory requirement, performance, garbage collection overhead or scalability.

10 WAFTL: Outline Workload Adaptive FTL Design Rationale Data Data Block-level Mapping Blocks (BMB) Page-level Mapping Blocks (PMB) Block... Flash Memory

11 WAFTL: Outline Workload Adaptive FTL Design Rationale Buffer Zone Page-level Mapping Data Partition Data Data Block-level Mapping Blocks (BMB) Page-level Mapping Blocks (PMB)

12 WAFTL: Outline Workload Adaptive FTL Two-level Address Translation Process Page Mapping Table (PMT) LPN Global Mapping Table (GMT) LPN PPN 3 PPN... LBN PBN LBN =LPN/Blk_Size - Page Mapping Blocks Block Offset: LPN mod Blk_Size 3 2 PBN +... LPN: Logical Page Number PPN: Physical Page Number LBN: Logical Block Number PBN: Physical Block Number Block Offset Block Mapping Blocks

13 WAFTL: Outline Workload Adaptive FTL Layout and In-memory Data Structure Request SRAM Buffer Zone Mapping Tree (BZMT) Global Mapping Table (GMT) LBN PBN 2 - Cached Page Mapping Table (CPMT) LPN PPN Data access Mapping replacement M PPN = M PPN =5 LBN PBN LPN PPN Data M VPN = M VPN = BMB PMB GMT PMT Buffer Zone Data Blocks Mapping Table Blocks

14 WAFTL: Outline Workload Adaptive FTL Buffer Zone Mapping Tree Key: Block Number Root node Interior node Leaf node Page count Block Popularity Block Dirty Pointer Array Block Node LPN 2 22 PPN Dirty Page-level mapping Buffer Zone Page 4 of 9

15 WAFTL: Outline Workload Adaptive FTL Buffer Zone Migration Block No: Block No: 2 Block No: Popularity: 3 Page count:4 8 9 Popularity: 2 Page count: Popularity: 2 Page count: Most Popular Block Yes No Page count >=Threshold Yes No Buffer Zone Buffer Dirty Buffer Zone Zone Data Active Page Active BMB Active PMB BMB PMB

16 Mapping Table Size(MB) Average Reesponse Time(ms) WAFTL: Outline Workload Adaptive FTL Determining Migration Threshold Performance oriented threshold Threshold is statically set as full block size and only full block data is stored into BMB. BEST performance, but Big Mapping table Dynamic threshold considering memory constraint Initially, THR is set to Block size THR decreases to a smaller value if performance degradation is smaller than D, and mapping table reduction is larger than D. D is a control parameter defined by users Fin Fin Threshold(pages) P P Blk _ size M M Blk _ size P THR M P P Blk _ size Blk _ size M Blk _ size M Blk _ size THR P THR and P Blk_size represent performance when threshold is set as THR and full block, respectively. M THR and M Blk_size represent mapping table size when threshold is set as THR and full block, respectively D D Threshold(pages) Fin Fin 2 Mapping table size is more sensitive to threshold than performance.

17 WAFTL: Outline Workload Adaptive FTL Garbage Collection Policy Requests Idle time Service time Offline Garbage Collection block erasure 2 blocks erasure block erasure Idle period (t predicti ) is predicted as t i predict t i real ( ) t i predict WAFTL use predicted idle length to calculate and determine how many invalid blocks (N i ) to be erased according to following Equation N i i t T predict erasure if if t t i predict i predict T T erasure erasure

18 Evaluation Outline Setup SSD Simulator FTL schemes: WAFTL, Pure Pagebased,, FAST 7 enterprise workloads Evaluation Metrics Average response time Erase count Page read/write operations Workload Traces Configuration Page Read to Register Page Program (Write) from Register Block Erase Serial Access to Register (Data bus) SSD Die Size Block Size Page Size Data Register Erase Cycles Buffer Zone sizes : 256MB/52MB/GB Workloads Avg. Req. Size(KB) Write(%) Seq.(%) Avg. Req. Inter-arrive Time(ms) Fin %.6% 8.89 Fin %.7%.8 Exchange %.5%.348 DevDiv %.9% DevDiv %.5% Sequential Read % 6% Sequential Write % 7% μs 2μs.5ms μs 2 GB 256 KB 4 KB 4 KB K SRAM for and WAFTL: 256KB For pure page-level FTL and FAST, we assume SRAM is enough to hold entire mapping table.

19 Average Response Time(ms) Erase Count() Page operations(million) Average Response Time(ms) Erase Count() Page operations(million) Evaluation Outline Pure Page FTL FAST WAFTL Zone52MB 32GB 48GB 64GB 8GB SSD Capacity WAFTL Zone=256MB WAFTL Zone=GB Pure Page FTL FAST WAFTL Zone=52MB 32GB 48GB 64GB 8GB SSD Capacity WAFTL Zone=256MB WAFTL Zone=GB Pure Page FTL Page write Page read Fin Trace (Static Migration threshold=64pages,256kb) FAST WAFTL Zone=GB.6.5 Pure Page FTL FAST WAFTL Zone=52MB WAFTL Zone=256MB WAFTL Zone=GB 25 2 Pure Page FTL FAST WAFTL Zone=52MB WAFTL Zone=256MB WAFTL Zone=GB 3 25 Page write Page read GB 48GB 64GB 8GB SSD Capacity 32GB 48GB 64GB 8GB SSD Capacity Pure Page FTL Fin2 Trace (Static Migration threshold=64pages,256kb) FAST WAFTL Zone=GB

20 Average Response Time(ms) Erase Count() Page operations(million) Average Response Time(ms) Erase Count() Page operations(million) Evaluation Outline Pure Page FTL FAST WAFTL Zone=52MB WAFTL Zone=256MB WAFTL Zone=GB Pure Page FTL FAST WAFTL Zone=52MB WATL Zone=256MB WAFTL Zone=GB Page write Page read GB 48GB 64GB 8GB SSD Capacity 32GB 48GB 64GB 8GB SSD Capacity Pure Page FTL FAST WAFTL Zone=GB Exchange Trace (Static Migration threshold=64pages,256kb) Pure Page FTL FAST WAFTL Zone=52MB WAFTL Zone=256MB WAFTL Zone=GB 2 Pure Page FTL FAST WAFTL Zone=52MB WAFTL Zone=256MB WAFTL Zone=GB 2 Page write Page read GB 48GB 64GB 8GB SSD Capacity 32GB 48GB 64GB 8GB SSD Capacity Pure Page FTL FAST WAFTL Zone=GB DevDiv Trace (Static Migration threshold=64pages,256kb)

21 Average Response Time(ms) Erase Count() Page operations(million) Average Response Time(ms) Erase Count() Page operations(million) Evaluation Outline Pure Page FTL FAST WAFTL Zone=52MB 32GB 48GB 64GB 8GB SSD Capacity WAFTL Zone=256MB WAFTL Zone=GB Pure Page FTL FAST WAFTL Zone=52MB 32GB 48GB 64GB 8GB SSD Capacity WAFTL Zone=256MB WAFTL Zone=GB Pure Page FTL Page write Page read DevDiv9 Trace (Static Migration threshold=64pages,256kb) FAST WAFTL Zone=GB 6 5 Pure Page FTL FAST WAFTL Zone=52MB WAFTL Zone=256MB WAFTL Zone=GB 3 25 Pure Page FTL FAST WAFTL Zone=52MB WAFTL Zone=256MB WAFTL Zone=GB 3 25 Page write Page read GB 48GB 64GB 8GB SSD Capacity GB 48GB 64GB 8GB SSD Capacity 5 5 Pure Page FTL Seq_Read Trace (Static Migration threshold=64pages,256kb) FAST WAFTL Zone=GB

22 Mapping table size(mb) PMB Blocks Distribution(%) Evaluation Outline Workload adaptive 8 256MB Buffer Zone 52MB Buffer Zone GB Buffer Zone WAFTL is adaptive to workloads (32GB SSD) Fin Fin 2 Exchange DevDiv DevDiv9 Seq-Read Seq-Write Traces 4 Pure Page Mapping FAST WAFTL Mapping table sizes under different workloads (256MB buffer zone, 32GB SSD) 3 2 Fin Fin 2 Exchange DevDiv DevDiv9 Seq-Read Seq-Write Traces

23 Mapping Table Size(MB) Average Reesponse Time(ms) Evaluation Outline Effect of Threshold Dynamic Threshold D=.6 Dynamic Threshold D=.3 Static Threshold THR= Buffer Zone: 256MB SSD: 32GB, 64Pages/Block Fin Fin 2 Exchange DevDiv DevDiv9 Seq-Read Seq-Write Traces 3 Dynamic Threshold D=.6 Dynamic Threshold D=.3 Static Threshold THR=64 2 4% 6% Buffer Zone:256MB SSD: 32GB, 64Pages/Block Fin Fin 2 Exchange DevDiv DevDiv9 Seq-Read Seq-Write Traces

24 Conclusion Outline WAFTL explores either page-level or block-level address mapping for data blocks based on access patterns in order to balance the mapping efficiency of a block-based approach and the GC efficiency of a page-based approach. a small part of NAND flash space for the buffer area to log data sequentially until it is full and then migrate them into either a page mapping block or block mapping block, depending on the migration threshold. different scheme to determine the value of migration threshold thereby, improving performance while reducing the mapping table size at the same time.

25

The Critical Role of Firmware and Flash Translation Layers in Solid State Drive Design

The Critical Role of Firmware and Flash Translation Layers in Solid State Drive Design The Critical Role of Firmware and Flash Translation Layers in Solid State Drive Design Robert Sykes Director of Applications OCZ Technology Flash Memory Summit 2012 Santa Clara, CA 1 Introduction This

More information

SSD Firmware Implementation Project Lab. #1

SSD Firmware Implementation Project Lab. #1 SSD Firmware Implementation Project Lab. #1 Sang Phil Lim (lsfeel0204@gmail.com) SKKU VLDB Lab. 2011 03 24 Contents Project Overview Lab. Time Schedule Project #1 Guide FTL Simulator Development Project

More information

Enhancing System Architecture by Modelling the Flash Translation Layer

Enhancing System Architecture by Modelling the Flash Translation Layer Enhancing System Architecture by Modelling the Flash Translation Layer Robert Sykes Sr. Dir. Firmware August 2014 OCZ Storage Solutions A Toshiba Group Company Introduction This presentation will discuss

More information

Greedy FTL. Jinyong Ha Computer Systems Laboratory Sungkyunkwan University

Greedy FTL. Jinyong Ha Computer Systems Laboratory Sungkyunkwan University Greedy FTL Jinyong Ha (Jinyongha@csl.skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Contents DRAM Controller FTL Metadata Garbage Collection Power-Off Recovery Greedy

More information

Bridging the Information Gap Between Buffer and Flash Translation Layer for Flash Memory

Bridging the Information Gap Between Buffer and Flash Translation Layer for Flash Memory 2011 IEEE Transactions on Consumer Electronics Bridging the Information Gap Between Buffer and Flash Translation Layer for Flash Memory Xue-liang Liao Shi-min Hu Department of Computer Science and Technology,

More information

Improving MLC flash performance and endurance with Extended P/E Cycles

Improving MLC flash performance and endurance with Extended P/E Cycles Improving MLC flash performance and endurance with Extended P/E Cycles Fabio Margaglia Johannes Gutenberg-Universität Mainz, Germany Email: margagl@uni-mainz.de André Brinkmann Johannes Gutenberg-Universität

More information

Application-Managed Flash Sungjin Lee, Ming Liu, Sangwoo Jun, Shuotao Xu, Jihong Kim and Arvind

Application-Managed Flash Sungjin Lee, Ming Liu, Sangwoo Jun, Shuotao Xu, Jihong Kim and Arvind Application-Managed Flash Sungjin Lee, Ming Liu, Sangwoo Jun, Shuotao Xu, Jihong Kim and Arvind Massachusetts Institute of Technology Seoul National University 14th USENIX Conference on File and Storage

More information

Sang-Phil Lim Sungkyunkwan University. Sang-Won Lee Sungkyunkwan University. Bongki Moon University of Arizona

Sang-Phil Lim Sungkyunkwan University. Sang-Won Lee Sungkyunkwan University. Bongki Moon University of Arizona Sang-Phil Lim Sungkyunkwan University Sang-Won Lee Sungkyunkwan University Bongki Moon University of Arizona Table of Contents Mo.va.on Background NAND Flash Memory and Flash Transla>on Layer (FTL) FAST

More information

NetApp Sizing Guidelines for MEDITECH Environments

NetApp Sizing Guidelines for MEDITECH Environments Technical Report NetApp Sizing Guidelines for MEDITECH Environments Brahmanna Chowdary Kodavali, NetApp March 2016 TR-4190 TABLE OF CONTENTS 1 Introduction... 4 1.1 Scope...4 1.2 Audience...5 2 MEDITECH

More information

A Superblock-based Flash Translation Layer for NAND Flash Memory

A Superblock-based Flash Translation Layer for NAND Flash Memory A Superblock-based Flash Translation Layer for NAND Flash Memory Jeong-Uk Kang, HeeseungJo, Jin-Soo Kim, Joonwon Lee Korea Advanced Institute of Science and Technology (KAIST) EMSOFT 06, October 22 25,

More information

Diversifying Wear Index for MLC NAND Flash Memory to Extend the Lifetime of SSDs

Diversifying Wear Index for MLC NAND Flash Memory to Extend the Lifetime of SSDs Diversifying Wear Index for MLC NAND Flash Memory to Extend the Lifetime of SSDs Yeong-Jae Woo Samsung Electronics Co. Hwaseong, South Korea yeongjae.woo@samsung.com Jin-Soo Kim Sungkyunkwan University

More information

Lecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University

Lecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University Lecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 1 Outline

More information

Ramon Canal NCD Master MIRI. NCD Master MIRI 1

Ramon Canal NCD Master MIRI. NCD Master MIRI 1 Wattch, Hotspot, Hotleakage, McPAT http://www.eecs.harvard.edu/~dbrooks/wattch-form.html http://lava.cs.virginia.edu/hotspot http://lava.cs.virginia.edu/hotleakage http://www.hpl.hp.com/research/mcpat/

More information

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM

RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM Fengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu, Shaojun Wei Institute of Microelectronics Tsinghua University The 45th International

More information

Lecture #29. Moore s Law

Lecture #29. Moore s Law Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday

More information

Lecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM

Lecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM Semiconductor Memory Classification Lecture 12 Memory Circuits RWM NVRWM ROM Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Reading: Weste Ch 8.3.1-8.3.2, Rabaey

More information

FIFO WITH OFFSETS HIGH SCHEDULABILITY WITH LOW OVERHEADS. RTAS 18 April 13, Björn Brandenburg

FIFO WITH OFFSETS HIGH SCHEDULABILITY WITH LOW OVERHEADS. RTAS 18 April 13, Björn Brandenburg FIFO WITH OFFSETS HIGH SCHEDULABILITY WITH LOW OVERHEADS RTAS 18 April 13, 2018 Mitra Nasri Rob Davis Björn Brandenburg FIFO SCHEDULING First-In-First-Out (FIFO) scheduling extremely simple very low overheads

More information

Fall 2015 COMP Operating Systems. Lab #7

Fall 2015 COMP Operating Systems. Lab #7 Fall 2015 COMP 3511 Operating Systems Lab #7 Outline Review and examples on virtual memory Motivation of Virtual Memory Demand Paging Page Replacement Q. 1 What is required to support dynamic memory allocation

More information

THE content-addressable memory (CAM) is one of the most

THE content-addressable memory (CAM) is one of the most 254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 1, JANUARY 2005 A 0.7-fJ/Bit/Search 2.2-ns Search Time Hybrid-Type TCAM Architecture Sungdae Choi, Kyomin Sohn, and Hoi-Jun Yoo Abstract This paper

More information

Data Center Energy Trends

Data Center Energy Trends Data Center Energy Trends Data center electricity usage Increased by 56% from 2005 to 2010 1.1% to 1.5% total world electricity usage 1.7% to 2.2% total US electricity (Note: Includes impact of 2008 recession.)

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 24: Peripheral Memory Circuits

CMPEN 411 VLSI Digital Circuits Spring Lecture 24: Peripheral Memory Circuits CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 24: Peripheral Memory Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11

More information

NAND Structure Aware Controller Framework

NAND Structure Aware Controller Framework NAND Structure Aware Controller Framework mengxin@derastorage.com Santa Clara, CA 1 Outline The Challenges of NAND Flash Adaptive Error Mitigation by means of NAND Structure Aware Noise Cells Repair Dynamic

More information

Architecture of Computers and Parallel Systems Part 9: Digital Circuits

Architecture of Computers and Parallel Systems Part 9: Digital Circuits Architecture of Computers and Parallel Systems Part 9: Digital Circuits Ing. Petr Olivka petr.olivka@vsb.cz Department of Computer Science FEI VSB-TUO Architecture of Computers and Parallel Systems Part

More information

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura System LSI Research Center Kyushu

More information

Mosaic: A GPU Memory Manager with Application-Transparent Support for Multiple Page Sizes

Mosaic: A GPU Memory Manager with Application-Transparent Support for Multiple Page Sizes Mosaic: A GPU Memory Manager with Application-Transparent Support for Multiple Page Sizes Rachata Ausavarungnirun Joshua Landgraf Vance Miller Saugata Ghose Jayneel Gandhi Christopher J. Rossbach Onur

More information

CS4617 Computer Architecture

CS4617 Computer Architecture 1/26 CS4617 Computer Architecture Lecture 2 Dr J Vaughan September 10, 2014 2/26 Amdahl s Law Speedup = Execution time for entire task without using enhancement Execution time for entire task using enhancement

More information

Microarchitectural Attacks and Defenses in JavaScript

Microarchitectural Attacks and Defenses in JavaScript Microarchitectural Attacks and Defenses in JavaScript Michael Schwarz, Daniel Gruss, Moritz Lipp 25.01.2018 www.iaik.tugraz.at 1 Michael Schwarz, Daniel Gruss, Moritz Lipp www.iaik.tugraz.at Microarchitecture

More information

CSE 237A Winter 2018 Homework 1

CSE 237A Winter 2018 Homework 1 CSE 237A Winter 2018 Homework 1 Problem 1 [10 pts] a) As discussed in the lecture, ARM based systems are widely used in the embedded computing. Choose one embedded application and compare features (e.g.,

More information

Improving the Reliability of. NAND Flash, Phase-change RAM and Spin-torque Transfer RAM. Chengen Yang

Improving the Reliability of. NAND Flash, Phase-change RAM and Spin-torque Transfer RAM. Chengen Yang Improving the Reliability of NAND Flash, Phase-change RAM and Spin-torque Transfer RAM by Chengen Yang A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy

More information

LSI and Circuit Technologies for the SX-8 Supercomputer

LSI and Circuit Technologies for the SX-8 Supercomputer LSI and Circuit Technologies for the SX-8 Supercomputer By Jun INASAKA,* Toshio TANAHASHI,* Hideaki KOBAYASHI,* Toshihiro KATOH,* Mikihiro KAJITA* and Naoya NAKAYAMA This paper describes the LSI and circuit

More information

Application Note Model 765 Pulse Generator for Semiconductor Applications

Application Note Model 765 Pulse Generator for Semiconductor Applications Application Note Model 765 Pulse Generator for Semiconductor Applications Non-Volatile Memory Cells Characterization The trend of memory research is to develop a new memory called Non-Volatile RAM that

More information

Memory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities

Memory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities Memory Basics RAM: Random Access Memory historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities ROM: Read Only Memory no capabilities for

More information

A Novel Technique to Reduce Write Delay of SRAM Architectures

A Novel Technique to Reduce Write Delay of SRAM Architectures A Novel Technique to Reduce Write Delay of SRAM Architectures SWAPNIL VATS AND R.K. CHAUHAN * Department of Electronics and Communication Engineering M.M.M. Engineering College, Gorahpur-73 010, U.P. INDIA

More information

EE 330 Lecture 12. Devices in Semiconductor Processes. Diodes

EE 330 Lecture 12. Devices in Semiconductor Processes. Diodes EE 330 Lecture 12 Devices in Semiconductor Processes Diodes Guest Lecture: Joshua Abbott Non Volatile Product Engineer Micron Technology NAND Memory: Operation, Testing and Challenges Intro to Flash Memory

More information

Data Storage Using a Non-integer Number of Bits per Cell

Data Storage Using a Non-integer Number of Bits per Cell Data Storage Using a Non-integer Number of Bits per Cell Naftali Sommer June 21st, 2017 The Conventional Scheme Information is stored in a memory cell by setting its threshold voltage 1 bit/cell - Many

More information

Utilization Based Duty Cycle Tuning MAC Protocol for Wireless Sensor Networks

Utilization Based Duty Cycle Tuning MAC Protocol for Wireless Sensor Networks Utilization Based Duty Cycle Tuning MAC Protocol for Wireless Sensor Networks Shih-Hsien Yang, Hung-Wei Tseng, Eric Hsiao-Kuang Wu, and Gen-Huey Chen Dept. of Computer Science and Information Engineering,

More information

UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering. Computer Architecture ECE 568

UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering. Computer Architecture ECE 568 UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Computer Architecture ECE 568 Part 14 Improving Performance: Interleaving Israel Koren ECE568/Koren Part.14.1 Background Performance

More information

UNIT-II LOW POWER VLSI DESIGN APPROACHES

UNIT-II LOW POWER VLSI DESIGN APPROACHES UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.

More information

EEC 216 Lecture #10: Ultra Low Voltage and Subthreshold Circuit Design. Rajeevan Amirtharajah University of California, Davis

EEC 216 Lecture #10: Ultra Low Voltage and Subthreshold Circuit Design. Rajeevan Amirtharajah University of California, Davis EEC 216 Lecture #1: Ultra Low Voltage and Subthreshold Circuit Design Rajeevan Amirtharajah University of California, Davis Opportunities for Ultra Low Voltage Battery Operated and Mobile Systems Wireless

More information

MS Project :Trading Accuracy for Power with an Under-designed Multiplier Architecture Parag Kulkarni Adviser : Prof. Puneet Gupta Electrical Eng.

MS Project :Trading Accuracy for Power with an Under-designed Multiplier Architecture Parag Kulkarni Adviser : Prof. Puneet Gupta Electrical Eng. MS Project :Trading Accuracy for Power with an Under-designed Multiplier Architecture Parag Kulkarni Adviser : Prof. Puneet Gupta Electrical Eng., UCLA - http://nanocad.ee.ucla.edu/ 1 Outline Introduction

More information

Static Energy Reduction Techniques in Microprocessor Caches

Static Energy Reduction Techniques in Microprocessor Caches Static Energy Reduction Techniques in Microprocessor Caches Heather Hanson, Stephen W. Keckler, Doug Burger Computer Architecture and Technology Laboratory Department of Computer Sciences Tech Report TR2001-18

More information

Clay Codes: Moulding MDS Codes to Yield an MSR Code

Clay Codes: Moulding MDS Codes to Yield an MSR Code Clay Codes: Moulding MDS Codes to Yield an MSR Code Myna Vajha, Vinayak Ramkumar, Bhagyashree Puranik, Ganesh Kini, Elita Lobo, Birenjith Sasidharan Indian Institute of Science (IISc) P. Vijay Kumar (IISc

More information

Leakage Power Minimization in Deep-Submicron CMOS circuits

Leakage Power Minimization in Deep-Submicron CMOS circuits Outline Leakage Power Minimization in Deep-Submicron circuits Politecnico di Torino Dip. di Automatica e Informatica 1019 Torino, Italy enrico.macii@polito.it Introduction. Design for low leakage: Basics.

More information

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09

Used Semiconductor Manufacturing Equipment: Looking for Sales in All the Right Places. Study Number MA108-09 Study Number MA108-09 August 2009 Copyright Semico Research, 2009. All rights reserved. Reproduction in whole or part is prohibited without permission of Semico. The contents of this report represent

More information

INF3430 Clock and Synchronization

INF3430 Clock and Synchronization INF3430 Clock and Synchronization P.P.Chu Using VHDL Chapter 16.1-6 INF 3430 - H12 : Chapter 16.1-6 1 Outline 1. Why synchronous? 2. Clock distribution network and skew 3. Multiple-clock system 4. Meta-stability

More information

A Static Power Model for Architects

A Static Power Model for Architects A Static Power Model for Architects J. Adam Butts and Guri Sohi University of Wisconsin-Madison {butts,sohi}@cs.wisc.edu 33rd International Symposium on Microarchitecture Monterey, California December,

More information

VLSI System Testing. Outline

VLSI System Testing. Outline ECE 538 VLSI System Testing Krish Chakrabarty System-on-Chip (SOC) Testing ECE 538 Krish Chakrabarty 1 Outline Motivation for modular testing of SOCs Wrapper design IEEE 1500 Standard Optimization Test

More information

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy School of Electrical and Computer Engineering, Purdue University,

More information

Nonlinear Multi-Error Correction Codes for Reliable MLC NAND Flash Memories Zhen Wang, Mark Karpovsky, Fellow, IEEE, and Ajay Joshi, Member, IEEE

Nonlinear Multi-Error Correction Codes for Reliable MLC NAND Flash Memories Zhen Wang, Mark Karpovsky, Fellow, IEEE, and Ajay Joshi, Member, IEEE IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 7, JULY 2012 1221 Nonlinear Multi-Error Correction Codes for Reliable MLC NAND Flash Memories Zhen Wang, Mark Karpovsky, Fellow,

More information

Arda Gumusalan CS788Term Project 2

Arda Gumusalan CS788Term Project 2 Arda Gumusalan CS788Term Project 2 1 2 Logical topology formation. Effective utilization of communication channels. Effective utilization of energy. 3 4 Exploits the tradeoff between CPU speed and time.

More information

A Three-Port Adiabatic Register File Suitable for Embedded Applications

A Three-Port Adiabatic Register File Suitable for Embedded Applications A Three-Port Adiabatic Register File Suitable for Embedded Applications Stephen Avery University of New South Wales s.avery@computer.org Marwan Jabri University of Sydney marwan@sedal.usyd.edu.au Abstract

More information

Opportunities and Challenges in Ultra Low Voltage CMOS. Rajeevan Amirtharajah University of California, Davis

Opportunities and Challenges in Ultra Low Voltage CMOS. Rajeevan Amirtharajah University of California, Davis Opportunities and Challenges in Ultra Low Voltage CMOS Rajeevan Amirtharajah University of California, Davis Opportunities for Ultra Low Voltage Battery Operated and Mobile Systems Wireless sensors RFID

More information

Status and Prospect for MRAM Technology

Status and Prospect for MRAM Technology Status and Prospect for MRAM Technology Dr. Saied Tehrani Nonvolatile Memory Seminar Hot Chips Conference August 22, 2010 Memorial Auditorium Stanford University Everspin Technologies, Inc. - 2010 Agenda

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 13 Building Blocks (Multipliers) Register Adder Shift Register Adib Abrishamifar EE Department IUST Acknowledgement This lecture note has been summarized and categorized

More information

Supporting x86-64 Address Translation for 100s of GPU Lanes. Jason Power, Mark D. Hill, David A. Wood

Supporting x86-64 Address Translation for 100s of GPU Lanes. Jason Power, Mark D. Hill, David A. Wood Supporting x86-64 Address Translation for 100s of GPU s Jason Power, Mark D. Hill, David A. Wood Summary Challenges: CPU&GPUs physically integrated, but logically separate; This reduces theoretical bandwidth,

More information

Benchmarking C++ From video games to algorithmic trading. Alexander Radchenko

Benchmarking C++ From video games to algorithmic trading. Alexander Radchenko Benchmarking C++ From video games to algorithmic trading Alexander Radchenko Quiz. How long it takes to run? 3.5GHz Xeon at CentOS 7 Write your name Write your guess as a single number Write time units

More information

MULTI-PORT MEMORY DESIGN FOR ADVANCED COMPUTER ARCHITECTURES. by Yirong Zhao Bachelor of Science, Shanghai Jiaotong University, P. R.

MULTI-PORT MEMORY DESIGN FOR ADVANCED COMPUTER ARCHITECTURES. by Yirong Zhao Bachelor of Science, Shanghai Jiaotong University, P. R. MULTI-PORT MEMORY DESIGN FOR ADVANCED COMPUTER ARCHITECTURES by Yirong Zhao Bachelor of Science, Shanghai Jiaotong University, P. R. China, 2011 Submitted to the Graduate Faculty of the Swanson School

More information

Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance

Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance Architectural Core Salvaging in a Multi-Core Processor for Hard-Error Tolerance Michael D. Powell, Arijit Biswas, Shantanu Gupta, and Shubu Mukherjee SPEARS Group, Intel Massachusetts EECS, University

More information

Extending NAND Endurance with Advanced Controller Technology

Extending NAND Endurance with Advanced Controller Technology Extending NAND Endurance with Advanced Controller Technology Wei Lin System Architect, Phison wei_lin@phison.com PHISON s presentation contains forward-looking statements subject to significant risks and

More information

DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM

DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM 1 Mitali Agarwal, 2 Taru Tevatia 1 Research Scholar, 2 Associate Professor 1 Department of Electronics & Communication

More information

EE382V-ICS: System-on-a-Chip (SoC) Design

EE382V-ICS: System-on-a-Chip (SoC) Design EE38V-CS: System-on-a-Chip (SoC) Design Hardware Synthesis and Architectures Source: D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Chapter 6:

More information

Digital Microelectronic Circuits ( ) CMOS Digital Logic. Lecture 6: Presented by: Adam Teman

Digital Microelectronic Circuits ( ) CMOS Digital Logic. Lecture 6: Presented by: Adam Teman Digital Microelectronic Circuits (361-1-3021 ) Presented by: Adam Teman Lecture 6: CMOS Digital Logic 1 Last Lectures The CMOS Inverter CMOS Capacitance Driving a Load 2 This Lecture Now that we know all

More information

Selecting Telecommunication Test Equipment To Maximize Throughput and Accuracy. By Robert Green Keithley Instruments, Inc.

Selecting Telecommunication Test Equipment To Maximize Throughput and Accuracy. By Robert Green Keithley Instruments, Inc. Selecting Telecommunication Test Equipment To Maximize Throughput and Accuracy By Robert Green Keithley Instruments, Inc. Soaring demand for cell phones, pagers mobile radios and base-stations, is putting

More information

A Robust Low Power Static Random Access Memory Cell Design

A Robust Low Power Static Random Access Memory Cell Design Wright State University CORE Scholar Browse all Theses and Dissertations Theses and Dissertations 2018 A Robust Low Power Static Random Access Memory Cell Design A. V. Rama Raju Pusapati Wright State University

More information

Team VeryLargeScaleEngineers Robert Costanzo Michael Recachinas Hector Soto. High Speed 64kb SRAM. ECE 4332 Fall 2013

Team VeryLargeScaleEngineers Robert Costanzo Michael Recachinas Hector Soto. High Speed 64kb SRAM. ECE 4332 Fall 2013 Team VeryLargeScaleEngineers Robert Costanzo Michael Recachinas Hector Soto High Speed 64kb SRAM ECE 4332 Fall 2013 Outline Problem Design Approach & Choices Circuit Block Architecture Novelties Layout

More information

PROBE: Prediction-based Optical Bandwidth Scaling for Energy-efficient NoCs

PROBE: Prediction-based Optical Bandwidth Scaling for Energy-efficient NoCs PROBE: Prediction-based Optical Bandwidth Scaling for Energy-efficient NoCs Li Zhou and Avinash Kodi Technologies for Emerging Computer Architecture Laboratory (TEAL) School of Electrical Engineering and

More information

EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3. EECS 427 F09 Lecture Reminders

EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3. EECS 427 F09 Lecture Reminders EECS 427 Lecture 13: Leakage Power Reduction Readings: 6.4.2, CBF Ch.3 [Partly adapted from Irwin and Narayanan, and Nikolic] 1 Reminders CAD assignments Please submit CAD5 by tomorrow noon CAD6 is due

More information

A Low-Power SRAM Design Using Quiet-Bitline Architecture

A Low-Power SRAM Design Using Quiet-Bitline Architecture A Low-Power SRAM Design Using uiet-bitline Architecture Shin-Pao Cheng Shi-Yu Huang Electrical Engineering Department National Tsing-Hua University, Taiwan Abstract This paper presents a low-power SRAM

More information

Contents 1 Introduction 2 MOS Fabrication Technology

Contents 1 Introduction 2 MOS Fabrication Technology Contents 1 Introduction... 1 1.1 Introduction... 1 1.2 Historical Background [1]... 2 1.3 Why Low Power? [2]... 7 1.4 Sources of Power Dissipations [3]... 9 1.4.1 Dynamic Power... 10 1.4.2 Static Power...

More information

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important! EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback

More information

On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? Mohamed Hassan

On the Off-chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option? Mohamed Hassan On the Off-chip Memory Latency of eal-time Systems: Is DD DAM eally the Best Option? Mohamed Hassan Motivation 2 PEDICTABILITY DAMs 3 LDAM 4 esults 5 Outline Historically, SAMs have been the option for

More information

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS The major design challenges of ASIC design consist of microscopic issues and macroscopic issues [1]. The microscopic issues are ultra-high

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: November 8, 2017 at 09:27 CS429 Slideset 14: 1 Overview What s wrong

More information

Simulation Performance Optimization of Virtual Prototypes Sammidi Mounika, B S Renuka

Simulation Performance Optimization of Virtual Prototypes Sammidi Mounika, B S Renuka Simulation Performance Optimization of Virtual Prototypes Sammidi Mounika, B S Renuka Abstract Virtual prototyping is becoming increasingly important to embedded software developers, engineers, managers

More information

A Comparative Simulation Study of Four Multilevel DRAMs

A Comparative Simulation Study of Four Multilevel DRAMs A Comparative Simulation Study of Four Multilevel DRAMs Gershom Birk, Duncan Elliott, Bruce Cockburn Department of Electrical & Computer Engineering University of Alberta Edmonton, Alberta, Canada Outline

More information

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering FPGA Fabrics Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 CPLD / FPGA CPLD Interconnection of several PLD blocks with Programmable interconnect on a single chip Logic blocks executes

More information

Processors Processing Processors. The meta-lecture

Processors Processing Processors. The meta-lecture Simulators 5SIA0 Processors Processing Processors The meta-lecture Why Simulators? Your Friend Harm Why Simulators? Harm Loves Tractors Harm Why Simulators? The outside world Unfortunately for Harm you

More information

Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM

Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM [ 2007 International Conference on VLSI Design ] Jan. 9, 2007 Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, *Akira

More information

COMP Online Algorithms. Paging and k-server Problem. Shahin Kamali. Lecture 11 - Oct. 11, 2018 University of Manitoba

COMP Online Algorithms. Paging and k-server Problem. Shahin Kamali. Lecture 11 - Oct. 11, 2018 University of Manitoba COMP 7720 - Online Algorithms Paging and k-server Problem Shahin Kamali Lecture 11 - Oct. 11, 2018 University of Manitoba COMP 7720 - Online Algorithms Paging and k-server Problem 1 / 19 Review & Plan

More information

FPGA Based System Design

FPGA Based System Design FPGA Based System Design Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 Why VLSI? Integration improves the design: higher speed; lower power; physically smaller. Integration reduces

More information

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering

Low-Power VLSI. Seong-Ook Jung VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Low-Power VLSI Seong-Ook Jung 2013. 5. 27. sjung@yonsei.ac.kr VLSI SYSTEM LAB, YONSEI University School of Electrical & Electronic Engineering Contents 1. Introduction 2. Power classification & Power performance

More information

Low Power Design Part I Introduction and VHDL design. Ricardo Santos LSCAD/FACOM/UFMS

Low Power Design Part I Introduction and VHDL design. Ricardo Santos LSCAD/FACOM/UFMS Low Power Design Part I Introduction and VHDL design Ricardo Santos ricardo@facom.ufms.br LSCAD/FACOM/UFMS Motivation for Low Power Design Low power design is important from three different reasons Device

More information

Barrier Engineering. Flash Memory. Rich Liu Macronix International Co., Ltd. Hsinchu, Taiwan, R.O.C. 1/ A*STAR/SRC/NSF Memory Forum

Barrier Engineering. Flash Memory. Rich Liu Macronix International Co., Ltd. Hsinchu, Taiwan, R.O.C. 1/ A*STAR/SRC/NSF Memory Forum Barrier Engineering g Scaling Limitations of Flash Memory Rich Liu Macronix International Co., Ltd. Hsinchu, Taiwan, R.O.C. 1/ Source Floating Gate NAND Device 1 Control gate ONO Floating gate Oxide Drain

More information

Enhancing DRAM Self-Refresh for Idle Power Reduction

Enhancing DRAM Self-Refresh for Idle Power Reduction Enhancing DRAM Self-Refresh for Idle Power Reduction Byoungchan Oh, Nilmini Abeyratne, Jeongseob Ahn Ronald G. Dreslinski and Trevor Mudge University of Michigan, Ann Arobr, MI 4819 {bcoh, sabeyrat, ahnjeong,

More information

A New network multiplier using modified high order encoder and optimized hybrid adder in CMOS technology

A New network multiplier using modified high order encoder and optimized hybrid adder in CMOS technology Inf. Sci. Lett. 2, No. 3, 159-164 (2013) 159 Information Sciences Letters An International Journal http://dx.doi.org/10.12785/isl/020305 A New network multiplier using modified high order encoder and optimized

More information

JDT EFFECTIVE METHOD FOR IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING FAST ADDERS

JDT EFFECTIVE METHOD FOR IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING FAST ADDERS JDT-002-2013 EFFECTIVE METHOD FOR IMPLEMENTATION OF WALLACE TREE MULTIPLIER USING FAST ADDERS E. Prakash 1, R. Raju 2, Dr.R. Varatharajan 3 1 PG Student, Department of Electronics and Communication Engineeering

More information

Superior Radar Imagery, Target Detection and Tracking SIGMA S6 RADAR PROCESSOR

Superior Radar Imagery, Target Detection and Tracking SIGMA S6 RADAR PROCESSOR Superior Radar Imagery, Target Detection and Tracking SIGMA S6 S TA N D A R D F E AT U R E S SIGMA S6 Airport Surface Movement Radar Conventional Radar Image of Sigma S6 Ice Navigator Image of Radar Inputs

More information

A Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS.

A Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS. A Novel Radiation Tolerant SRAM Design Based on Synergetic Functional Component Separation for Nanoscale CMOS. Abstract This paper presents a novel SRAM design for nanoscale CMOS. The new design addresses

More information

A Message Scheduling Scheme for All-to-all Personalized Communication on Ethernet Switched Clusters

A Message Scheduling Scheme for All-to-all Personalized Communication on Ethernet Switched Clusters A Message Scheduling Scheme for All-to-all Personalized Communication on Ethernet Switched Clusters Ahmad Faraj Xin Yuan Pitch Patarasuk Department of Computer Science, Florida State University Tallahassee,

More information

Large-scale Stability and Performance of the Ceph File System

Large-scale Stability and Performance of the Ceph File System Large-scale Stability and Performance of the Ceph File System Vault 2017 Patrick Donnelly Software Engineer 2017 March 22 Introduction to Ceph Distributed storage All components scale horizontally No single

More information

EEC 118 Lecture #12: Dynamic Logic

EEC 118 Lecture #12: Dynamic Logic EEC 118 Lecture #12: Dynamic Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Today: Alternative MOS Logic Styles Dynamic MOS Logic Circuits: Rabaey

More information

FINFET BASED SRAM DESIGN FOR LOW POWER APPLICATIONS

FINFET BASED SRAM DESIGN FOR LOW POWER APPLICATIONS FINFET BASED SRAM DESIGN FOR LOW POWER APPLICATIONS SHRUTI OZA BVU College of Engineering, Pune-43 E-mail: Shruti.oza11@gmail.com Abstract- Industry demands Low-Power and High- Performance devices now-a-days.

More information

All Digital on Chip Process Sensor Using Ratioed Inverter Based Ring Oscillator

All Digital on Chip Process Sensor Using Ratioed Inverter Based Ring Oscillator All Digital on Chip Process Sensor Using Ratioed Inverter Based Ring Oscillator 1 G. Rajesh, 2 G. Guru Prakash, 3 M.Yachendra, 4 O.Venka babu, 5 Mr. G. Kiran Kumar 1,2,3,4 Final year, B. Tech, Department

More information

Self-Aware Adaptation in FPGAbased

Self-Aware Adaptation in FPGAbased DIPARTIMENTO DI ELETTRONICA E INFORMAZIONE Self-Aware Adaptation in FPGAbased Systems IEEE FPL 2010 Filippo Siorni: filippo.sironi@dresd.org Marco Triverio: marco.triverio@dresd.org Martina Maggio: mmaggio@mit.edu

More information

Traditional analog QDC chain and Digital Pulse Processing [1]

Traditional analog QDC chain and Digital Pulse Processing [1] Giuliano Mini Viareggio April 22, 2010 Introduction The aim of this paper is to compare the energy resolution of two gamma ray spectroscopy setups based on two different acquisition chains; the first chain

More information

EE 330 Lecture 44. Digital Circuits. Dynamic Logic Circuits. Course Evaluation Reminder - All Electronic

EE 330 Lecture 44. Digital Circuits. Dynamic Logic Circuits. Course Evaluation Reminder - All Electronic EE 330 Lecture 44 Digital Circuits Dynamic Logic Circuits Course Evaluation Reminder - All Electronic Digital Building Blocks Shift Registers Sequential Logic Shift Registers (stack) Array Logic Memory

More information

A Novel Low-Power Scan Design Technique Using Supply Gating

A Novel Low-Power Scan Design Technique Using Supply Gating A Novel Low-Power Scan Design Technique Using Supply Gating S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh, and K. Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette,

More information

Online Frequency Assignment in Wireless Communication Networks

Online Frequency Assignment in Wireless Communication Networks Online Frequency Assignment in Wireless Communication Networks Francis Y.L. Chin Taikoo Chair of Engineering Chair Professor of Computer Science University of Hong Kong Joint work with Dr WT Chan, Dr Deshi

More information

2002 IEEE International Solid-State Circuits Conference 2002 IEEE

2002 IEEE International Solid-State Circuits Conference 2002 IEEE Outline 802.11a Overview Medium Access Control Design Baseband Transmitter Design Baseband Receiver Design Chip Details What is 802.11a? IEEE standard approved in September, 1999 12 20MHz channels at 5.15-5.35

More information

Enabling ECN in Multi-Service Multi-Queue Data Centers

Enabling ECN in Multi-Service Multi-Queue Data Centers Enabling ECN in Multi-Service Multi-Queue Data Centers Wei Bai, Li Chen, Kai Chen, Haitao Wu (Microsoft) SING Group @ Hong Kong University of Science and Technology 1 Background Data Centers Many services

More information