Extending NAND Endurance with Advanced Controller Technology
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1 Extending NAND Endurance with Advanced Controller Technology Wei Lin System Architect, Phison PHISON s presentation contains forward-looking statements subject to significant risks and uncertainties. Actual results may differ materially from those contained in the forward-looking statements. Information as to those factors that could cause actual results to vary can be found in PHISON s annual reports and other documents filed from time-to-time with the TWSE. Except as required by law, we undertake no obligation to update any forward-looking statement, whether as a result of new information, future events, or otherwise. Santa Clara, CA 1
2 Error Handling Tech. in Controller HRE Eliminator NAND Flash NAND I/O Interface Digital Signal Processor Reliability Information Processor DIS Processor Digital Signal Processors: Reduce Error. Collect/transfer the channel info. Vth Distribution Construction Random Noise Cancellation HRE Statistic Collection Read Level Optimization Health Monitoring Data Reconstruction Adaptive LLR Calculation Digital Signal Translation Reliability Information Scaling Firmware Flash Parameter optimization Statistical Analyzer Noise Cancellation Error Characterization Error Probability Analyzer Information Scaling Advanced Protection Firmware: Judge the info. form DSP/ECC. Adaptively control ECC engine. Adaptively control NAND Flash. Adaptively change the data Structure. ECC ECC Engine: Low Power. Low Cost. Excellent Correction Strength. Santa Clara, CA 2
3 Error Handling Tech. in Controller HRE Eliminator NAND Flash NAND I/O Interface Digital Signal Processor Reliability Information Processor DIS Processor Digital Signal Processors: Reduce Error. Collect/transfer the channel info. Vth Distribution Construction Data Reconstruction Digital Signal Translation Statistical Analyzer Error Characterization Random Noise Cancellation HRE Statistic Collection Read Level Optimization Adaptive LLR Calculation Reliability Information Scaling Noise Cancellation Error Probability Analyzer Information Scaling Firmware Health Monitoring Flash Parameter optimization Advanced Protection ECC Santa Clara, CA
4 Digital Signal Processor in Controller Monitor the health of the Data. Estimate/collect the channel information. Convert the channel information to reliability info. for ECC. Reduce the input errors (normal errors & HRE). Improve the decoding throughput. Reduce the complexity of the decoding flow. Santa Clara, CA 4
5 What s HRE? Santa Clara, CA 5
6 The Impact to the Reliability BCH LDPC Total Error Normal Error HRE Santa Clara, CA 6
7 HRE Eliminator Santa Clara, CA 7
8 Error Handling Tech. in Controller Santa Clara, CA 8
9 Adaptive Data Structure FW Area FW Area FW Area FW Area SLC SLC SLC SLC SLC SLC User Area User Area User Area User Area SLC SLC TLC SLC TLC TLC TLC SLC SLC SLC Santa Clara, CA 9
10 Error Handling Tech. in Controller Santa Clara, CA 10
11 Migration of ECC Technologies Technology (nm) 3x 3x 3x/2x 2x/1x 1x/1y 1y/1z 1z ECC/Signal BCH/Retry/L BCH/Retry/L Advanced Advanced BCH BCH BCH/Retry Processing DPC DPC DSP DSP Santa Clara, CA 11
12 Migration of ECC Technologies Technology (nm) 3x 3x 3x/2x 2x/1x 1x/1y 1y/1z 1z ECC/Signal BCH/Retry/L BCH/Retry/L Advanced Advanced BCH BCH BCH/Retry Processing DPC DPC DSP DSP MLC -> TLC -> QLC Santa Clara, CA 12
13 Migration of ECC Technologies? Technology (nm) 3x 3x 3x/2x 2x/1x 1x/1y 1y/1z 1z ECC/Signal BCH/Retry/L BCH/Retry/L Advanced Advanced BCH BCH BCH/Retry Processing DPC DPC DSP DSP MLC -> TLC -> QLC Santa Clara, CA 13
14 Even We Changed to LDPC Larger chip size. Huge power consumption. A Gap between simulation and real NAND channel on Correction capability. Weak immunity to HRE. Complex decoding flow. Santa Clara, CA 14
15 Even We Changed to LDPC Larger chip size. Huge power consumption. A Gap between simulation and real NAND channel on Correction capability. Weak immunity to HRE. Complex decoding flow. Santa Clara, CA 15
16 The Gap between NAND and Theory Santa Clara, CA 16
17 Even We Changed to LDPC Larger chip size. Huge power consumption. A Gap between simulation and real NAND channel on Correction capability. Weak immunity to HRE. Complex decoding flow. Santa Clara, CA 17
18 Weak Immunity to HRE Santa Clara, CA 18
19 Even We Changed to LDPC Larger chip size. Huge power consumption. A Gap between simulation and real NAND channel on Correction capability. Weak immunity to HRE. Complex decoding flow. Santa Clara, CA 19
20 Complex Decoding Flow N Y Y N N Y Y N Santa Clara, CA 20
21 Complex Decoding Flow N Y Y N N Y Y N Santa Clara, CA Retry LLR 21
22 A Novel ECC is Proposed Superior correction capability then BCH and the HB of LDPC. Support soft decoding. 1/3 power consumption than BCH. Same gate count as BCH. Simple decoding flow. No need to use soft bit information. Excellent HRE immunity. Santa Clara, CA 22
23 Summary A Novel ECC engine with superior correction capability is proposed for next generation NAND Flash memory. Digital signal processors are proposed to improve the system performance and reliability. Adaptive controlling technology is implemented to control the DSP/ECC/NAND/Data structure for superior reliability. Santa Clara, CA 23
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