Error Detection & Vertical LDPC ECC for Reliable 3D-TLC NAND Flash

Transcription

1 Error Detection & Vertical LDPC ECC for Reliable 3D-TLC NAND Flash Shun Suzuki, Toshiki Nakamura, Kyoji Mizoguchi and Ken Takeuchi Chuo University, Japan Santa Clara, CA 1

2 Background Outline Conventional Asymmetric Coding (AC) Low-Density Parity-Check (LDPC) Code Proposals 1 ) Error Detection (HED + V-LDPC) 2 ) Error Correction Conclusion Santa Clara, CA 2

3 Background Outline Conventional Asymmetric Coding (AC) Low-Density Parity-Check (LDPC) Code Proposals 1 ) Error Detection (HED + V-LDPC) 2 ) Error Correction Conclusion Santa Clara, CA 3

4 Conventional Asymmetric Coding (AC) Conventional Asymmetric Coding (AC) [1] Flag Add 1 Input data :1011 Add Flip Don t flip Santa Clara, CA [1] S. Tanakamaru et al., ISSCC, 2011, pp

5 Conventional Asymmetric Coding (AC) Conventional Asymmetric Coding (AC) [1] Flag Add Flip Input data : Don t flip Add 0 e.g. ) Code Length (CL) = 4 Input data : # of 1 s # of 0 s 6/12 6/12 Santa Clara, CA [1] S. Tanakamaru et al., ISSCC, 2011, pp

6 Conventional Asymmetric Coding (AC) Conventional Asymmetric Coding (AC) [1] Flag Add Flip Input data : Don t flip Add 0 e.g. ) Code Length (CL) = 4 Input data : Add a flag for increasing # of 1 s # of 0 s # of 1 s # of 0 s 6/12 6/12 10/15 > 5/15 Proportion of 0 and 1 is changed by AC Santa Clara, CA [1] S. Tanakamaru et al., ISSCC, 2011, pp

7 # of cells Conventional Asymmetric Coding (AC) Random data V TH -state : Er Upper page 0 Middle page 0 Lower page 1 (Er : Erase) A B C D E F G V TH Santa Clara, CA 7

8 # of cells # of cells V TH -state : Er Upper page 0 Middle page 0 Lower page 1 (Er : Erase) Conventional Asymmetric Coding (AC) Random data A B C D E F G V TH V TH Er A B C D E F G Encode AC7 Page Increased data Upper page 1 Middle page 1 Lower page 1 Increase Er-state cells : AC1 Increase A-state cells : AC2 Increase G-state : cells : AC8 : Santa Clara, CA 8

9 Measured BER (a.u.) Conventional Asymmetric Coding (AC) AC7 decreases BER mostly in 3D-TLC NAND flash 3D-TLC NAND flash, N W/E = 1, N CL = 15 AC1 AC AC7 is optimal coding Data-retention time (day) AC3 AC4 AC5 AC6 AC7 AC8 Random Santa Clara, CA 9

10 Background Outline Conventional Asymmetric Coding (AC) Low-Density Parity-Check (LDPC) Code Proposals 1 ) Error Detection (HED + V-LDPC) 2 ) Error Correction Conclusion Santa Clara, CA 10

11 Low-Density Parity-Check (LDPC) Code Decoding flowchart Read data Predict BER (by AEP-LDPC w/o upper lower cells [1]) Calculate LLR Decode data Santa Clara, CA [1] T. Tokutomi et al., IMW, 2014, pp

12 Low-Density Parity-Check (LDPC) Code Decoding flowchart Read data Predict BER (by AEP-LDPC w/o upper lower cells [1]) Calculate LLR 3D NAND flash Read Decode data Santa Clara, CA [1] T. Tokutomi et al., IMW, 2014, pp

13 Low-Density Parity-Check (LDPC) Code Decoding flowchart Read data Predict BER (by AEP-LDPC w/o upper lower cells [1]) Calculate LLR 3D NAND flash Read Predicted BER is 2.0% based on BER table (shown in next slide) Decode data Santa Clara, CA [1] T. Tokutomi et al., IMW, 2014, pp

14 Low-Density Parity-Check (LDPC) Code Decoding flowchart Read data Predict BER (by AEP-LDPC w/o upper lower cells [1]) Calculate LLR Decode data 3D NAND flash Read Predicted BER is 2.0% based on BER table (shown in next slide) Likely to be Predicted BER LLR(0) = ln 1 BER BER, LLR(1) = ln BER 1 BER (LLR : Log-likelihood ratio) Santa Clara, CA [1] T. Tokutomi et al., IMW, 2014, pp # of cells V REF High BER Likely to be 0 Bit should be error V TH LLR

15 Low-Density Parity-Check (LDPC) Code Decoding flowchart Read data Predict BER (by AEP-LDPC w/o upper lower cells [1]) Calculate LLR Decode data 3D NAND flash Read Predicted BER is 2.0% based on BER table (shown in next slide) Likely to be Predicted BER LLR(0) = ln 1 BER BER, LLR(1) = ln BER 1 BER (LLR : Log-likelihood ratio) LDPC corrects errors by using LLR Santa Clara, CA [1] T. Tokutomi et al., IMW, 2014, pp # of cells V REF High BER Likely to be 0 Bit should be error V TH LLR

16 AEP-LDPC w/o upper lower cells BER prediction method AEP-LDPC w/o upper lower cells [1] BER table V TH -state Erase A G Page page state Upper BER UEr BER UA BER UG Middle BER MEr BER MA BER MG Lower BER LEr BER LA BER LG Santa Clara, CA [1] T. Tokutomi et al., IMW, 2014, pp

17 AEP-LDPC w/o upper lower cells BER prediction method AEP-LDPC w/o upper lower cells [1] BER table e.g. ) Read data Which page? 0011 Lower page 0011 Page V TH -state Erase A G page state Upper BER UEr BER UA BER UG Middle BER MEr BER MA BER MG Lower BER LEr BER LA BER LG Which state? C A E Predicted BER is BER LA Santa Clara, CA [1] T. Tokutomi et al., IMW, 2014, pp G

18 Concept of this work Conventional AEP-LDPC w/o upper lower cells can not correct errors because predicted BER is too small Predicted BER % 0.12% 0.11% % 0.09% Santa Clara, CA Conv. LDPC : AC code unit Error include in these bits Which bit is error?? Error information is poor 18

19 Decode of iterations Santa Clara, CA Concept of this work If error bits have large predicted BER, LDPC corrects errors effectively Simulation, Max iteration of LDPC = Errors are correctable with fewer Predicted 15 iterations of LDPC decoding BER 0.1% % Error bit 5 Error bit Error bit is more Predicted BER of error bits (%) correctable 19

20 Santa Clara, CA Concept of this work In our work, proposed Error Detection detects errors based on AC algorithm Predicted BER Proposed Error Detection gets to know : 1This AC code unit includes error bit 2Error exists in 0 s of this unit 0.10% 0.12% 0.11% 1 Proposed Error Detection Detect that at least one error exists in 0 s % 0.09% 20

21 Santa Clara, CA % 0.12% 37% Concept of this work Our proposed Error Correction intentionally increases predicted BER of detected bits LDPC ECC effectively corrects errors Predicted BER Emphasize % 0.12% 0.11% % 0.09% Proposed Error Correction Emphasize predicted BER % 30% 21

22 Background Outline Conventional Asymmetric Coding (AC) Low-Density Parity-Check (LDPC) Code Proposals 1 ) Error Detection (HED + V-LDPC) 2 ) Error Correction Conclusion Santa Clara, CA 22

23 Concept of Proposed Error Detection Proposed Error Detection 1Horizontal Error detection (HED) Proposed HED detects AC code unit including error bit 2Vertical-LDPC (V-LDPC) Proposed V-LDPC averages detected errors among decode units of LDPC Error detection information is used for proposed Error Correction Santa Clara, CA 23

24 Proposed Error Detection 1Horizontal Error Detection (HED) HED detects AC code unit including error bit Encoded AC data 1 s> 0 s Code unit of AC 1 s> 0 s 1 s> 0 s 1 s> 0 s Santa Clara, CA 24

25 Proposed Error Detection 1Horizontal Error Detection (HED) HED detects AC code unit including error bit Encoded AC data 1 s> 0 s Code unit of AC 1 s> 0 s s> 0 s 1 s> 0 s 1 s> 0 s s> 0 s 1 s < 0 s 1 s> 0 s Error Santa Clara, CA 25

26 Encoded AC data Proposed Error Detection 1Horizontal Error Detection (HED) HED detects AC code unit including error bit 1 s> 0 s Code unit of AC 1 s> 0 s s> 0 s 1 s> 0 s 1 s> 0 s Error Detection Santa Clara, CA 26 HED detects that this code unit includes errors 1 s> 0 s 1 s < 0 s 1 s> 0 s At least one error exists in 0 s

27 Detected error rate Measured BER (a.u.) Proposed Error Detection ~Result of HED~ 3D-TLC NAND flash, N CL = 8, N W/E = 400, Upper page Middle page Lower page Detected error rate of upper page is low 1 BER of upper page is high Data-retention time (day) Data-retention time (day) Santa Clara, CA 27

28 Conventional LDPC ECC order Upper Middle Lower Proposed V-LDPC order Upper Middle Lower : Encode/decode unit Proposed Error Detection 2Vertical-LDPC (V-LDPC) Santa Clara, CA 28

29 Conventional LDPC ECC order Upper Middle Lower Proposed V-LDPC order Upper Middle Lower : Encode/decode unit Proposed Error Detection 2Vertical-LDPC (V-LDPC) e.g.) Upper Middle Lower Conv. LDPC Errors Detected errors by HED Prop. V-LDPC Unit 1 Unit 2 Unit 3 Detected errors are dispersed among decode units Santa Clara, CA 29

30 # of detected errors (a.u.) Proposed V-LDPC, N W/E = 1, N CL = Proposed Error Detection ~Result of V-LDPC~ Unit 1 Unit 2 Unit Data-retention time (day) Proposed V-LDPC order Unit 1 Unit 2 Unit 3 All units have almost same number of detected errors Santa Clara, CA 30

31 Background Outline Conventional Asymmetric Coding (AC) Low-Density Parity-Check (LDPC) Code Proposals 1 ) Error Detection (HED + V-LDPC) 2 ) Error Correction Conclusion Santa Clara, CA 31

32 Proposed Error Correction Emphasize predicted BER of detected bits Detected AC code unit 0.2% 0.3% 0.2% 0.5% 0.1% (e.g.) Predicted BER by HED detects that AEP-LDPC w/o at least one error exists in 0 s upper lower cells Santa Clara, CA 32

33 Proposed Error Correction Emphasize predicted BER of detected bits Detected AC code unit 0.2% 0.3% 0.2% 0.5% 0.1% Obtain ratio 2 : 3 : 5 20% 30% 50% Total 100% (1 bit error) Santa Clara, CA 33

34 Update Proposed Error Correction Emphasize predicted BER of detected bits Detected AC code unit 0.2% 0.3% 0.2% 0.5% 0.1% Obtain ratio 2 : 3 : 5 20% 30% 50% Total 100% (1 bit error) Updated BER % 30% 0.2% 50% 0.1% Santa Clara, CA 34

35 Data-retention time (day) Data-retention time (day) Result of Prop. Error Detection & Correction N CL = 8, Max iteration = 30, Conventional AEP-LDPC Proposed Error w/o upper lower cells Detection & Correction Fail 6.1 N W/E Fail Numbers in blue frames show number of iterations Santa Clara, CA 35 N W/E

36 Acceptable BER (a.u.) Decode of iterations (cycles) 2 1 Result of Prop. Error Detection & Correction Conv. AEP-LDPC w/o upper lower cells Prop. Error Detection & Correction 3D-TLC NAND flash, N CL = 8, N W/E = 300, Max iteration = 30, +90% 0 Conv. AEP-LDPC w/o upper lower cells Proposed Error Detection & Correction % Data-retention time (day) 36

37 Background Outline Conventional Asymmetric Coding (AC) Low-Density Parity-Check (LDPC) Code Proposals 1 ) Error Detection (HED + V-LDPC) 2 ) Error Correction Conclusion Santa Clara, CA 37

38 Conclusion Proposed techniques 1Error Detection (HED + V-LDPC) HED detects errors and V-LDPC averages detected errors 2Error Correction LLR values of detected error bits are emphasized Conv. LDPC ECC Prop. Error Detection & Correction Acceptable BER Baseline +90% Acceptable dataretention time Baseline +230% Santa Clara, CA 38

39 Thank you for your attention This work was partially supported by JST CREST Grant Number JPMJCR1532, Japan. Santa Clara, CA 39