Implementation of Block Turbo Codes for High Speed Communication Systems

Transcription

1 ASS 2004 Implementation of Block Turbo Codes for High Speed Communication Systems 21 September 2004 Digital Broadcasting Research Division, ETRI Sunheui Ryoo, Sooyoung Kim, and Do Seob Ahn 1

2 Needs of high speed codec for wireless communication systems New standard for wireless communications - Broadcasting and mobile systems converge to seamless network as well as moving towards closer, mutually beneficial interworking. - These systems include networks with multimode, multiband, and multimedia high capacity mobile terminal. - Such future systems should be able to fulfill the stringent requirements for quality of service (QoS), mainly in terms of throughput, delay and error rate. Needs of high speed block turbo codec - any current research activates in the field of wireless communication system are focusing on finding the powerful channel codes - not only with the excellent error correction capability - but also with the practical implementation complexity. 2

3 Block turbo codes Turbo codes -After turbo codes are first introduced, they have been widely studied for their outstanding performance close to the Shannon limit. - Soon after, Pyndiah introduced Block Turbo Codes, and there have been many presentations on H/W implementations. - Some recent implementation results showed that its speed can cope with even fiber-optic applications. Efficient block turbo codes implemented in FPGA level - However their implementations are all based on algebraic decoding algorithms. - On the other hand, our block turbo codes used trellis decoding algorithms which have inherent soft input soft output (SISO) decoding capability. - By using this, we can provide an efficient iterative decoding algorithm and the high performance. 3

4 Block turbo codes - construction Encoding of multi-dimensional turbo codes - The concept of block turbo codes allows us to construct powerful codes by using the systematic linear block codes. -An m dimensional block turbo codes are theoretically possible for m larger than 2. - We construct an m dimensional block turbo code using the component BCH codes with parameters (n 1, k 1 ), (n 2, k 2 ),, and (n m, k m ) -wheren i, and k i stand for codeword length and information word length. - The parameters of the m dimensional block turbo codes are given by n = n 1 n 2 nm, k = k 1 k 2 k m, and the code rate R is given by R = R 1 R 2 R m n k information row parity column parity 4

5 Block turbo codes - decoding Soft output decoding algorithm - To compensate for the inferior performance of the SOVA compared to the more complex AP algorithm with several performance improvement techniques. - We decoded block turbo codes iteratively on each axis using soft output information from the decoding on the other axes. Soft output decoding algorithm info rmatio n ro w pa rity n2 Soft output decoding algorithm column parity 5

6 Block turbo codes - component codes Expurgated BCH codes - 2D and 3D block turbo codes is implemented - Below table shows their component code, code rate, and bit energy to noise spectral density ratio (E b /N 0 ) to achieve a bit error rate of An uncoded BPSK scheme requires about 10 db to achieve a BER of The block turbo code is able to produce a coding gain of from 6.2 db up to 8.5 db depending on the component codes and the dimension of block turbo codes Code Dimension Component BCH (n, k) Code rate SNR@BER 10-6 A 2 (31,25) db B 2 (63,56) db C 3 (15,10) db 6

7 Decoder - component Parallel decoding with line - Block turbo consist of m component - Each component consist of independent line - Parallel line decoding can be executed simultaneously. L(r) r Component (r) L e Soft_ d d Turbo product L(r) r Line 0 (r) L e Soft_ d d Line 1... Line N control signal FS & Control part 7

8 Decoder - line Sub block of line and parameter bit precision Line L(r) r 8 bit 6 bit ACS CRU scale Trunc 8 bit 10 bit 1 bit (r) L e Soft_ d d FS & Control part r L e (r) Soft_d d Signal Information received from the channel Extrinsic information Soft decision result of decoding Hard decision result of decoding Precision 6 bit 8 bit 10 bit 1 bit 8

9 emory structure 2, 3D memory - Using the block memory core in Xilinx chip - Repeating the writing and reading operation Channel reliability Block memory1 Block memory x-axis decoding Component Reliability Pipe Converting to y-axis y-axis decoding Component Reliability Pipe Converting to z-axis z-axis decoding Component Reliability Pipe Converting to x-axis 9

10 Implementation Results Operation speed on the HES board - We implemented block turbo codes using FPGA chip of HES Xilinx XC2V The shaded cells present a single chip implementation. - The parallel line decoding reduces the total decoding time - Block memory architecture accelerates the clock speed. Block turbo code # of Line Critical Path clk frequency clk/line Decode /plane Total clk Data Rate /iteration A (2D) 8 16 ns 65 Hz 69 clk clk 73 bps ns 65 Hz 69 clk clk 292 bps B (2D) 8 18 ns 57 Hz 133 clk 8 2,128 clk 84 bps ns 57 Hz 133 clk clk 627 bps C (3D) 8 20 ns 49 Hz 37 clk 30 3,330 clk 15 bps ns 53 Hz 37 clk 15 1,665 clk 32 bps ns 54 Hz 37 clk clk 480 bps 10

11 Conclusion Implementation of high speed block turbo codec - This paper introduces our efficient implementation method of block turbo codes and shows the emulation results. - We used a trellis based decoding algorithm for block turbo codes, and implemented 2D and 3D block codes in FPGA level. - We applied various efficient algorithms to enhance the performance. - The implementation of line s in parallel improves the decoding speed with N times. - The block memory structure remarkably reduces the critical path and thus achieves high speed decoding. 11