High-Rate Non-Binary Product Codes

Transcription

1 High-Rate Non-Binary Product Codes Farzad Ghayour, Fambirai Takawira and Hongjun Xu School of Electrical, Electronic and Computer Engineering University of KwaZulu-Natal, P. O. Box 4041, Durban, South Africa Tel: , Fax: {ghayour, ftakaw, Abstract-Research has shown that random codes with long block length are more likely to approach the channel capacity. One approach for designing a long length code with reasonable complexity is to combine two or more short length codes with each other. In this paper we are investigating on non-binary product codes which are constructed from combination of two nonbinary single parity-check (SPC) codes as their component codes. Designing a high-rate code with this method is feasible and it can be done by tending the length of the code towards infinity. The construction and decoding of a non-binary SPC product codes when the SPC codes are defined over a finite field of order q, as well as when they are defined over an integer residue ring of order q is studied and the simulation results is represented. Index Terms Product codes, non-binary codes over ring, single parity-check (SPC) codes I. INTRODUCTION Shannon in [1] showed that random codes with long block length are more likely to approach the channel capacity. Although codes with longer length are performing better, but their decoding complexity will also increase according to their length. One approach for designing a long length code with reasonable complexity is to combine two or more short length codes with each other and generate a code with longer block size. Decoding complexity can be reduced by separately decoding of the component codes and the performance of a combined code can get better by implementing an iterative decoding scheme between its component codes. The idea of combining codes is dating back to the invention of product codes by Elias in 1954 [2]. He showed that these codes are capable of achieving an error-free coding scheme. This has been done by tending the dimensions of a product code towards infinity. Since then, many error correcting codes based on product constructions have been suggested. Product codes can be constructed as binary codes or as non-binary ones. Binary product codes can be constructed by using binary component codes, for example by using BCH codes as their component codes. Non-binary product codes can be constructed by combining non-binary codes with each other, for example by combining Reed-Solomon codes. It is also possible to combine a binary code with a non-binary code and construct a hybrid product code. Product codes are efficient for controlling both randomerror and burst-error patterns [3]. Also they have been suggested for applications where high-rate coding schemes are required, such as submarine cables, optical transport network, and networks at 100Gbit/sec [4]. In these applications code rates greater than 0.9 is required. A simple product code can be constructed by combining single parity check (SPC) codes with each other. SPC codes are algebraic simple codes with high coding rate and relatively weak performance. It has been shown in [5], [6], [7] and [8] that good performance codes can be constructed by combining SPC codes with each other. The work in [5] studied binary SPC multidimensional product codes and it has been shown that these codes can have good performance under the iterative decoding. In [6], it has been studied that by combining binary SPC codes in serial or parallel concatenation manner, good performance codes can be produced and the simulation results have shown that binary SPC concatenated codes can outperform 16-states turbo codes. In [7], an improved new structure of binary SPC product codes with an embedded interleaver was proposed. Recently the work in [8] has shown that a product code constructed from extended binary SPC codes with length of and rate of is only 0.44 db away from the Shannon limit at a BER of Majority of researches which have been made on SPC product codes are on binary SPC product codes. In this paper we are investigating on non-binary product codes which are constructed from combination of two non-binary SPC codes as their component codes. Non-binary codes can be defined over a finite field of order q or over a ring of order q. Decoding of non-binary SPC codes when the SPC codes have been defined over a finite field of order q and codewords have been transmitted over a discrete memoryless channel (DMC) has been studied in [9]. Due to usage of DMC, for different field order, different channel have been used and performances of the codes for different field orders did not compare to each other.

2 In this paper we study the construction and decoding of non-binary SPC product codes when SPC codes are defined over a finite field of order q, as well as when they are defined over an integer residue ring of order q. In this paper, codewords are transmitted over an additive white Gaussian noise (AWGN) channel and codes performances for different field and ring orders are compared with each other. It is well known that for a prime number p, and a positive integer n, a finite field with q=p n elements exists. This finite field can be shown by. Also for any positive integer number q, a ring of integer residue q exists which it can be shown by. It is also well known that for a prime number q,. employed in dimension. This product code is denoted by (N,K,d min ) q. Two-dimensional (2-D) product code, as it is depicted in Fig. 1, is consisted of a data block, a set of parity-check symbols on each row, a set of parity-check symbols on each column, and a set of parity-check symbols on the paritychecks. The rest of the paper is organizes as follows. In Section II structure of non-binary product codes for both and is presented. In Section III decoding algorithm for non-binary SPC codes is discussed. In Section IV the simulation results are presented. Finally in Section V conclusion for this paper is given. II. STRUCTURE OF PRODUCT CODE In General, a product code defined over or is constructed as follows. The message sequence is arranged in a hypercube of dimension λ, with {k 1, k 2, k 3,, k λ } symbols in each dimension and each symbol belongs to set. It is obvious that the total numbers of message symbols are equal to Fig. 1: A general structure for a twodimensional product code In this paper we consider product codes formed by single parity check (SPC) codes. This means that every row and column of data has only one parity-check symbol. A twodimensional example of such code is shown in Fig. 2. Each dimension is encoded with a systematic code of C i which is defined over or, depending the product code is defined over a finite field or over a ring, and it is generating a codeword of length n i. This process is repeated for all dimensions. The resulting λ dimensional product code has the block length of Information Parity Fig. 2: The structure of a 2-D SPC product code and the code rate is equal to The code rate of λ dimensional SPC product code is equal to Where r i is the rate of the code in the i-th dimension. It can be proved that the minimum distance of a product code is equal to where is the minimum distance of the component code As it is seen, designing a high-rate code is feasible by tending n towards infinity. Non-binary SPC product codes can be considered as an error correcting code for the applications where high code rate, non-binary codes are required. In this paper we are introducing two different approaches for constructing nonbinary SPC product codes. In the first approach, the component non-binary SPC codes are defined over, and in the second approach the component non-binary SPC

3 codes are defined over integer residue ring of order q,. A. Non-binary SPC Product Codes over Let us assume a two-dimensional product code with SPC codes as its component code. This code is depicted in Fig. 3. U 1,1 U 1,2 U 1,3 U 2,1 U 2,2 U 2,3 U 3,1 U 3,2 U 3,3 U n-1,1 U n-1,2 U n-1,3 P 1 P 2 P 3 Fig. 3: Two-dimensional SPC product code and they belong to set symbols are P 1 P 2 P 3 P n-1 P n are message symbols. Row parity-check and column parity-check symbols are and they have been selected in a way so that the parity-check equations given in (6) and (7) are being satisfied. III. DECODING Maximum a posteriori (MAP) decoding of product codes is usually computationally infeasible. This is due to the large length of the product codes. This complexity even applies more when the length of the component code and the field order which the component codes have been defined over are increasing. For reducing the decoding complexity in product codes, an iterative decoding algorithm based on soft-input soft-output (SISO) decoding of the component codes is usually employed. In this section a decoding algorithm for the non-binary product codes is introduced. In this algorithm we are using a MAP decoder for each of the component codes. In each decoding cycle or iteration the information between the vertical and horizontal parity-check equations are being exchanged. We derive the formula for two-dimensional SPC code but it can be easily extended to the SPC codes with greater dimensions. Let us consider the two-dimensional product code in the Fig. 3. Regardless of the fact that the SPC codes have been defined over or they have been defined over, are the symbols belong to the set. We assume that the code symbols are mapped into the binary sequences and transmitted over a binary input AWGN channel by using binary phase-shift keying BPSK modulation. For, all the symbols can be mapped into the binary sequence of length p as it is shown in (10). is the addition operation over. The binary sequences are then modulated with BPSK modulation scheme and are mapped into a bipolar sequences as it is shown in (11) B. Non-binary SPC Product Codes over Let us again assume the two-dimensional product code which was depicted in Fig. 3. This time the SPC codes are defined over. This means that are message symbols and they are belong to set. Row parity-check symbols are and column parity-checks symbols are and they have been selected in a way so that the parity-check equations given in (8) and (9) are being satisfied. where and. At the receiver side we have the received vector Y = where and is the noise symbol correspondent to each transmitted codeword symbol. are zero-mean Gaussian random variables with variance which they are independent from each other as well as from transmitted symbols. Based on the MAP decision rule we have is the addition operation over This is equivalent to (14) and (15) in the bottom of the page. From the row parity-check equation we have (14) and from

4 BER column parity check equation we have (15), where An iterative decoding algorithm can be implemented as it is shown in Fig. 4. This algorithm is given below. Initialization: The channel likelihood ratios for all the received symbols should be calculated as addition defined over which is a bit-wise operation. For the SPC product codes defined over the performance of the code is getting improvement by increasing the order of the field as depicted in Fig 5. As it is mentioned before. This means that for the nonbinary SPC product codes defined over the upper bound will be equal to the upper bound of binary SPC product code. Decoding each dimension: Based on the likelihood ratio value and from (14) and (15) the extrinsic information for all the symbols in every SPC component code should be calculated q=16 q=64 Theoritical Upper-Bound q=2 Message passing: Only the extrinsic information is passed between the decoders Step 2 and 3 should be repeated as long as required Channel Values Eb/N0[dB] Row Code Decoder Column Code Decoder Soft Output Fig. 5: Performance of the (9,4) family of SPC product code defend over the ring of integer mod q Fig. 4: Soft-in Soft-out Decoder The bound can be found in [7] and is equal to IV. NUMERICAL RESULTS In this paper we compare the performance of the product codes resulted from combining different order of non-binary SPC codes. Although for transmitting non-binary symbols, higher-order modulation can be used, but in this paper all the codes are compared under the same conditions. This means that all the codewords are transmitted over the same channel by using the same modulation scheme. Due to this fact, we consider that all the non-binary symbols are mapped into the binary sequences prior to transmission. These binary sequences are then modulated with BPSK scheme and are transmitted over an AWGN channel. Mapping of the symbols into the bits may cost bandwidth inefficiency for the special cases of q where. For the SPC product codes defined over the performance of the code is independent from the order of the field. In the other word the performance of the binary SPC codes defined over is similar to the performance of the non-binary SPC codes defined over. This is due to the fact that the parity symbol in SPC codes is resulted from where n is the length of the code. As it is shown in Fig. 5 by increasing the order of the ring from to a 0.5dB gain is achieved and by increasing to a 0.7dB gain is achieved. Based on this approach and by defining longer SPC codes over greater rings, designing the high-rate codes with good performance will be possible. V. CONCLUSION In this paper we introduced two different approaches for construction of a non-binary SPC product codes. In the first approach, the component non-binary SPC codes are defined over a finite field of order q, and in second approach the component non-binary SPC codes are defined over the ring of integer mod q. It has been shown that for the non-binary SPC codes defined over, the performance of the codes are independent from the order of the field and the nonbinary codes have similar performance to the binary ones. If

5 the SPC codes have been defined over the ring of integer mod q, then the performance of the codes is getting improvement by increasing the order of ring. Based on this approach and by defining longer SPC codes over greater rings, designing the high-rate codes with good performance will be possible. REFERENCES [1] C. E. Shannon, A Mathematical Theory of Communication, Bell Syst. Tech. J., Vol. 27, pp , [2] P. Elias, Error free coding,. IRE Trans. Inform. Theory, vol. 4, pp.29-37, Sept [3] H. Burton, E. Weldon, Jr., Cyclic Product Codes, IEEE Trans on Inform Theory, Vol. 11, pp , July [4] J. Justesen, Performance of Product Codes and Related Structures with Iterated Decoding, IEEE Trans on Commun, vol. 59, pp , Feb [5] D. M. Rankin, T. A. Gulliver, Single Prity Check Product Codes, IEEE Trans on Commun, vol. 49, pp , Aug [6] J. S. K. Tee, D. P. Taylor, P. A. Martin, Multiple Serial and Parallel Concatenated Single Parity-Check Codes, IEEE Trans on Commun, vol. 51, pp , Oct [7] H. Xu, F. Takawira, A New Structure of Single Parity Check Product Codes, SAIEE Africa Research Journal, vol.97, No.2, pp , June [8] A. Shiozaki, M. Kishimoto and G. Maruoka, Close-to-capacity performance of extended single prity check product codes, Eletronics Letters, vol.47, pp , Jan [9] M. Caldera, H. J. Zepernick, APP Decoding of Nonbinary SPC Product Codes over Discrete Memoryless Channels, 10 th International Conference on Telecommunication, ICT2003, vol. 2, pp , Farzad Ghayour received the BSc and MSc degree in electronic engineering from the Isfahan University of technology, Isfahan, Iran in 2002 and 2006, respectively. He is currently working towards the PhD degree in electronic engineering at the University of KwaZulu-Natal. His research interests include information theory and error control coding for wireless communication systems.