TABLE OF CONTENTS CHAPTER TITLE PAGE

Transcription

1 TABLE OF CONTENTS CHAPTER TITLE PAGE DECLARATION ACKNOWLEDGEMENT ABSTRACT ABSTRAK TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES LIST OF ABBREVIATIONS i i i i i iv v vi ix xi xiv 1 INTRODUCTION Background Problem Description Project Objectives Scope of Project Proposed Methodology Outline of the Thesis 8

2 2 LITERATURE REVIEW Mobile systems-gprs and EDGE Wimax Systems Viterbi Compiler by Altera MFDA (Modified Feedback Decoding Algorithm) Other types of Adaptive Viterbi Algorithms New Developments in Adaptive Coding 21 3 THEORY Channel Models Multipath fading channel Methods to reduce the effects of fading Combating Distortion Combating Loss in SNR Convolutional Codes / Viterbi Decoder Encoder Structure Generator representation Tree Diagram representation State Diagram representation Trellis Diagram representation Convolutional Decoding Puncturing and Depuncturing Fire Codes Reed Solomon Codes 41 4 DESIGN METHODOLOGY Introduction Target FPGA description Implementation Flow Diagram RTL Architecture Shared methodology for the Viterbi Decoder 52

3 4.5.1 BMC unit description ACS unit description Trace Back Unit / Survivor Memory 65 5 RESULTS Overview Approach in selecting candidate configuration Algorithm / Matlab results Viterbi Performance Trace back length determination RTL results Test method Timing results Functional coverage FPGA results FPGA configuration FPGA system simulation 86 6 CONCLUSIONS AND RECOMMENDATIONS Conclusion and Recommendations Recommendation for Future Work 91 REFERENCES 92 Appendix A-B

4 LIST OF TABLES TABLE NO. TITLE PAGE 2.1 Coding schemes in GPRS Coding Schemes in EGPRS Brief Summary of the Code Sets Conventional Bit Metric Values Input / Output signal for top level Viterbi 49 Decoder 4.2 Input / Output signal for Viterbi_BMC block 50 (Branch Metric Calculator) 4.3 Input / Output signal for Viterbi_ACS block 50 (Add Compare Select) 4.4 Input / Output signal for Viterbi_MEM block (Memory) 51

5 4.5 Input / Output signal for Viterbi_traceback 51 block (Traceback) 4.6 Input / Output signal for Viterbi_filo block 51 (First In-Last Out) 4.7 Generator Polynomial of the various Standards 52 and its similarity 4.8 State Table of Constraint length 3 encoder of 53 polynomial G[7,5]. 4.9 State Table of Constraint length 4 encoder of 54 polynomial G[15,11] Rate 1/2 BMC calculation Rate 1/3 BMC calculation Pipelined structure of the BMC formula Test Methodology Legend explanation Summary of the plots in Figure 5.1,5.2 and PER values of packet size N=500 and N= respectively 5.4 Statement coverage and Branch coverage from 84 Modelsim 5.6 Summary of APEX20K200E features LE used in the adaptive Viterbi design 86

6 LIST OF FIGURES FIGURE NO. TITLE PAGE 1.1 Tx Rx modules Conventional method for GPRS and EDGE Shared Hardware approach GPRS and 7 EDGE 1.4 Internal Viterbi blocks Convolutional encoder constraint length 7 12 and rate ½ 2.2 BTC and shortened BTC codes CTC encoder Configurability of the Viterbi on Altera s MegaCore 15

7 2.5 Block diagram of a MFD Channel Modeling The Three major performance categories in 26 terms of BER vs EB/No. 3.3 Methods of Mitigating Frequency selective 27 and Fast Fading. 3.4 Methods to combat loss in SNR General structure of convolutional encoder K=3, r = ½, m=2 convolutional encoder Tree diagram representation for four input bit 32 intervals 3.8 State machine of the convolutional encoder 33 in figure Trellis diagram of the encoder of figure Trellis path for the input sequence of x = 35 {1,0,1,1} 3.11 Soft Decision and Hard Decision example Convolution Encoder + Viterbi decoder 37 system 3.13 BSC Channel, where p is the crossover probability System showing puncturing and 40 depuncturing blocks 3.15 Example of data structure after puncturing Example of data structure after depuncturing FPGA integration Flow Diagram of Viterbi Decoder Behavioral structure of the branch metric 45 computation 4.4 Behavioral structure of the Add Compare 46 Select unit 4.5 FSM structure of the Traceback unit Top Level RTL Architecture of Viterbi 48

8 Decoder 4.7 Viterbi Flow Structure Trellis Diagram for a constraint length 3 over 55 1 time period 4.9 Trellis diagram for constraint length 4 and 3 56 over 1 time period 4.10 Branch Metric Unit a Trellis of K=3, 4 states b Trellis structure for K=4, 8 states ACS Unit ACS units showing the shared multiplexer Sample Merging Paths and its selection Numerical Example of how the ACS works Memory structure for a traceback length of BER under AWGN channel BER under fast fading with AWGN channel BER under Slow fading with AWGN 71 channel 5.4 Simulation curve of 3 different convolutional 73 encoder 5.5 BER of various traceback length MCS9 P BLER of various traceback length MCS9 P Functional RTL test methodology Timing Diagram showing the Code Rate 1/2 78 input mechanism 5.9 Timing Diagram showing the Code Rate 1/3 78 input mechanism 5.10 Timing diagram for configuration of K=5, 79 rate ½ 5.11 Timing diagram for configuration of K=7, 79 rate ½ 5.12 Timing diagram for configuration of K=7, 80

9 rate 1/ Timing diagram of the BMC block Timing diagram of the ACS block Timing diagram of the Memory block Timing diagram of the Trace Back Block Timing diagram of the FILO Block FPGA simulation setup HyperTerminal settings 88 LIST OF ABBREVIATIONS GPRS - General Packet Radio Service EDGE - Enhanced Data Rates for GSM Evolution 3G - Third Generation WiMAX - Worldwide Interoperability for Microwave Access MIPS - Millions of Instructions per Second DSP - Digital Signal Processor FPGA - Field Programmable Gate Array BPSK - Binary Phase Shift Keying TX - Transmitter RX - Receiver FEC - Forward Error Control BER - Bit-Error Rate

10 Eb/No - Energy per Bit over Spectral Noise Density SNR - Signal to Noise Ratio CRC - Cyclic Redundancy Check WLAN - Wireless Local Area Network GSM - Global System for Mobile communication EGPRS - Enhanced GPRS TB-CC - Tail Biting Convolutional Codes BTC - Block Turbo Codes CTC - Convolutional Turbo Codes LDPCC - Low Density Parity Check Codes ZT-CC - Zero Tail Convolutional Code OFDM - Orthogonal Frequency Division Multiplexing OFDM A - Orthogonal Frequency Division Multiplexing Access RS - Reed Solomon CS - Coding Scheme MCS - Modulation Coding Scheme BCH codes - Bose-Chauduri-Hocquenghem codes GF - Galois Field XOR - Exclusive OR CPLD - Complex Programming Logic Device JTAG - Joint Test-Action Group ROM - Read Only Memory RAM - Random Access Memory PSK - Phase Shift Keying GMSK - Gaussian Minimum Shift keying TDD - Time Division Muliplexing FDD - Frequency Division Muliplexing BPS - bits per second MFDA - Modified Feed back Decoding Algorithm FDA - Feed Back Decoding BSC - Binary Symmetric Channel TB - Trace Back