A Modular Approach to the Design of the Soft Output Viterbi Algorithm (SOVA) Decoder

Transcription

1 A Modular Approach to the Design of the Soft Output Viterbi Algorithm (SOVA) Decoder Jacques Martinet and Paul Fortier Département de génie électrique et de génie informatique Université Laval, Sainte-Foy (Québec) G1K 7P { martinet, fortier }@gel.ulaval.ca IP Block 9 1

2 Abstract The SOVA (Soft Output Viterbi Algorithm) is used in the decoding of convolutional codes [1]. Our objective is to realize an FPGA implementation of a decoder with quantified (i.e. multi-bit) inputs that is completely parallel, using a hypercube based architecture. The longer the constraint length, K, (i.e. the amount of memory cells) of the encoder, the more powerful the code is. However, the complexity of the decoder increases exponentially with K. If we use a modular approach, we can distribute the computational effort on several FPGA circuits []. Also, a modular architecture can be scalable, i.e. blocks can be reused on decoders corresponding to different values of K. Using VHDL and a top-down approach, we have tried to make our design generic and re-usable. With a parametrized description, it is possible to obtain a compromise between bit error rate performance, the complexity of the circuit and the execution speed, just by changing the parameters and re-synthesizing the code. These compromises help us in making the right choices for the architecture of the different components of the circuits []. The problem is to find a generic procedure to decompose the SOVA based decoder while minimizing the number of interconnections between the FPGA circuits. Also, as K increases, the ACS modules dominates the overall complexity of the circuit. The SOVA decoder is decomposed in several modules, each containing ACS processors, a unit to compute the maximum value between accumulations at each iteration, a delay line of length L information bits containing the differences between the accumulations, and an I/O multiplexer unit to control the data flow between the FPGA circuits and between the ACS modules inside an FPGA chip. In addition to the ACS modules, we need a control module for the hypercube paths between the ACS modules. This control module takes the trace-back bits from each ACS processor and feeds them to the trace-back module. It also gets the maximum value from each ACS module to compute an overall maximum value. Finally, among all the outputs of the delay lines, it obtains the one from the current path and gives it to the unit that revises the quantified output. Our final goal is to use two SOVA decoders to realize a turbo decoder.

3 Convolutional encoding : A powerful error correcting scheme Binary Info + + X Y code transmitted code Generator matrix : G = [ 1 1 1, 1 1] Code Rate : Tx = 1/n = 1/ Recursive Systematic Convolutional Encoder + code 1 [X Y] Encoder State Constraint length : K = 3 3

4 Decoding of convolutional codes with the Viterbi Algorithm [1] Principe : For each step and for each node of the trellis, path merges. Of these paths, only one is kept, the one with the highest cumulative metric, ( the most likely one ) => maximum likelyhood detector. Time State State 1 State 1 State 11 Trellis representation of the encoder s state

5 Decoding of convolutional codes with the Viterbi Algorithm SOVA decoder is composed of 5 components : the ACS (Add-Compare-Select) processors ; the metric computation unit ; the hypercubic paths between processors that diminish the amount of exchange between registers ; the trace-back computation unit to search back the best path, through the trellis [3] an algorithm to revise the paths []. 5

6 Soft Output Viterbi Algorithm : SOVA code (3 bits = alpha) code 1 ( 3 bits ) Clk Reset Acs [patth, name] Acs 1 [path, name] Compare cumuls max cumula code,1 tbbf cumula cumuls code,code1 tbbf mux mux cumul (Gamma bits) Control cube [lienx or y] Clk clk divider mux mux cumuls cumula code,1 tbbf cumuls cumula code,code1 tbbf tbbf Sel ptr ( bits) ptr ( bits) Acs 1 [path, name] Acs 11 [path, name] Trace Back [tbb, debut] tbbf diff à diff3 Memory [ Gamma * (L-1)* k-1 ] [.] Component register Clk and Reset for all components, Sel for the Mux W à W3 Component s integration into the decoder, for K = 3 Revision [ tbbis,..] estimate confidence

7 Path Revision The quantified output of the SOVA corresponds to a confidence measure for each decoded information bit. Treilli de l algorithme de Viterbi états Alternate path Decoded bits états Direct path 1 3 maximum Path revision temps Revision Trace-back At each step, the unit revises the value of the difference between direct path and the alternative path, from the node maximum to the node decoded bits. 7

8 Hardware Implementation Choice Synchronous architecture (one clock). Use of FPGA, for rapid prototyping. Hypercubic structure to diminish the amount of exchange between registers. Trace-back bits method. Correlation s metric on quantified imput ( of 3 bits ). Soft Output drive by the revision units. 1 states hypercubic implementation

9 Hardware Implementation Choice Path value s overflow : use of c []. Circular RAM memory versus register, for MEM and TBK. Maximum between N values with minimization of the delay and the module size. ACS processors grouping strategy. Spatial hypercubic organisation : parallel versus seriel communication between the modules. VHDL language : top-down approch, generic and parametric description. Developement cycle, make of good test bench. CPLD/ ASIC/ Microcontroler/ FPGA : Speed versus price and developpement time. ptr.write ptr.read + Trace-back circular registrer T.B.B matrix B + c( -A) = not(a) + 1 c( -A ) = A - k Path value s overflow : C computation A

10 Why a modular approch? The longer the constraint length, K, (i.e. the amount of memory cells) of the encoder, the more powerful the code is. However, the complexity of the decoder increases exponentially with K. Thus, the number of ACS processors becomes too large to be put on only one FPGA circuit. The problem is to find a generic approch to decompose the SOVA the way that minimize the connection between FPGA. 1

11 Modular Approch data in P3 acs acs1 tbb cumul acs acs3 max memoire One module view Modular architecture max diff choix P P1 P P3 P P1 P module. module n- IO/MUX IO/MUX /. / SÉQUENCEUR/MULTIPLEXEUR SOVA input/output 11

12 Xilinx s FPGA overview Compose of : CLB : Combinatorial logic block IOB : input output block Switch matrix : root line across the circuit Connection line : connect switch matrix to CLB and IOB 1

13 Conclusion Our final goal is to use two SOVA decoders to realize a full-parallel, modular turbo decoder. Performance : - Full parrallel architecture. - L + L bis + bits of delay between the input and the output. - Number of CLB = 75 : on a 5- Xilinx chip. - Number of states : 1. - Decoding speed : 11 Mbits/s. 13

14 References [1] G. D. Forney, The Viterbi algorithm, Proceedings IEEE, vol. 1, pp. -7, March [] H. L. Lou, Implementing the Viterbi algorithm, IEEE Signal Processing Magazine, September 1995, pp -5. [3] G. Fettweis, Algebraic survivor memory management design for Viterbi detector, IEEE Transactions on Communications, vol. 3, no. 9, pp. 5-3, September [] C. Berrou, P. Adde, E. Angui, S. Faudeil, A low complexity soft-output Viterbi decoder architecture, Proc. IEEE Int. Conf. on Communications, pp. 73-, May 1993 [5] C. Berrou, A. Glavieux, P. Thitimasjshima, Near Shannon Limit Error Correcting Coding and Decoding: Turbo-code, Proc. IEEE Int. Conf. on Communications, pp. 1-7, May [] L. E. Pouliot, P. Fortier, Rapid Prototyping of Modular/Hypercube Trellis Decoders for Communication Systems, Canadian Conference on Electrical and Computer Engineering, St. John s, NF, May , pp