4.4 Implementation Structures in FPGAs and DSPs. Presented by Lee Pucker President, ForwardLink Consulting

Transcription

1 4.4 Implementation Structures in FPGAs and DSPs Presented by Lee Pucker President, ForwardLink Consulting

2 Agenda Case Study on Implementation Structures Synchronization in a GSM Network Option 1: DSP Implementation of a GSM Sync Burst Matched Correlator Option 2: FPGA Implementation of a GSM Sync Burst Matched Correlator Discussion on Trade-offs in Device Selection Conclusions

3 Typical problem Synchronization on a GSM network The Mobile Station and Base Station Terminals in a GSM network contain multiple clocks that run asynchronously For these radios to communicate, they need to synchronize their clocks

4 This Problem is Addressed Through the GSM Logical Channel and Frame Structure GSM Signals Are Transmitted in Bursts 1 Burst per Time Slot Each time slot contains bits at bits/sec 8 Time Slots per Frame One time slot in each downlink frame is used by the base station to transfer synchronization and control information Referred to as logical channels Every 10 frames, the base station transmits a Sync Channel (SCH) to facilitate synchronization by the mobile station with the base station Source: ETSI 3GPP TS FCH SCH BCCH BCCH BCCH BCCH FCH SCH FCH SCH FCH SCH FCH SCH IDLE

5 The GSM Synchronization Channel (SCH) The GSM Synchronization Burst Contains a training sequence of 64 bits that is used to facilitate synchronization Sync bits are known by both the base station and the mobile Detecting where the synchronization burst occurs in time allows the mobile station to synchronize with the base stations baud clock and frame clock Tracking the drift from SCH burst to SCH burst can be used by the mobile station to fine tune receiver clock More on this when you study Synchronization later in this course

6 Process for detecting the GSM SCH Oversample the received complex baseband GSM signal by 4X This allows us to synchronize to the base station with an accuracy of.25 bits Sometimes referred to as a qbit Baud rate = MSymbols per second, so the sample rate is MSamples per second GMSK modulate the training sequence of the SCH to create the matched filter and upsample by 4 Creates 64 X 4 samples = 256 samples Slide the received GSM sample data against the matched filter to find the correlation peak

7 Matched Filter for Detecting a SCH

8 The Correlation Function Let MF be the Matched Filter Sequence (Length 255) Let S be the Signal Sequence C be the Correlation Sequence Cn = Σ 255 MF(m) x S*(n+m) m = 0

9 DSP Implementation of the GSM SCH Matched Filter The TMS320C6416 Processor

10 A Typical DSP the TMS320C6416T Single C64x fixed point DSP core Independent L1 Program and L1 Data Cache Built in 8Mbit L2 Cache Dual external memory interfaces Viterbi and Turbo coprocessors 3 independent timers Source:TMS320C6414T, TMS320C6415T, TMS320C6416T Fixed Point Digital Signal Processors Data Sheet (SPRF226J)

11 The C64x VLIW Architecture The C64x CPU hosts dual sets of functional units each with dedicated register files.l and.s functional unit performs arithmetic, logical and branch operations.m functional units perform two 16 bit x16 bit multiplies per clock.d data addressing units are responsible for data transfers between register files and memory 32 registers each with 32 bits Source:TMS320C64x Technical Overview

12 Key issue the need to support fixed point math Most DSP s utilize fixed point vs. floating point math Allows for significant reduction in power and cost associated with the device Fixed point math requires scaling to occur 16 bit * 16 bit = 32 bit to maintain full precision 16 bit + 16 bit = 17 bit to maintain full precision If A, B, C, D are 16 bit values, then A*B + C*D requires 33 bits Can t be supported on a processor that only does 32 bit arithmetic Usually handled by right shifting the products to make them 31 bit numbers This is simplified if using unsigned or sign/magnitude values versus 2 s complement

13 GSM Synchronization Channel Matched Filter Implementation on a TMS320C6416t DSP Cn = Σ 255 MF(m) x S*(n+m) m = 0 During each clock cycle (order is important, and optimizations are required) Add/subtract previous complex products to accommodate conjugation and add to previous sum with appropriate scaling using the.l and.s units C_Real = W + X + Cr_Imag C_Imag = Y - Z + C_Imag Computer new complex products using.m unit W = MF_Real * S_Real X = MF_Imag * S_Imag Y = MF_Imag * S_Real Z = MF_Real * S_Imag Decrement m (m = m-1).s Unit If m = 0, Branch using S. Unit Save C to memory for Cn using.d unit Increment n Set m = 256, Reset C to 0; Load next S_Real (n + m), S_Image (n + m), MF_Real(m), MF_Imag(m) into A and B registers using.d unit

14 Performance Training sequence = 64/ or.4096 of the bits in a sync burst For a 1 GHz Clock, the filter implementation shown in the previous slide operating with input data of 1MSPS will consume greater than.4 the cycles for 1 pass Only 2 passes (n=0 and n=1) and the processor is exhausted Solution is to Reduce precision to allow more operations per cycle, or Go to a faster processor

15 FPGA Implementation of the SCH Matched Filter

16 A typical FPGA for wireless signal processing The Xilinx Virtex 5 SXT Virtex 5 SXT FPGA has a number of features supporting wireless signal processing DSP48E Slice Embedded Block Ram Configurable Logic Blocks Source: Virtex-5 Family Overview LX, LXT, and SXT Platforms

17 The Virtex 5 SXT DSP48E Slice Source: Virtex-5 SXT Platform Technical Backgrounder

18 Virtex 4 SXT Block Ram Up to kbit dual port clocks Built in address sequencing to support FIFO and shift register functions Source: Virtex-5 Users Guide

19 Virtex 4 Configurable Logic Blocks Primary logic resources provided by the FPGA Each CLB has 2 slices Each slice consists of mulitple look up tables, registers, and combinatorial logic elements

20 GSM Synchronization Channel Matched Filter Implementation on a Virtex 5 SXT FPGA Filter Taps Stored in BlockRAM 256 Tap Shift register created using BlockRAM Signal In S0 S1 S2 S3 S252 S253 S254 S255 MF0 MF1 MF2 MF3 MF252 MF253 MF254 MF255 X X X X X X X X Sum Multiply and Accumulate Functions Supported via DSP48 Slices C Out

21 Performance Because the FPGA is an inherently parallel processor, the entire correlation can be done in 1 clock cycle The Virtex 5 supports this at clock rates up to 550 MSPS So why wouldn t you always use an FPGA???

22 Design Considerations and Device Selection

23 Device Selection Process Block Diagrams Identify Algorithms for Implementing Each Defined Block. Establish Functional Requirements for Algorithms Block Diagrams with Functional Requirements This step may also include a make versus buy decision Modify Block Diagrams to Better Align Algorithms From Different Air Interfaces Air Interface Specifications Develop From Concept Block Diagram Definition Architectures Supporting Each Mode of Target Air Interfaces Modify Algorithms Based on Device Constraints Selection Criteria for Processing Devices Block Diagram with Functional Requirements Mapped Map Algorithms to to Selected Devices Candidate Processing Devices and Select Devices Modify Block Diagrams Based on Device Constraints

24 Selection Criteria for Signal Processing Devices Performance Can it do the job Programmability Life cycle/maintenance costs Level of Integration Cost per unit Development Cycle Cost of development Power Battery life

25 Example 4 Device Mapping for 8-PSK Demod IF Signal From RF Subsystem (65 MSPS) Decimate by 30 Digital Down Converter (< 65 ops/ Decimate by 2 +/- ε Resampler (< 62 ops/ Quadrature Phase Detector (< 100 ops/ Integrate and Dump Symbol Mapping Recovered Bits To Channel Decoder Carrier Adjust Symbol Rate Adjust Carrier Rate Detector (< 100 ops/ Symbol Rate Detector (< 200 ops/ Baud Clock ( khz) Figure 7a: Base Architecture

26 Example 4 Continued Mapping 1 IF Signal From RF Subsystem (65 MSPS) Decimate by 30 Digital Down Converter (< 65 ops/ Decimate by 2 +/- ε Resampler (< 62 ops/ Quadrature Phase Detector (< 100 ops/ Integrate and Dump Symbol Mapping Recovered Bits To Channel Decoder ASIC (Channelizer) Carrier Adjust Symbol Rate Adjust Carrier Rate Detector (< 100 ops/ Symbol Rate Detector (< 200 ops/ Baud Clock ( khz) DSP or GPP (Channel Processor) Figure 7b: Device Mapping 1

27 Example 4 Continued Mapping 2 IF Signal From RF Subsystem (65 MSPS) Decimate by 30 Digital Down Converter (< 65 ops/ Decimate by 2 +/- ε Resampler (< 62 ops/ Quadrature Phase Detector (< 100 ops/ Integrate and Dump Symbol Mapping Recovered Bits To Channel Decoder FPGA (Channelizer) Carrier Adjust Symbol Rate Adjust Carrier Rate Detector (< 100 ops/ Symbol Rate Detector (< 200 ops/ Baud Clock ( khz) DSP or GPP (Channel Processor) Figure 7c: Device Mapping 2

28 Example 4 Continued Mapping 3 IF Signal From RF Subsystem (65 MSPS) Decimate by 30 Digital Down Converter (< 65 ops/ Decimate by 2 +/- ε Resampler (< 62 ops/ Quadrature Phase Detector (< 100 ops/ Integrate and Dump Symbol Mapping Recovered Bits To Channel Decoder Carrier Adjust FPGA (Channelizer) Symbol Rate Adjust Carrier Rate Detector (< 100 ops/ Symbol Rate Detector (< 200 ops/ Baud Clock ( khz) DSP or GPP (Channel Processor) Figure 7d: Device Mapping 3

29 What Generally Goes Where ASIC/FPGA DSP GPP Digital Down Conversion/ Digital Up Conversion Resampling Resampling Equalization and Preemphasis Filtering Carrier Synchronization Carrier Synchronization Chip Rate/Code Symbol Synchronization Symbol Synchronization Synchronization Spread/Despread Modulation/Demodulation Modulation/Demodulation Carrier Synchronization Interleaving/ De-Interleaving Interleaving/ De-Interleaving Symbol Synchronization Packet Framing Packet Framing Diversity Combining Resampling Error Correction Coding/Decoding Error Correction Coding/Decoding Link Layer Processing Note: System on Chip (SoC) technology may integrate all of the above

30 Real world example (Source: EE Times) GPP for higher levels of the protocol stack DSP for baseband signal processing Hardware coprocessor (ASIC) for computationally expensive functions

31 Discussion