UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering. Computer Architecture ECE 568

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1 UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Computer Architecture ECE 568 Part 14 Improving Performance: Interleaving Israel Koren ECE568/Koren Part.14.1 Background Performance of : Latency main contribution to cache miss penalty» Access Time: time between request and word arriving» Cycle Time: time between requests > access time (for DRAM) Bandwidth -> I/O & Large Block Miss Penalty (L2) uses SRAM: Static Random Access 6 transistors/bit vs. 1 for DRAM cell is DRAM: Dynamic RAM Dynamic - needs to be refreshed periodically ( 8 ms, 1% time) Addresses divided into 2 halves ( as a 2D matrix) Two step operation:» RAS or Row Access Strobe» CAS or Column(s) Access Strobe ECE568/Koren Part.14.2 Page 1

2 DRAM Architecture Col. 1 bit lines Col. word lines 2 M Row 1 N+M N MSB N M M Row Address Decoder LSB Column Decoder & Sense Amplifiers Data D Row 2 N cell (one bit) DIMM (Dual Inline Module) contains multiple chips with clock/control/address signals connected in parallel Each IC includes several smaller arrays ECE568/Koren Part.14.3 DRAM Operation Two steps in read/write access to a given bank Row access (RAS) decode row address, enable addressed row (often multiple Kb in row) small voltage changes detected by sense amplifiers which latch whole row of bits Column access (CAS) decode column address to select a few latches (4, 8, 16, or 32 bits depending on DRAM package) on read, send latched bits out to chip pins on write, change latches which then charge storage cells to required value Can perform multiple column accesses on same row without another row access (burst mode) Each step has a latency of around 15-20ns in modern DRAMs Various DRAM standards (DDR, RDRAM) have different ways of encoding the signals for transmission to the DRAM, but all share same core architecture ECE568/Koren Part.14.4 Page 2

3 Faster Through Organization Simple:,, Bus, same width (32 or 64 bits) Wide: -to-/mux 1 word; Bus to : multiple words (Alpha: 64 bits & 256 bits; UtraSPARC: 512) Interleaved:,, Bus 1 word; N Modules (N=4) MUX ECE568/Koren Part.14.5 Wide memory vs. Interleaving Disadvantages of wide memory Wide system bus (multiple wires) MUX between & cache on processor s critical path Not useful for multiple units independently accessing memory» Multiprocessor/multi-core» I/O» with Non-blocking MUX Simple timing model (word size is 32 bits) 1 cycle to send address, 6 cycles access time, 1 cycle to send data Block is 4 words Simple M = 4 x (1+6+1) = 32 Wide M = = 8 Interleaved M = (1+6+1) +3x1 = 11 ECE568/Koren Part.14.6 Page 3

4 8-way Interleaving ECE568/Koren Part.14.7 K. Hwang, ``Advanced Computer Architecture, McGraw-Hill, How many banks? Independent Banks Ideally: number banks number clocks to access word in bank Ex.: 4-way interleaving, 8 words/cache_block; M_cycle=10 cycles For sequential accesses, otherwise will return to original bank before it has next word ready ECE568/Koren Part.14.8 Page 4

5 Bandwidth BW_bank = 1 / DRAM_cycle_time BW of m banks = m x BW_bank (Ideal case) If random memory requests (from different units): BW m^.56 x BW_bank m x BW_bank Example of bandwidth analysis (Burnett & Coffman, Hellerman) maintains a request queue A_1,A_2,...,A_q Before each cycle a request sequence A_1,A_2,...,A_k (k m & k q) is selected so that no two requests are to same bank The closer k is to m, the better p(k) = probability density function of request sequence length m BW = E{k} = k p(k) k=1 Assume all requests are instruction addresses with λ = Prob. of a branch p(1)= λ; p(k)=(1- λ)^{k-1} λ for 1<k<m; p(m)=(1- λ)^{m-1} ECE568/Koren Part.14.9 J. Hayes, ``Computer Architecture & Organization, McGraw-Hill,1998. Bandwidth as a function of λ BW=λ+2(1-λ)λ+3(1-λ)^2 λ+ +m(1-λ)^{m-1} BW= [1-(1-λ)^m] / λ BW=1 when λ=1 lim BW = m λ->0 BW=5 when λ=0.2 for 8-way interleaving J. Hayes, ``Computer Architecture & Organization, McGraw-Hill,1998. ECE568/Koren Part Page 5