Y. Tsiatouhas. VLSI Systems and Computer Architecture Lab. On-Line Testing 2

Transcription

1 CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina On Line Testing ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques Overview. Reliability issues Transient faults 2. Soft errors 3. Timing errors 4. tolerance design techniques VLSI Systems and Computer Architecture Lab On-Line Testing 2

2 Reliability in Nanometer Technologies Soft Rate (SER) increases with technology scaling 64K ynamic Logic MB SRAM IEM 999 The evolution (scaling) of CMOS technology results in: the reduction of the transistor size the increment of the operating frequency the reduction of the power supply voltage the increment of the transistors number in a die which h in turn affect the circuit it noise margins and reduce their reliability. SER vs V On-Line Testing 3 Transient Faults and On Line Testing Permanent Faults: faults that permanently affect the circuit operation. Temporary Faults: faults that do not affect permanently the circuit operation and are discriminated to: Transient Faults: due to random fault generation mechanisms lk like power supply disturbance, electromagnetic interference, radiation e.t.c. Intermittent Faults: due to the degradation of the circuit characteristics. On Line Testing: testing procedures are performed during the circuit operation. Concurrent Testing: testing is performed concurrently to the circuit normal operation. Periodic Testing: testing is performed periodically when the circuit is in the idle mode of operation. Off Line Testing: testing is performed when the circuit is not used (e.g. manufacturing testing). On-Line Testing 4 2

3 Requirements We need design techniques and architectures that will guarantee the correct operation under any circumstances. Techniques that will provide error resiliency or error detection / correction capabilities. We need self checking and concurrent testing mechanisms. We need self healing architectures that will dynamically react to overcome technology and environmental related variabilities and which will be capable to recover after an error generation and will operate correctly even in the presence of failures. Towards this direction, error tolerance techniques have been proposed: error correction codes and self checking circuits and checkers error mitigation techniques aiming to reduce error rates error detection and correction methodologies On-Line Testing 5 Radiation and Soft s (I) Cosmic Rays Primaries Low Energy isappear eflected ~25Km Secondary Cosmic Ray Secondary Cosmic Rays (neutrons & pions) Earth ~/cm 2 s at sea level Burst of Electronic Charge M electrons/μm Si Problem with Soft s in VLSI circuits due to Single Event Transients (SETs) andsingle Event Upsets (SEUs) generated by: emitted α particles by package impurities cosmic ray particles (neutrons, protons and pions) On-Line Testing 6 Si 3

4 Radiation and Soft s (II) SET Transient pulse attenuation/masking! Transient Pulse of uration SET Soft generation! Soft On-Line Testing 7 Timing s (I) Transient faults due to crosstalk, power supply disturbance or ground bounce and environmental variations (e.g. temperature gradients) contribute to timing error generation. evice aging (BTI, HCI effects) is also an important sourceof timingi errors. Timing verification turns to be a hard task. Moreover, the increased path delay deviations, due to process variations and the statistical behavior of nanodevices, as well as the manufacturing defects that affect circuit speed may result in timing errors that are not easily detectable (in terms of test cost) in high frequency and high device count ICs. Considering also the huge number of paths in modern circuit designs along with the complexity of testing, it is easy to realize thatt a significant ifi number of df defective ICs may pass the fabrication tests. Modern systems running at multiple frequency and voltage levels may suffer from timing errors due to environmental and process related (and also data dependent) variabilities that can affect circuit performance. On-Line Testing 8 4

5 Timing s (II) free case Timing generation! elayed Pulse by d d On-Line Testing Timing 9 The Scan esign Topology of Intel UPATE C PH2 C C2 PH 2 System + CAPTURE SI Scan 2 C2 C LA C LB SO SCA SCB Separated System and Scan s Extra cost of one On-Line Testing 5

6 Intel s Resilience Approach UPATE C PH2 C C2 PH 2 Main + X CAPTURE Scan_IN AN Scan X 2 C2 C LA C LB _L Scan_OUT SCA SCB Additional cost of:, 2 X, AN and per! The error detection latency is high! Univ. of Stanford & Intel IEEE Computer, 38 (2), 25 On-Line Testing The BISER Architecture Main A BISER C Element C + V Secondary Shadow B Weak Keeper A B B A Gnd Muller C Element Univ. of Stanford & Intel ICICT, 27 On-Line Testing 2 6

7 The GRAAL Architecture Φ Register Main + Φ2 Shadow X _j _j+ Φ Φ2 Φ2 Φ Φ Φ2 TIMA & iroc ITC, 27 On-Line Testing 3 The Razor Topology Main Razor + Shadow X _L _R j Additional cost of:, X, and per! Univ. of Michigan & ARM IEEE Computer, 37 (3), 24 On-Line Testing 4 7

8 The Razor Operation (I) Main Razor + Shadow X _L _R j Free Case On-Line Testing 5 The Razor Operation (II) Main Razor + Shadow X _L _R j Erroneous Case _ No error detection latency! One clock cycle cost for error correction! On-Line Testing 6 8

9 The Time ilation Topology T Register Main M T + X _L _R j Capture Cap_ elay Additional cost of: X, and per. Univ. of Ioannina & Athens IEEE ICECS, 26 On-Line Testing 7 The Time ilation Operation (I) T Register Main M T + X _L _R j Free Case Capture Cap_ elay On-Line Testing 8 9

10 The Time ilation Operation (II) T Register Main M T + X _L _R j Erroneous Case Capture Cap_ Cap_ elay No error detection latency! One clock cycle cost for error correction! On-Line Testing 9 Timing iagrams Cycle i Cycle i+ Cycle i+2 Cycle i+3 Valid ata Correct Arrival Cap_ Timing Fault Valid ata elayed Arrival Memory State ata i ata i+ Extended Memory State Capture ata i ata i ata i+ Correct ata Erroneous ata Timing Correction Correct ata On-Line Testing 2

11 The Time ilation Architecture Logic Logic Logic Logic Stage Stage Stage Stage I EX MEM T FF Re eg. T FF Re eg. T FF Re eg. _R _R _R 2 _R 3 _R 4 T FF Re eg. T FF Re eg. Capture FF elay Cap_ Pipeline Organization On-Line Testing 2 Pipeline Recovery Failing stage Erroneous stage Time in cycles I EX MEM MEM I ~EX EX MEM I nstructions I I EX MEM I EX I Re execution with correct values at stage inputs On-Line Testing 22

12 References Making Typical Silicon Matter with Razor, T. Austin,. Blaauw, T. Mudge and K. Flautner, IEEE Computers, vol. 37, no. 3, pp , 24. RobustSystemb S esign with ihbuilt In Soft Resilience, S. Mitra, N. Sif Seifert, M. Zhang,. Shi and K S. Kim, IEEE Computers, vol. 38, no. 2, pp , 25. Built In Soft Resilience for Robust System esign, S. Mitra et al, International Conference on IC esign and Technology, pp , 27. GRAAL: A New Fault Tolerant esign Paradigm for Mitigating the Flaws of eep Nanometric Technologies, M. Nicolaidis, International Test Conference, p. 4.3, 27. Testing and Reliable esign of CMOS Circuits, N. Jha and S. Kundu, Kluwer Academic Publishers, 99. On-Line Testing 23 2