Symbolic Simulation of the Propagation and Filtering of Transient Faulty Pulses

Transcription

1 Workshop on System Effects of Logic Soft Errors, Urbana Champion, IL, pril 5, 25 Symbolic Simulation of the Propagation and Filtering of Transient Faulty Pulses in Zhang and Michael Orshansky ECE Department, University of Texas at ustin bstract This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliability of commercial electronics. For the first time, a fast and accurate technique based on static, vector-less analysis of soft error rates (SER) in general combinational circuits is proposed. The analysis technique is targeted to cell-based designs and characterized by two essential features: () accurate error-pulse propagation and attenuation models of library cells that are based on STlike pre-characterization methods; and (2) an efficient computational procedure for pulse propagation via encoding of the error-pulses with the binary decision diagrams (DD). oth electrical and logical masking mechanisms of soft errors are accurately captured.. Introduction Reliability of commercial electronics with respect to the increasing error rates due to extrinsic radiation, known as soft error, is becoming a significant concern. Historically, the most significant impact of soft errors was on memory units (latches, flip-flops, registers, and arrays). However, as the transistor feature size scales down, soft errors due to combinational logic are becoming more substantial. It is predicted that by 2, the soft error rate (SER) due to combinational logic may be comparable to that of the memory units []. ecause of the increasing error rates in combinational circuitry, new tools and analysis methodologies are needed to ensure circuit reliability. oth micro-architects and circuit designers are in need of predicting error rates for their designs. Once estimated, they can assess the need for hardening the design. soft error due to combinational logic only occurs if the following four conditions are all satisfied: ) a high-energy particle (an alpha particle, or a neutron) hits a +/P+ depletion region of an MOS transistor implementing logic gate; 2) the particle-strike generates a error-pulse at the output of the logic gate; 3) the error-pulse successfully propagates to the flip-flop; 4) the error-pulse is latched by the flip-flop at the clock arrival (sampling) time. The propagation of the error-pulse is impacted by several mechanisms that reduce the overall likelihood of the pulse producing an erroneous value at the flip-flop. s a result, the SER may be substantially lower than the raw particlestrike rate. In the literature [-6], these mechanisms are referred to as electrical masking, logic masking, and latching-window masking. ccurately yet efficiently accounting for the reduction of error rate likelihood due to these masking mechanisms is the focus of this work. Prior work in this area has concentrated on modeling and describing the particle interactions at the very low nuclear level (e.g. [7]), performing device-level simulations to predict the electrical response of individual transistors to a particle strike (e. g. [8]), and performing circuitsimulation of a small set of gates to model the propagation of pulses(e.g. []). Several authors have addressed the problem of SER analysis for general combinational logic [2-4]. ccurately estimating the SER due to particlestrikes on combinational logic gates represents a significant computational challenge. The primary reason is that SER de-ratings due to electrical, logic, and latchingwindow masking are all input-vector dependent. Existing techniques approach this problem by explicitly enumerating all input-vectors, or a set of randomly picked input vectors [2-4]. The problem with these techniques is that the size of the input-vector space is exponential to the number of primary inputs. Therefore, for circuits with a large number of primary inputs, these techniques usually take hours, or even days, to achieve reasonable accuracy [4]. In this paper, we propose an efficient and accurate approach for SER analysis of cell-based designs. The efficiency is achieved by resorting to symbolic representation of the error pulses using binary decision diagrams (DD). The accuracy is guaranteed by relying on the precise description of the non-linear gate transfer characteristics using the SPICE-based pre-characterization of the cells in the library. The rest of the paper is organized as follows. Section 2 describes the cell characterization procedure. In Section 3, we discuss the static analysis of SER. Section 4 presents the experimental results, and we draw conclusion in Section Cell-library Characterization The proposed static SER analysis methodology is targeted towards the use with the cell-based design methodology. ccurate library characterization is thus a key

2 Workshop on System Effects of Logic Soft Errors, Urbana Champion, IL, pril 5, 25 consideration. The two essential characterization steps are pulse generation and pulse attenuation (propagation). 2. Pulse Generation particle-strike on a circuit node results in a voltage pulse of a specific magnitude and shape. The goal of the library characterization is to predict for every library gate, with its specific transistor network, the characteristics of the voltage pulse at its output node, and the rate for the voltage pulse to occur. In this work, we only consider particlestrike due to high-energy neutrons present in the cosmic rays. high-energy particle produces a current pulse when it hits the reverse-biased P junction of the + or P+ regions of an MOS transistor. The resulting current pulse can be described by [][4]: 2q t T Iqt (,) = e s () πts Ts where q is the collected charge, and T s is a time constant dependent on technology. q depends on the energy of the particle, and because the energy of the particle follows some distribution, q is a random quantity. The polarity of the current pulse depends on the type of the depletion region. It flows from the junction to the ground, if the depletion region is n-type, and it flows from Vdd to the junction, if the depletion region is p-type. The rate for the collected charge in the + region to fall in the range between q and q+δq, R () q Δ q, is [][4]: Q R () s q Δ q = F eff e Δ q (2) Qs where F is the flux rate of the high-energy particles, eff is the effective area of the cell s + region, and Q s is a technology-dependent constant. The rate for the collected charge in the P+ region is determined similarly. The severity of the particle strike on a cell is described by the voltage pulse at the cell s output node. The voltage pulse is determined by four factors: current pulse in (), load capacitance of the cell C load, exact location of the + (P+) region the particle-strike occurs, and input-vector of the cell. mong the above four factors, the current pulse, which is characterized by the collected charge q, and C load play the dominant roles. Therefore, for simplicity, given a combination of q and C load, we choose the exact location of the +(P+) region and the input vector of the cell in a way such that the worst-case voltage pulse results. To characterize the voltage pulse, SPICE simulation is performed for each of the data points in the set Ω, defined as, t Ω = [, Q ] [, C ] (3) max q max where Q max is the chosen maximum collected charge, and C max is the maximum load capacitance the cell can have. The outcome of this characterization step is a table of voltage pulses indexed by q and C load for each library gate. 2.2 Cell s Dynamic Transfer Function fter a transient faulty pulse is generated, it propagates toward the primary outputs of the circuit. In the course of its propagation, the pulse s electrical properties, such as width and magnitude, evolve as a result of the low-pass characteristics of the gates it propagates through. Specifically, short pulses tend to be attenuated, while long pulses tend to maintain their original width and magnitude after passing through a combinational logic gate. Keeping with the spirit of static analysis, we capture the dynamic transfer function of each library cell at the library characterization stage. The shape of the output pulse is mainly determined by the shape of the input pulse and the cell s load capacitance. While different input-pin to output paths may be characterized by somewhat different transfer characteristics, this is a secondary effect, which we have for now ignored.. Performing circuit simulation for all possible input pulse waveforms and load capacitances in order to capture the transfer function is expensive. We used a characterization approach based on functional approximation. set of base simulations are performed once, each followed by the sensitivity analysis. The input pulse characteristics, or load capacitance values are varied slightly, the impact on the output pulse is observed. The result is a matrix of partial derivatives for each combination of input pulse and load capacitance. Pulses may re-converge and overlap at a gate in a circuit if multiple paths exist between the particle-striking point (fault-site) and the gate. We do not specifically characterize this case. Our strategy is to capture the firstorder effect of pulse-overlapping. We first treat the overlapped input pulses as logic signals and perform logic operations on the input pulses. fter this step, for instance, very short pulses may result, depending on the polarity and timing alignment of the input pulses. In reality, these very short pulses may never show up due to the logic gate s low-pass filtering characteristic. Therefore, the cell s dynamic transfer function on a single pulse is applied to the pulse just obtained to get a more realistic output pulse. We believe that the error due to this approximation is a secondary effect. 3. Static nalysis of Circuit Soft-Error Susceptibility Instead of explicitly enumerating all the input-vectors or a set of randomly-picked input-vectors, our proposed approach is based on implicit enumeration of the input-

3 Workshop on System Effects of Logic Soft Errors, Urbana Champion, IL, pril 5, 25 vector space. Specifically, the occurrence of error-pulse at a circuit node is represented as a function of the primary inputs symbolically. We use a graph (event-dd) to represent this function. y propagating this fault-encoding function to the primary outputs of the circuits using symbolic manipulations, we are able to analyze the SER statically. Efficient logic operations by symbolic manipulation speeds up analysis for logic masking, while cell-library characterization ensures accurate yet efficient account for electrical masking at run-time. In this work, we make the following functions:. Particle-strike can occur at every gate in the circuit, with any amount of collected charge q. 2. The input-vectors to the circuit primary inputs are stable. The validity of this assumption for SER analysis was proven in [2]. 3. The equilibrium probabilities of the primary inputs are known and independent of each other. The flow of our static SER analysis tool is described in the next paragraph. For each q on each gate, the generated voltage pulse is retrieved from the cell library. We then propagate this pulse statically to the primary outputs of the circuit, where the flip-flops are located. Static error-pulse propagation is discussed in detail in Section 3. and 3.2. The pulse emerging at a primary output (input of a flip-flop) experiences latching-window masking of the flip-flop due to the random nature of the particle-strike time [-4]. Latching probability computation will be discussed in Section 3.3. The total bit error rate (ER) for a flip-flop is then: ER = α (,) q i ( R (,) q i Δ q) + i i q q P P α (,) qi ( R (,) qiδq) where, R Δ q ( RP Δ q ) is the rate of particlestrike on the + (P+) region of gate i, with collected charge in the range of (q, q+δq), and α (,) qi ( α ( qi, ) ) P is a factor attributed to SER reduction due to the masking mechanisms. R Δ q ( RP Δ q ) is determined by the energy spectrum of the particle strike and the effective + (P+) area of the cell, as shown in (2). Our focus in the static analysis is to determine α (,) qi and α P(,) qi. 3. Fault-Event Encoding with DDs The blockage of an error-pulse by a gate because of the values of other controlling input signals is known as logical masking, and without accounting for logical (4) masking, the error rates cannot be accurately estimated [3][4]. In essence, the problem is whether the path from a fault-site to the output is sensitizable under the specific alignment of side inputs to the gates. When formulated in this way, the problem is akin to that of delay fault testing. We represent both the oolean function and the function describing the occurrence of error-pulse by binary decision diagrams (DD) [9]. The binary decision diagram that describes the oolean function at a node is referred to as static-dd. In a static-dd, the logic values of a circuit node for various input-vectors are represented as the logic values in the terminal vertices. To find the logic value for a particular input-vector, we start from the root vertex of the static-dd and follow the branches determined by the input-vector until we reach a terminal vertex. Similarly, we can encode the error-pulse occurring at a node in terms of a DD, which is referred to as event- DD. In this case, the terminal vertices of an event-dd represent both the error-pulses and the original logic values (referred to as static logic values). The example event-dd in Figure is interpreted as: if (= D =), the output is a stable ; otherwise, the output is a falling pulse (the polarity of the pulse is implied by its static logic value). ote that a gate s output may contain multiple pulses due to signal re-convergence. To capture that possibility, we use a vector of pulses in the terminal vertices of the even-dd to describe the events. If none of the terminal vertices of an event-dd contains a pulse, as a result of electrical masking, it effectively degenerates to a static-dd. This generality feature of the event-dd greatly simplifies our algorithm in the sense that to construct a new event-dd, operations can be performed either between two event-dds, or between an event- DD and a static-dd, using existing DD techniques [9, ] with slight modification in the operation rules as described in Section Fault Generation and Propagation with event-dd For a gate to produce an error-pulse after a particle-strike in the + region, its output must originally be, as the particle-strike can only lead to the lowering of the potential. (ecause of the similarity of the two cases, we limit the discussion to the case of the + sensitive region.) For the D gate in Figure, given a strike in the + region, there are two scenarios: ) if = (X=), no pulse is generated and X remains at ; 2)if = (X=), a falling pulse is generated at X, and the pulse shape can be retrieved from the cell-library, given the collected charge q and load capacitance of the cell C load. The state of X can be represented graphically by an event-dd shown in Figure.

4 Workshop on System Effects of Logic Soft Errors, Urbana Champion, IL, pril 5, 25 X Static = rriv_t= t Width = t Peak = V Figure. Fault-encoding with event-dd when a falling pulse is generated at a D gate. Pulse arrival time, width (the duration above the threshold voltage), and peakto-peak value are used to describe the error-pulse. The polarity of the pulse is implied by the original static logic value. When none of the terminal vertices contains an error-pulse, it degenerates to a static-dd, describing the oolean function at that node. Propagating the fault events statically is equivalent to constructing the event-dds for the circuit nodes in the fan-out cone of the fault-site where the particle-strike occurs. The event-dd of a circuit node is simply its static-dd for the circuit nodes outside the fan-out-cone of the fault site, since they do not contain error-pulses. We construct the event-dds starting from the fault-site, and proceed to the primary outputs. To construct the event- DD of a gate s output, the event-dds at its inputs must be constructed first. Constructing the output event-dd for an operation on two input event-dds is a recursive process similar to that of constructing the static-dd, which utilizes the standard DD operations [9]. The operations are different only in how the terminal vertices are processed. Specifically, when the terminal vertex of one operand is reached, we check if the state of the output is able to be determined: if yes, a terminal vertex for the output event-dd is generated; and if no, a non-terminal vertex for the output is generated, and the other operand event-dd is searched one level deeper for more information. Determining the state of the output is through logic operation and table look-up from the library. Logic operation is performed, for example, if one operand has a controlling value and has no pulse, in which case, the output value is determined regardless of the state of another operand (logic masking). Table lookup is performed when the analog characteristics of the output pulse is to be determined (electrical masking). Figure 2 illustrates the event-propagation for a small circuit. For simplicity, only the pulse width (the duration above the threshold voltage) is used to describe the pulse in this example. In Figure 2(d), the error-pulse is logicallymasked when =. The pulse width changes along the propagation. The event-dd at node X is the same as its static-dd because the pulse at node X is too small to reach the threshold voltage. If the pulses contained in an event-dd are all eliminated after passing through a gate, such as the case of Figure 2(e), there is no need to propagate the event-dd further. This is another feature of the approach to achieve computational efficiency Static = rriv_t= 2 Width = 3 M Static = rriv_t= Width = 4 (b)m (d) 4 (a) (c) (e)x Figure 2. Illustration of static pulse propagation in a simple circuit. umbers inside the gates are their propagation delays. The pulses are described by their widths. (b), (c), (d) and (e) are the event-dds of node M,,, and X, respectively. In (d), the error-pulse is logically-masked when =. The pulse width changes along the propagation because of electrical masking. The event-dd at node X is the same as its static-dd because the pulse at node X is too small to reach the threshold voltage. 3.3 Latching Probability Computation fter the event-dd propagates to the primary outputs, the error-latching probability for particle-strike at the faultsite can then be assessed if the signal statistics of the primary inputs are known. First, we find the probability for each terminal vertex to occur by traversing the event-dd. This is similar to finding the probability for a oolean function to be or using DD []. ext, the latching probability of each pulse contained in the terminal vertices is calculated [][ 3]: X

5 Workshop on System Effects of Logic Soft Errors, Urbana Champion, IL, pril 5, 25 pw w PL( pw) = (5) Tc where PL is the latching probability, pw is the pulse width, w is latching-window size of the flip-flop, and T c is the clock period. The error-latching probability of an event- DD is the sum of the PL for all pulses in its terminal vertices weighted by the probabilities for them to occur. This error latching probability is α ( qi, ) ( α ( qi, ) P ) in (4). Using (4), we are able to determine the actual ER for all the flip-flops. 4. Experimental Results The static analysis tool was implemented in C++ on a Dell GX26 workstation. We used an internal cell library based on PTM nm technology []. The tool takes a technology-mapped netlist, equilibrium probability of the primary inputs, clock period, and flux rate of the highenergy neutrons, and gives ER of the flip-flops at the primary outputs. In order to verify the validity of the static fault-event propagation, we devised a Monte-Carlo test based on SPICE simulation. We assume that the equilibrium probabilities are all.5. In the test, randomly generated input-vectors are fed to the circuit primary inputs and for each random input-vector, we simulated the behavior of the output signal for a given particle-strike (modeled as a current pulse in ()) on a given gate (fault-site). ased on the simulation results, we calculated the bit error rate contributed by each individual fault-site. The comparison between the Monte-Carlo simulations and the static analysis is shown in Figure 3. s can be seen, the static analysis achieves reasonable accuracy. We demonstrate the efficiency of our algorithm using three randomly generated circuits. The results are shown in Table I. The runtime of the algorithm on circuits considered so far is low. Experiments to test the algorithm on larger benchmark are currently underway. 5. Conclusions In this paper, we proposed a static soft error analysis tool based on symbolic manipulation and fault-encoding using DD. Initial experimental results show that the proposed approach is accurate and computationally efficient. Figure 3. Contribution to the bit error rate of a test circuit by particle strike on each individual gate. The total ER is the sum of ER contributed by all gates in the circuit.

6 Workshop on System Effects of Logic Soft Errors, Urbana Champion, IL, pril 5, 25 Table I. Experimental results for several benchmark circuits. #of inputs ER(FIT) Processing time (s) References [] P. Shivakumar et al, Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic, Proc. DST, pp , 22. [2] H. Cha et al, Gate-Level Simulation Environment for lpha-particle-induced, IEEE Trans. Computers, Vol. 45, pp , 996. [3] K. Mohanram et al, Cost-Effective pproach for Reducing Soft Error Failure Rate in Logic Circuits, Proc. ITC, pp , 23. [4] M. Zhang et al, Soft Error Rate nalysis (SER) Methodology, Proc. ICCD, pp.-8, 24. [5] Q. Zhou et al, ''Transistor Sizing for Radiation Hardening,'' Proc. IRPS, pp. 3-35, 24. [6] Q. Zhou et al, ''Cost-Effective Radiation Hardening Technique for Combinational Logic,'' Proc. ICCD, pp. -6, 24. [7] P. C. Murley et al, Soft-error Monte Carlo modeling program, SEMM, IM J. Res. Develop., Vol. 4, pp. 9-8, 996. [8] P. Hazucha et al. Impact of CMOS Technology Scaling on the tmospheric eutron Soft Error Rate. IEEE Trans. ucl. Sci., Vol. 47, pp , 2. [9] R. ryant, Graph-based algorithms for oolean function manipulation, IEEE Trans. Computers., Vol 35, pp , 986. [] F. ajm, Transition density, a stochastic measure of activity in digital circuits, Proc. DC, pp , 99. [] PTM,