Proceedings of the International Conference on Computer Design, pp , October 1993

Transcription

1 Proceedings of the International Conference on Computer Design, pp. 5854, October 99 A LogicLevel Model for Particle Hits in CMOS Circuits Hungse Cha and Janak H. Patel Center for Reliable and HighPerformance Computing University of Illinois at UrbanaChampaign Urbana, IL 687 Abstract Systems designed for reliability must be validated through simulations. However, traditional SPICE like simulators or even mixedmode simulators are too slow for the task of simulating the eects of particle hits on relatively large circuits. Gatelevel simulators oer tremendous speedup over these electrical level simulators, but they are only as good as the which captures the particle eect at the logic level. The goal of this research is to develop a computationally ecient which captures the behavior of the particle at the logic level. This can then be used in a gatelevel timing simulator to propagate the particle eects to the latches and the outputs of the circuit under simulation. We have developed a closed form solution to approximate the logic pulse waveform resulting from particle hits. As is presented in the paper, the tracks the data from SPICE simulations remarkably well. Introduction Computers are increasingly being used in critical applications in which reliability is of the utmost importance. Due to recent advances in VLSI technology, device dimensions have shrunk to the submicron region, and as a consequence, circuits have become more susceptible to the particles. The circuits used in critical applications in space must be designed to tolerate the particle hits. These circuits should undergo a validation phase where the particle hits are simulated. Since these hits produce electrical eects on the circuit, electricallevel simulators have to be used to accurately propagate the particle eect. However, electricallevel simulators such as SPICE [] are too slow on even a moderatesized circuit. Mixedmode simulators have been developed and used to speed up the simulation time, but even these are not fast enough [, ]. Recently, gatelevel simulators have been employed to drastically improve the simulation time [4, 5]. However, gatelevel simulators are only This research was supported by Joint Electronic Service Program Contract N4J97. as good as the which maps the electricallevel particle eect into logic level eect. The goal of this research is to develop a computationally ecient to capture the behavior of the particle phenomenon at the logic level. This can then be used in a gatelevel timing simulator to propagate the particle eects to the latches and the outputs of the circuit under simulation. We have developed a closed form solution to approximate the logic pulse waveform resulting from particle hits. Each of the steps leading to the nal solution is presented in this paper. In Section, we describe the charge collection phenomenon caused by particles. Then we give the for the transient voltage pulse width at the injection node in section, followed by the of the propagation delay of an inverter in the next section. In section 5, the s developed in previous sections are put together to the logic eect of the particle at the output of the succeeding gate. Finally, we conclude in section 6 with a discussion on the applicability of this. The immediate eects of particles The phenomenon of particles striking MOS devices has been extensively studied by researchers [6, 7]. It may be ed by a time varying doubleexponential current pulse [7] I(t) = I o (e?t=? e?t= ); () where is the collection time constant of the junction and is the time constant for initially establishing the ion track. The time constants for the exponentials depend on several process dependent factors, and in this work, the time constants given in [8] are used: = :64? sec and = 5:? sec. There are four possible cases of charge injection scenarios for CMOS circuits as shown in Figure where the resistors represent conducting transistors, the rectangles represent the drain regions of transistors, and the direction of arrows inside the current sources correspond to the direction of the current ow. For cases I and II, the voltage at the p node will go up, and for

2 case I p n n p case III p n case II n p case IV Pulse width (nsec) pC 8pC 7pC 6pC 5pC 4pC Number of fanout inverters Figure : Pulse width at the injection node Figure : Four possible scenarios for charge injection due to particles R (a) C Figure : Equivalent circuit for charge injection cases III and IV, the voltage at the n node will go down. Cases II and IV will not aect the logic state of the circuit because the node is already at the logic value toward which the injected charge will drive the node. However, cases I and III may aect the logic value of the node, which in turn may cause incorrect operation of the circuit. In this paper, we will only consider inverters since other gates can be mapped to equivalent inverters. At the time of the fault injection, the aected inverter may be switching, or it may be at a stable high or low. Since recent work indicates that transient faults injected before the circuit has settled for the clock cycle rarely manifest themselves as latched errors [5], we will not consider the case of transitioning inverter at the time of fault injection. Furthermore, of the two possible remaining cases as shown in Figure, we will only consider (a) since the case shown in (b) can be analyzed in a similar manner. R (b) C The pulse width at the injection node The voltage waveform resulting from an particle depends on three quantities: the injection charge, the strength of the conducting transistor and the total capacitance at the injection node. If we consider the PMOS transistor as a linear resistor R, an analytical solution for the output voltage as a function of time can be obtained: V o (t) = RI o e?t=? e?t=rc? RC=? e?t=? e?t=rc? RC= V DD : () Upon examining equation, we nd that V o (t) is a function of two quantities, RI o and RC. This observation simplies our of the voltage pulse waveform because now we may describe it as a function of two quantities instead of three. For the development of the s in this paper, we have used MOS level parameters from Orbit, a fabrication company accessible through MOSIS. The inverter design used is from the standard cell library from Mississippi State University which is distributed as part of the Octtools [9] set from University of California, Berkeley. SPICE simulations have been run on the invf inverter with various injection charges and various output capacitances. The logic threshold of.5 V has been used to obtain logic waveforms from the voltage waveforms. The pulse width as a function of the injection charge and the number of fanout inverters, which represent the capacitance at the injection node, is shown in Figure. We can immediately see two distinct regions of behavior. For smaller capacitances, the pulse width increases with

3 V DD V DD / T IS T PHL input output Figure 4: Denition of propagation delay of inverters increasing capacitance. This is due to the slower RC time constant for recharging the injection node. For large capacitances, the injected charge is not enough to drive the voltage to the opposite power rail, resulting in smaller pulse widths. The pulse width can be ed by two linear equations of the form P W = A L W I o B L W C out Const; () where P W stands for the pulse width at the injection node, and A; B, and Const are obtained from linear regression analysis of SPICE data. The P W computed using the above equation is superimposed on the SPICE data in Figure. As can be seen, the and the SPICE data agree quite well. 4 Propagation delay of inverters In the previous section, we have developed a simple for the pulse width at the injection node, but it does not give us enough information about the shape of the pulse, which is needed if we are to propagate the pulse to the output of a succeeding gate. Before we can proceeed, however, we rst need to investigate the propagation delay of inverters. The propagation delay is dened as the time it takes for the output to reach V DD = minus the time it takes for the input to reach V DD =. The falling delay P HL is shown in Figure 4, and the rising delay P LH is similarly dened. The gure also shows T IS, which is the time it takes for the ramping input to fully change. SPICE simulations of invf with various values for T IS is shown in Figure 5. As can be seen in the gure, the propagation delay is a nonlinear function of T IS and the output capacitance. Therefore, a simple curve tting technique is inappropriate and we need a deeper understanding of the propagation delay as a function of these parameters. Using the simple square law current equations for the MOS transistors, a closed form solution for the propagation delay for the step input change can be found []: P HL = D L W C out; (4) Propagation delay (nsec) Tis = 8 ns Tis = 6 ns Tis = 4 ns Tis = ns Tis = ns Number of fanout inverters Figure 5: Propagation delay of inverter as a function of T IS and output capacitance where D is a process dependent parameter. Although this solution has been obtained using the square law current equations, it can be applied in general with the parameter D extracted from SPICE simulations followed by linear regression analysis. The above equation is valid for the step input change, but as can be seen in Figure 5, the propagation delay is also a function of the input slew rate. Researchers have developed various s for P HL as a function of ramping inputs [,,, 4]. We have based our on Shoji's work [] since it is very simple, making it suitable for inclusion into a gatelevel simulator. Solving for the propagation delay using very simple linear current equations for MOS transistors, he obtains 8 < P HL = P HL : p? if < if > ; (5) where is the input slew rate, is a factor indicating the relative strengths of the NMOS and the PMOS transistors, P HL is the P HL for the step input change, and is the slew rate which marks the boundary between the dierent regions of behavior. We have modied and as follows to t the data from SPICE better: and = = k N (W=L) N G k P (W=L) P k N (W=L)N k P (W=L)P E F G (6) V DD P HL ; (7)

4 first level gate second level gate third level gate Figure 6: Denition of gate levels where E, F, and G are parameters to be extracted from SPICE simulations followed by linear regression analysis. The parameters E and F are needed to provide a better matching in the region >, and the parameter G is needed in the region < for the same reason. Furthermore, G is actually dependent on the relative strengths of NMOS and PMOS transistors, and it is in turn ed by a linear function whose parameters are obtained from SPICE data. The computed values of P HL from the equations above are superimposed on the data from SPICE simulations in Figure 5, and, as can be seen, they match very well. 5 The eect of charge injection on the output of a fanout inverter The goal of this research, as is mentioned above, is to develop a to compute the logic level eect due to an particle hit. Researchers have found that at least three gate levels as shown in Figure 6 are needed in SPICE like simulations until the electrical eects become stable enough to be treated as logic signals [, ]. However, most of the time the electrical eects become stable enough to be treated as logic signals after only two gate levels and the additional eort involved in ing the third gate level is not justied. In order to nd the pulse width at the output of the second level gate, we need information about the shape of the pulse at the input. We'll the shape as piecewise linear pulse as shown in Figure 7. The pulse is ed as a step change to the opposite rail followed by a ramp of constant slope. The ramp is characterized by T IS = P LH and it starts at time P W? P LH to satisfy the pulse width found in equation. Now we are ready to nd the pulse width at the output of the second level inverter. According to our of the voltage pulse waveform at the injection node, the second level inverter will see two transitions, one a step and the other a ramp. We can immediately write the following equation to describe the pulse width of the second inverter: P W = P HL? P LH P W : (8) Injection node voltage Time (nsec) SPICE Figure 7: Model of the pulse waveform at the injection node V DD V DD / V Ta Tb input output time Figure 8: Slow transitioning of the second inverter with respect to the input pulse The subscript refers to values at the injection node while the subscript refers to values at the output of the second level inverter. Equation 8 is valid provided that the output of the second level inverter has had enough time to rise to V DD before it is pulled down to ground and that the injection node voltage dips down to V before rising back up. If not, the equation for P W becomes more complicated. We'll consider each of these cases in turn. Figure 8 illustrates the rst case. While the output of the second inverter is still transitioning, the input has risen suciently high to start driving the output to ground. Dene T a and T b as seen in the gure, and assume that the output rises in a linear fashion until the input has risen to V DD = at which time the output starts falling, also in a linear fashion. Then we have, and T b = P HL V DD T a = P W? P LH (9) VDD P LH P W? V DD : () 4

5 Putting equations 8, 9, and together, we have 8 if P LH > P W P HL >< P W VDD V DD P LH P W? VDD P W =? P HL if P LH < P W < P LH P HL? P LH P W >: if P LH < P W () Finally, we should consider the case when the input voltage does not fall all the way down to V. In this case, the PMOS transistor is not fully turned on, and the NMOS transistor may be conducting if the input voltage is high enough. We'll ignore the NMOS transistor since most of the time it does not provide a signicant current. The propagation delay we use must be modied according to how much the input voltage has dipped with respect to some reference value. Assuming that the voltage waveform is triangular in shape in the case we are considering, we can nd the lowest point of the input voltage waveform for the P W under consideration as well the one for a reference P W, and multiply our original value of propagation delay by some factor. The reference P W has been chosen to be the maximum obtained by varying the capacitances at the injection node while keeping the other parameters the same. Then we have and V inmin = V DD V inmin j P W=P Wmax = V DD? V DD T IS P W ()? V DDP W max T IS j P W=P Wmax : () The maximum value of P W as well as T IS j P W=P Wmax can be found directly from equation. Then, we have P LH = P LH factor(v inmin ) factor(v inmin j P W=P Wmax ) : (4) where (V x jv T P j) factor(v x ) = V DD? V x? jv T P j V DD? V x? jv T P j 4(VDD? V x? jv T P j) ln? : (5) V DD The factor(v x ) is taken from an analytical solution for the propagation delay where the input undergoes a step change from V DD to V x. The new propagation delay P LH is used in place of P LH for the Pulse width (nsec) pc 8 pc 7 pc 6 pc 5 pc 4 pc Number of fanout inverters at the injection node Figure 9: Pulse widths at the output of the second level inverter computation of P LH in the case where the injection node capacitance is larger than the one which gives maximum P W. Figure 9 shows P W from SPICE simulations as a function of injected charge and capacitance at the injection node. The capacitance at the output of the second level gate is equal to the gate capacitance of one inverter in this simulation run. The gure also shows the computed values of P W from the which incorporates all of the cases discussed above. Although there are some discrepancies between the two sets of data, we see that the tracks the SPICE data remarkably well. Since we are concerned about the logic pulse waveform, we also need information about the delay from the injection time of the particle to the rst transition of the logic pulse at the output of the second level inverter. This is easily obtained since it is just P LH. 6 Concluding remarks In this paper, a closed form solution for approximating the logic level waveforms due to particles has been presented. The takes into account the strengths of the pullup and pulldown transistors, the amount of charge injection, and the capacitive loading at the injection node and at the output of the second level inverter. Since the has its roots in analytical equations, it applies to a wide range of transistor sizes and fabrication processes. The parameter extraction for the target process is quick and easy since the SPICE simulations are performed only on a few inverters, and furthermore, it has to be done only once for the specic process. Although we have treated only inverters in this work, this is not overly 5

6 restrictive since in most cases the other gates can be mapped to equivalent inverters. Due to its simplicity, the presented in this paper is suitable for incorporation into a gatelevel timing simulator for the accurate simulation of the logic eects of particle hits on CMOS VLSI circuits. References [] T. L. Quarles, \SPICE version C users guide," Memorandum no. UCB/ERL M89/46, Electron. Res. Lab., Univ. of California, Berkeley, Apr [] G. Choi, R. K. Iyer, R. Saleh, and V. Carreno, \A fault behavior for an avionic microprocessor: a case study," in Int. Working Conf. Dependable Computing for Critical Applications, Aug. 989, pp [] F. L. Yang and R. A. Saleh, \Simulation and analysis of transient faults in digital circuits," IEEE J. Solid State Circuits, vol. 7, no., pp. 5864, Mar. 99. [4] E. W. Czeck and D. P. Siewiorek, \Eects of transient gatelevel faults on program behavior," in Digest, th Int. Symp. FaultTolerant Comput., June 99, pp. 64. [5] H. Cha, E. M. Rudnick, G. S. Choi, J. H. Patel, and R. K. Iyer, \A fast and accurate gatelevel transient fault simulation environment," to appear in Digest, rd Int. Symp. FaultTolerant Comput., June 99. [6] T. C. May and M. H. Woods, \Alphaparticleinduced soft errors in dynamic memories," IEEE Trans. Electron Devices, vol. ED6, no., pp. 9, Jan [7] G. C. Messenger, \Collection of charge on junction nodes from ion tracks," IEEE Trans. Nucl. Sci., vol. NS9, no. 6, pp. 4, Dec. 98. [8] V. A. Carreno, G. Choi, and R. K. Iyer, \Analogdigital simulation of transientinduced logic errors and upset susceptibility of an advanced control system," NASA Technical Memorandum 44, Nov. 99. [9] OCTTOOLS5. Part : User Guide, A. Casotto: editor, Electron. Res. Lab., Univ. of California, Berkeley, Oct. 99. [] J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits, AddisonWesley, 988, ch. 4. [] D. Overhauser, I. N. Hajj, and V. B. Rao, \Switchlevel timing analysis of VLSI MOS circuits including parasitics," Proc. IEEE Int. Symp. on Circuits and Systems, May 986, pp [] N. Hedenstierna and K. O. Jeppson, \CMOS circuit speed and buer optimization," IEEE Trans. on Comp.Aided Design, vol. CAD6, no., pp. 78, Mar [] M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, Englewood Clis, NJ, 988, ch.. [4] S. R. Vemuru and A. R. Thorbjornsen, \A for delay evaluation of a CMOS inverter," Proc. IEEE Int. Symp. on Circuits and Systems, May 99, pp