Introduction. Timing Verification

Transcription

1 Timing Verification Sungho Kang Yonsei University YONSEI UNIVERSITY Outline Introduction Timing Simulation Static Timing Verification PITA Conclusion 2 1

2 Introduction Introduction Variations in component delays may be correlated to a certain extent due to global fabrication process fluctuations and similar fabrication process effects on neighboring devices Decreasing minimum feature sizes, increasing design complexity, and faster circuit operation are resulting in the following: gate outputs seeing significant resistive effects of the interconnect load, the need for long interconnect to be modeled as distributed RC elements, and significant capacitive coupling effects across neighboring signal lines This is leading to interconnect delays being a significant part of the chip delay, and in many cases even dominating the delay through the switching elements To ensure correct temporal operation of such circuits, gate-level pre- and post-fabrication timing verification methodologies need to be able to handle the above circuit characteristics 3 Timing Verification Introduction The objective of timing verification of a combinational circuit is either to ensure that the circuit satisfies some given timing constraints at the circuit outputs, or to determine the maximum delay of the circuit under some given component delay model It is also of interest to determine the critical paths in the circuit i.e. those paths that determine the maximum circuit delay This critical path information can be used to decrease the delay of the circuit, which might be desirable when the circuit performance is being optimized, and is necessary if the circuit violates some given timing constraint at one or more of its outputs 4 2

3 Two Strategies Introduction Static Timing Verification Obtain bounds on the maximum delay of a circuit by analyzing in it an input pattern independent manner Dynamic Timing Verification Timing Simulation Used to arrive at an estimate for the maximum delay by repeated simulation of the circuit for different input patterns 5 Timing Simulation Timing Simulation Traditional circuit simulators like SPICE use implicit integration techniques, complex device models and computationally expensive nonlinear equation solvers As a result, the cost of verifying the timing behavior of a large digital circuit with a typical circuit simulator becomes prohibitively high To address this problem, a variety of timing simulators have been developed to exploit the nature of digital MOS circuits and/or use more efficient modeling techniques to be able to handle large circuits The result is a set of tools which compromise on analoglevel accuracy to gain on speed of simulation while still maintaining a level of accuracy sufficient for timing verification of digital circuits 6 3

4 SPECS Timing Simulation A significant speedup in evaluating the timing response can be achieved by using explicit approximation, such as Forward Euler formula This is an approach taken in SPECS Instead of using analytical functions to model electronic devices like in conventional circuit simulation methods, SPECS represents devices by piecewise constant table models of I-V characteristics The event driven simulation process itself makes no further approximations This is very useful in the verification of timing of critical paths in a digital circuit 7 MOTIS Timing Simulation In MOTIS, an internal hierarchy is created by grouping the circuit into superblocks A superblock has multiple inputs and outputs, and is unidirectional externally, but can be bidirectional internally In the timing simulation mode, simplified circuit simulation techniques with less accurate transistor models are used to evaluate the signals within the superblock Logic simulation techniques are used to propagate the values produced This kind of simulation is much faster than conventional circuit simulation 8 4

5 LSIM Timing Simulation Another class of simulation like LSIM combine switch level simulation with simple RC delay models for verifying the timing behavior of MOS circuits LSIM partitions the circuit into channel-connected components, each of which is a graph The vertices of the graph are the circuit nodes and an ONtransistor between two nodes (source and drain) constitutes an edge between them A signal at a node has a logic value and a strength associated with it The problem of finding the steady state response of such a circuit is reduced to the single source shortest path problem in graph theory Using these, results in a speedup of about two orders of magnitude over other simulation methods 9 Timing Simulation Timing Simulation Timing simulation can be done at an even higher level of abstraction using HDL The simulators implemented for these languages allow mixed level descriptions The high level of abstraction permits them to perform fast simulation but the delay models used are very simplistic 10 5

6 STAT Timing Simulation Dynamic simulation level choosing is used in STAT, which is an event driven multi-level timing simulator employing hierarchical timing model A set of model validity conditions(mvcs) are used to dynamically select the level at which a portion of the circuit to be simulated The event queue generated in a run of the circuit with certain delay values for the component delays is reused in a different run of the same circuit with slightly perturbed delays This is particularly important when the verification needs to take into account the variations in delays caused due to perturbations in the chip manufacturing process 11 AWE and ACES Timing Simulation The Asymptotic Waveform Evalation(AWE) technique enables efficient macromodeling of complex interconnect networks However there is a need to merge these AWE macromodels with the transistor level description of the gates to verify signal propagation through the circuit Adaptively Controlled Explicit Simulation(ACES) has been developed to perform timing verification of digital ICs and can handle MOS, bipolar and BiCMOS ACES uses an adaptively controlled explicit integration approximation to compute the circuit response that overcomes the stability problems in previous techniques Simulation accuracy in ACES can be controlled by varying the accuracy of the integration approximation or the piecewise linear device models 12 6

7 TETA Timing Simulation The dominant effects of interconnect delays on the timing performance have been the motivation of a new interconnect-centric approach to timing simulation, called TETA Complex interconnect networks are modeled by reduced order N port macromodels To avoid inverting the interconnect time-domain N-port matrix, TETA applies successive chord iterations for the nonlinear devices and a novel compaction scheme for transistor clusters This approach requires only the stability of the N-port interconnect model, thereby avoiding the problem of nacromodel passivity To increase the simulation efficiency even further, the successive chord iteration method permits table look-up models for MOS transistors 13 One of the earliest tools for timing analysis of a circuit is PERT, which calculated the maximum delay of a logic circuit as the delay of the topologically longest path However, if the functionality of the logic gates is taken into consideration, it is observed that some paths in the circuit are false, that is, they are not sensitizable for any combination of primary inputs This means that the maximum delay of the circuit can be smaller than the delay of the topologically longest path 14 7

8 Assume unit gate delays and zero wire delays. Consider the path a-g1-g2-g3-y that has a delay of 3units. For a rising or falling transition at time zero to propagate form a through this path, the side input at the AND gate g2 must be at a logic 1 at the time this transition propagates through the gate, implying that primary input b should be 1 at time t=1 unit, and also, the side input at the OR gate g3 must be at logic 0 at t=2 units which in turn implies that primary input b be 0 at t=1 unit. Since primary input b is required to be both a 1 and a 0 at t=1 unit, a transition cannot propagate through the path a-g1-g2- g3-y. Hence this path is not sensitizable. a g1 g2 b g3 y Sensitization example g4 15 Single Stepping Transition Mode Assumptions must be made about the range and arrival of PI vectors to the combinational circuit A single stepping transition mode of operation assumption is one where all circuit nodes are assumed to have stabilized to their final values under a previously applied input vector V0 before a new vector V1 is applied This reflects the assumption that the combinational circuit of interest is embedded in a FF based synchronous sequential system The combinational circuit delay found under this assumption can be used as a valid clocking period if this delay is greater than half of the delay if the longest topological path in the combinational circuit 16 8

9 Floating Mode In case this validity condition does not hold, or if the combinational circuit is embedded in a different type of a digital system, it could happen that some of the internal circuit may not have stabilized to their final values under the previous vector before the effect of the newly applied vector propagates to these nodes In such a event, the newly applied vector V1 interacts with not just the most recently applied previous vector V0, but also with other previously applied vectors This mode of operation assumption is termed the transition mode of operation and the delay of the combinational circuit found under this assumption is called delay by sequences of vectors Floating mode of operation assumption Unknown node values imply that the nodes could be at arbitrary values due to the effect of previously applied input vectors 17 Component Delay Model Another important input to timing analysis is component delay model. A common component delay model is the fixed delay model, where the delay of each component c is assumed to be a fixed number Dc. The monotone speedup model assumes that a component can be speeded up arbitrarily, so given for each component c, it assumes that the delay f the component lies in the range [0, Dc]. The bounded delay model assumes that each component delay can vary independently of each other in a range [Dc 1,D c u ] Although these component delay models are commonly used by previously reported timing analyzers, they are not very realistic since the delay of a component depends on many factors : input transition time, output loading, signal activity in neighboring components, internal component state fabrication process fluctuations, supply voltage and operating temperature. 18 9

10 Component Delay Model A family of circuits corresponds to a given circuit netlist with associated component delay models. A circuit instance is usually defined as a circuit obtained by setting the fabrication process parameters to fixed values. We define a circuit instance to be a circuit obtained by setting its component delays to fixed values within their respective component delay models. Note that under the fixed component delay model, a family of circuits has only one circuit instance - that with each component c set to its respective delay value Dc. We will use the term circuit to imply a family of circuits, unless noted otherwise. 19 The maximum circuit instance delay under a given mode of operation assumption is the maximum delay of the circuit instance over all possible inputs under this mode of operation, accounting for path sensitization The maximum circuit delay under a given mode of operation assumption and a given component delay model is the maximum delay of the circuit over all possible inputs under the given mode of operation and over all circuit instance possible under the given component delay model, again accounting for path sensitization The circuit instance at which this maximum occurs is termed the worst-case circuit instance The maximum path delay is the maximum delay a path can be attain for a given component delay model 20 10

11 The floating mode circuit instance delay cannot increase as component delays are reduced, that is, floating mode circuit instance delay follows the monotone speedup property Therefore under the monotone speedup component delay model and the bounded component delay model, the floating circuit delay is found by setting all component delays to their individual maximum values Under the floating mode of operation assumption, the worst case circuit instance is the one with all component delays set to their respective maximum values On the other hand, the 2-vector transition mode circuit instance delay does not follow the monotone speedup property 21 For any given circuit instance, the 2-vector transition mode delay cannot be greater than the floating mode delay This is because the assumption made about the initial values on the circuit nodes is more conservative under the floating mode of operation : allowing arbitrary initial node values under the floating mode of operation assumption takes into account the case when the initial node values are those determined by the previously applied input vector as under the 2-vector transition mode of operation assumption The floating mode delay upper bounds the circuit delay found under any of the other modes of operation It can be derived from this and the monotone speedup property of floating mode delay that the maximum circuit delay found under the floating mode of operation upper bounds the maximum delay of all possible circuit instances under all other modes of operation 22 11

12 An exact path sensitization criterion under the floating mode of operation A path P is exactly sensitizable under the floating mode of operation iff there exists at least one PI vector such that one of the following conditions is satisfied at each gate along the path P The on-path gate input is an earliest arriving controlling value, that is, all side-inputs settle either to non-controlling values at any time or to controlling values when or after the on-path controlling value arrives Or the on-path gate input is a latest arriving controlling value, that is, all side-inputs settle to non-controlling values no later than the arrival time of the on-path controlling value 23 For the loose criterion, the conditions on the gate sideinputs along the path being sensitized are the same as those for the exact criterion except for the last one If the on-path input is a non-controlling value, then all side-inputs settle to non-controlling values Note that no timing constraint has been imposed on the gate side-inputs in this case A path which may not be exactly sensitizable could be classified as loosely sensitizable Nevertheless it is proved that the maximum circuit delay is exactly the same for both criteria 24 12

13 Numerous Sensitization Criterion Numerous sensitization criterion If they are path correct and if the delay they compute is exact or an underestimate or an overestimate Criterion Path-correct Delay Exact(SENV) yes exact Loose(SENV) yes exact Dynamic no exact Viability yes exact Static no underestimate Brand-Iyengar no overestimate Du-Yen-Ghanta yes overestimate Perremans-Clasen yes overestimate -DeMan 25 Static Sensitization Benkoski et. al. Have proposed a path sensitization criterion wherein a path is statically sensitizable iff there exists at least one primary input vector such that the side-inputs at each gate along the path settle to non controlling values. The authors have also presented algorithms to find the statically sensitizable path with the maximum delay, using a either depth-first search technique or a best-first search technique to trace paths, and a modified D-algorithm. They have also introduced a mechanism for directing the path search using the maximum possible delay of a partial path (called its esperance), on the basis that a sensitizable path (under the exact criterion)need not be statically sensitizable, static sensitization has been shown to always produce a lower bound on the floating mode circuit delay. The theoretical argument for this can be found in, while an example circuit which demonstrates this is shown in. Interestingly, it has been shown via an example that the delay of the longest statically sensitizable path can sometimes be an upper bound on the 2-vector transition mode circuit delay

14 Viability A path is viable iff there exists at least one PI vector such that at each gate along the path, the side-inputs either settle to non-controlling values or terminate a viable path under the vector with larger delay A dynamic programming algorithm based on a best-first search technique to trace paths in a non-increasing order of their esperance, and on storing the most recent viability function at each gate input has also been presented An alternative approach for performing viability analysis using path-recursive functions has also been presented Though an unsensitizable path can be viable, the maximum circuit delay found using viability exactly equals the floating mode circuit delay This is because for any path that is viable but unsensitizable, there must exist another path of larger or equal delay that is viable and sensitizable 27 Brand-Iyengar A sensitization criterion where, given some ordering of the inputs to each gate in the circuit, a path is is considered to be sensitizable off there exists at least one vector such that the lower side inputs at each gate along the path settle to non-controlling values Under their sensitization criterion, a sensitizable path may be claimed to be false and an unsensitizable path may be claimed to be true, however, it has been proved that this sensitization criterion will never underestimate the floating mode circuit delay 28 14

15 Du-Yen-Ghanta A path sensitization criterion wherein a path is considered to be sensitizable iff there exists at least one vector such one of the following conditions is satisfied at each gate along the path The on-path input should be a controlling value if there is any side-input which is guaranteed to settle down later than the onpath input Or each side-input that is guaranteed to settle down no later than the on-path has be a non-controlling value This is implemented using a D algorithm 29 Perremans-Claesen-DeMan A path sensitization criterion wherein a path is sensitizable iff there exists at least one vector such that the side inputs at each gate along the path meet one of the following conditions If the on-path input is a non-controlling value, the side-inputs must settle to a controlling value Or if the on-path input is a controlling value, those side-inputs whose upper bound settling time is less than the delay of the onpath signals must settle to a non-controlling value The upper bound settling time at a node is a dynamic variable that gets updated as the algorithm progresses 30 15

16 TrueD-F Devadas et. al. have proposed a method to determine the sensitizability of a set of paths simultaneously, as opposed to many of the approaches described above which rely on path tracing. Their approach is used to answer the question Is there a true path of delay ˆ T?, where T is chosen by examining the path delays in decreasing order, or by a binary search among possible values. The method is based on simultaneously determining the sensitizability of all paths whose delays are greater than or equal to T, and it works by finding a test for a single stuck-fault at the circuit output using a timed D-calculus that is derived from the exact criterion. 31 Dynamic Criterion The dynamic sensitization criterion is similar to the loose sensitization criterion except that when the on-path gate input is a controlling value, the lower side-inputs (under some ordering of the inputs to each gate in the circuit) can either settle to non-controlling values at any time or to controlling values strictly after the on-path controlling value arrives. The order of inputs to a gate are determined dynamically, while an esperance-directed best-first search procedure is used for path tracing and a D-algorithm techniques is used for checking the consistency of the sensitization conditions

17 Timed Boolean Calculus Use timed boolean variables, which are a function of regular boolean variables and time, to model the transient behavior of each circuit mode The timed boolean calculus is a set of rules to propagate these timed boolean expressions through the logic elements in the circuit according to the exact sensitization criterion A heuristic is used to find an approximate representation for these expressions so that the sensitizability computation can be done in polynomial time, the trade-off being that the maximal delay found could be conservative 33 VIPER The conditions for vigorous sensitization of a path which are the same as the loose criterion This method is based on PODEM for sensitizability checking and critical path tracing by extending partial paths based on a cost function 34 17

18 Timed Boolean Function Timed Boolean Function(TBFs) use to determine the maximum delay of a circuit under the single-stepping transition mode of operation and the general transition mode of operation assumptions A TBF is the waveform at a node in the circuit and is represented as a function of the boolean variables and component delays in the fanin cone of the node and a varaible denoting time The sensitized approaches determine the maximum circuit delay under the floating mode of operation by setting all component delays to their individual maximum delay models 35 Timed Boolean Function This is valid for the fixed, monotone speedup and bounded component delay models However it may not be possible to set all component delays to their individual maximum values simultaneously due to the following effects Fabrication process effects : On-chip component delays are correlated to some extent to the effects of similar fabrication process fluctuations Signal propagation effects : The transition time of a gate output affects the delay of not just immediate fanout gates, but also of succeeding downstream logic Signal interaction effects : The delay of a transition through a gate will depend on signal activity on the gate side-inputs, while the delay of a transition through an interconnect line will depend on signal activity on neighboring lines due to capacitive coupling effects 36 18

19 Timed Boolean Function Under these effects, not all components may exhibit their maximum delay values simultaneously, e.g., an increase in the m-channel surface doping in a CMOS inverter increases the delay of an input rising transition and decreases the delay of an input falling transition, therefore the rise and fall delays of a an inverter cannot be simultaneously set to their individual maximum values. The assumption that all component delays can simultaneously be at their individual maximum values is a very pessimistic way of accounting for these effects, therefore previously reported floating mode timing analyzers based on the sensitization criteria mentioned above are very conservative in their delay estimates. Moreover, their sensitization mechanisms offer no way of accounting for these effects in a more realistic manner. Therefore, there is a need for a timing analysis mechanism which can account for fabrication process effects, signal propagation effects, and signal interaction effects very accurately. 37 Statistical Timing Verification Static Timing Verification There are two major reasons for statistical distributions of signal delays: signal interaction effects and fabrication process effects. Capacitive coupling between nets is a result of physical proximity. Manufacturing fluctuations affects both the gates and interconnect parasitics due to difficulties in controlling the fabrication process. These problems have received some attention but the approaches to realistic statistical timing verification to large digital ICs are still inadequate, especially for technologies below 0.25 microns in which the interconnect dominates the overall timing performance

20 Statistical Timing Verification Static Timing Verification In the domain of statistical timing verification, various attempts have been made to introduce delays as random variables in timing analysis. These have relied upon Gaussian delay distributions and operators to calculate the delay distributions for the signal paths. The results are not accurate due the assumption about the distributions, and the lack of component delay correlations and false path elimination in the analysis. Statistical simulation techniques introduced in STAT! Have modeled the delays within a macromodel block as functions of basic, statistically independent fabrication process variations. As a result, accurate delay distributions and correlations have been obtained under the assumption of single input transition. In the follow-up work, a methodology for formal modeling of signal interactions has been proposed. In this approach, conservative conditions on the minimum time difference between the subsequent input changes have been derived to guarantee the validity of the single input change delay macromodels. 39 Statistical Timing Verification Static Timing Verification An approach to compute the probability distribution of the delay of a circuit, given the probability distributions for the gate and wire delays. The corresponding tool is named TrueD-S. Each node in the circuit has a set of waveforms, transition sequence with a corresponding validity region. The symbolic transition sequences are an extension of timing diagrams for symbolic simulation, while a validity region is the intersection of a set of delay constraints. The waveforms are computed starting from the primary inputs and propagating them through the logic elements. At each logic element, combining the input waveforms can give rise to as many output waveforms as the number of possible total orderings of the switching instants of the combining input waveforms. Assuming that the circuit has no false paths, only the last symbolic switching instant needs to be retained for each waveform, thus saving memory

21 Statistical Timing Verification Static Timing Verification Determining the circuit delay in the presence of correlated variations in component delays cause by fabrication process fluctuations. Under the single-stepping transition mode of operation assumption, a path is said to be sensitizable if a transition can be propagated along the path all the way from the primary input to the primary input to the primary output. In order to do so, the sideinputs at each gate along the path being sensitized must be at non-controlling values during the time that the on-path transition passes through the gate. Each such sideinput requirement implies a set of boolean and path delay constrains, which is represented symbolically. The delay of the candidate path is maximized under the correlated component delay model, such that the side-input boolean conditions and associated path delay constraints are simultaneously satisfied. The approach itself, however, is very computation intensive in the presence of long false paths since the sensitization conditions are checked of a per-path basis 41 - PITA PITA Primitive PDF Identification based Say a given circuit has a set of primitive path sets PITA maximum circuit instance delay maxdelay x p = { Π p, Π p2,..., Π (ckt) = max{delay 1 pn x ( Π p1 } ),delay x ( Π p2 ),...,delay x ( Π pn )} delayx ( Π) = min{ delayx ( π ), delayx ( π 2),..., delayx ( π π pi, 1 n The shortest path j, which determines the delay of the primitive path set Π pi at circuit instance x, is called the primitive anchor path of. Π pi )} 42 21

22 - PITA PITA Primitive PDF Identification based The PITA maximum circuit instance delay is exactly equal to the maximum circuit instance delay under the floating mode of operation The number of primitive anchor paths in a circuit is less than the number of paths in the circuit that satisfy the loose criterion and consequently also less than the number of viable paths in the circuit 43 Maximum Circuit Instance Delay PITA PITA maximum circuit delay maxdelay(c kt) = max maxdelay ( ckt) = max{maxdelay( Π maxdelay( Π) = max min {delay x x x x ( π p1 ),..., maxdelay( Π ),delay ( π pn ),...,delay When the component delays are assumed to vary independently of each other, the PITA maximum circuit delay is exactly equal to the maximum circuit delay under the floating mode of operation. For any component delay model, the PITA maximum circuit delay is exactly equal to the realizable maximum circuit delay under the floating mode of operation 1 x 2 ) x ( π n )} 44 22

23 Primitive PDF Identification PITA The PITA approach netlist T(lower bound) component delay upper bounds component delay models iterative-ssta primitive path set( ) maxdelay( ) primitive path set delay evaluator mode = critical path mode = all path maximum circuit delay maximum circuit delay critical primitive path set critical primitive path set 45 Primitive PDF Identification PITA The core of the PITA methodology is based on the iterative-ssta (iterative Signal Stabilization Time Analysis) algorithm, which is used to identify primitive path sets whose delay upper bounds are greater than some lower bound threshold value. The iterative-ssta procedure uses only the upper bounds on the component delays to identify these primitive path sets, and every time such a primitive path set is identified, the primitive path set delay evaluators is invoked which computes the maximum delay of the primitive path set using the user-input component delay models

24 Primitive PDF Identification PITA Recall that the general form of the ST-expression at a node n is : st > T Bcond {Cexpr > T } st n0 n1 n > T n... Bcond Bcond... Bcond n 01 n0 N 0 1 n1 n1n1 {...} {Cexpr {Cexpr {...} {Cexpr n01 n0 N 0 1 n1 n1 N1 n > T } n > T } n > T } Where Bcond k n0/1 represent the Boolean conditions in terms of the primary input variables such that node n may have transitions but stabilizes ultimately to a logic 0/1, and {Cexpr Tn } are of the form n0/1 k > {(delay[path i ] > T n ) (delay[path j] > Tn )...} n 47 Pessimism of PITA PITA As with all other path sensitization mechanisms which perform the analysis under a floating mode of operation assumption, PITA can be more pessimistic than an analysis done under a single stepping transition mode of operation. PITA can overestimate the signal stabilization times because hazards at a gate input can cause the gate output to stabilize earlier. Static hazard Actual stabilizing time g Stabilizing time predicted by PITA 48 24

25 Application of PITA PITA Determination of the maximum circuit delay for independent varying bounded component delays Determination of the maximum circuit delay taking into account fabrication process effects, signal propagation effects, and signal interaction effects A post-layout delay optimization scenario where critical paths need to be identified and speed up using transistor and wire resizing, interconnect re-routing, buffer insertion, etc. A post-layout timing verification scenario where critical paths are iteratively identified and re-extracted more accurately to get a precise circuit delay estimate 49 25