DESIGN AND ANALYSIS METHODOLOGIES TO REDUCE SOFT ERRORS IN NANOMETER VLSI CIRCUITS BALKARAN SINGH GILL

Transcription

1 DESIGN AND ANALYSIS METHODOLOGIES TO REDUCE SOFT ERRORS IN NANOMETER VLSI CIRCUITS by BALKARAN SINGH GILL Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Dissertation Advisor: Dr. Christos A. Papachristou Department of Electrical Engineering and Computer Science CASE WESTERN RESERVE UNIVERSITY January 2006

2 CASE WESTERN RESERVE UNIVERSITY SCHOOL OF GRADUATE STUDIES We hereby approve the dissertation of candidate for the Ph.D. degree *. (signed) (chair of the committee) (date) *We also certify that written approval has been obtained for any proprietary material contained therein.

3 Dedication to my grandfather

4 Contents Contents vi List of Tables x List of Figures xi Chapter 1 Introduction Motivation Our Approaches Analysis and Mitigation of Soft Errors in Logic Detection and Correction of Soft Errors in SRAM Analysis of Soft Errors in Clock Networks Dissertation Outline Chapter 2 Related Work Literature Survey Related Work Chapter 3 Background Radiation-induced Current Pulses Soft Errors in Logic Circuits Single Event Transient in Logic vi

5 3.2.2 Soft Delay Errors in Logic Soft Errors in SRAM Soft Errors in Clock Networks Radiation-induced clock jitter (RIJ) Radiation-induced race (RIR) Soft Errors Susceptibility of VLSI Circuits I Methodologies to Reduce Soft Errors in Logic 30 Chapter 4 Node Sensitivity Analysis for Soft Errors Introduction SEU Rate of a Node Critical Pulse Width, W path c,node Determining Critical Energy, E path c,node Probability of Inputs, P node,path, for Pulse Propagation Local Pulse Propagation Global Pulse Propagation Determining T node,path Results Reducing Soft Error Rate Chapter 5 Soft Delay Errors - Introduction Introduction Soft Delay Phenomenon Fault Modelling Active Transition Delay Model Inactive Transition Delay Model Analyzing Soft Delay Error Effects vii

6 5.4.1 Technology Scaling Effects V dd Scaling Effects Gate Fanout and β multiplier Effects Discussion Chapter 6 Node Sensitivity Analysis for Soft Delay Errors Mixed-Mode Simulations Soft Delay Error Analysis Approach Upset Rate of a Node, U node Probability of Sensitive Transitions, P node Computing T node Results and Discussion II Methodologies to Reduce Soft Errors in Memory 86 Chapter 7 Design and Analysis of Built-in Current Sensor (BICS) Introduction New Built in Current Sensor Simulation Mechanism and Results Simulation Results BICS Reliability Analysis Process, Voltage and Temperature (PVT) Analysis Power Supply Noise analysis Power Dissipation Analysis Comparisons Chapter 8 Single-word Mulitple-bit Upsets Correction in SRAM Introduction SMU Correction Approach viii

7 8.2.1 BICS for Single Event Upset Detection Multiple Bit Error Correction Mechanism Evaluating Multiple Bit Error Correction Correction of Single Error in a Data Word Correction of Single Word Multiple Errors III Soft Errors Analysis in Clock Networks 116 Chapter 9 Radiation-Induced Clock Jitter and Race Introduction Simulation Approach External Clock Nodes - Analytical Approach Internal Clock Nodes - Fully SPICE based SER Simulations Analytical Clock-SER Modelling Algorithm Wcrit calibration and modelling Timing Derating (TD) of Jitter and Race Chip Level Approach Chapter 10 Summary and Future Work Summary Future Work Bibliography 134 ix

8 List of Tables 4.1 An attenuation characterization table of an AND gate Energy characterization table for output node out of the AND gate for Figure Accuracy and run time comparisons Normalized sensitivity of nodes Reduction in the node sensitivity after applying node hardening technique Comparison between different technologies for soft delay Soft delay under load and hitting particle energy for an AND gate Accuracy and run time comparisons Normalized sensitivity of nodes Simulation results for 1 to 0 flip Simulation results for 0 to 1 flip Power dissipation for voltage and process variations Comparisons between new BICS and the BICS of [Calin et al., 1995b] 100 x

9 List of Figures 3.1 Charge creation due to the particle strike Different regions of the charge collection after the particle strike Current pulse generated due to the particle strike Soft delay error in a 4 bit ripple carry adder. Co is the carry signal SEU sensitive nodes of a SRAM cell Electrical masking for particle strike generated pulse Logic masking for particle strike generated pulse Timing masking for particle strike generated pulse Simulation setup to calculate W F F c for a flip-flop Simulation setup for the characterization of an AND gate Pulse propagation in the reverse direction from flip-flop F 1 to node N Simulation setup to inject current pulses at a node of an AND gate Local pulse propagation Global pulse propagation Latching window of a flip-flop Propagation delay (a) of a buffer in the normal operation Propagation delay (b) of a buffer due to the particle strike during the transition CMOS circuit to show the soft delay phenomenon xi

10 5.4 Timing diagram of Figure 5.3 shows the active transition case Timing diagram of Figure 5.3 shows the inactive transition case Model circuit with current source used for HSPICE simulations Collected charge versus delay for different process technologies Collected charge versus width of the glitch using for different technologies Collected charge versus delay for 0.07µm technology for different supply voltages Collected charge versus width of the glitch for 0.07µm technology for different supply voltages Collected charge versus delay for 0.07µm technology for different gate fan-outs Collected charge versus delay for 0.07µm technology for different β multiplier Collected charge versus the width of the glitch for 0.07µm technology for different gate fan-outs Collected charge versus the width of the glitch for 0.07µm technology for different β multiplier Shape of the current pulses for various hitting particle energies Flow of SDE Analysis Approach Variation of E c,node with respect to transition arrival time at the output Simulation setup for the characterization of an AND gate Saturation of E c,node Saturation of N sens T wov of a node BICS proposed in [Calin et al., 1995b] xii

11 7.2 New BICS The shape of the current pulse for different values of Q and t f Spice simulation results for 1 to 0 flip for Q = 3fC and t f = 30ps Simulation setup for the noise analysis of the BICS Types of Single Event Mulitple Upsets in SRAM Memory architecture for multiple bit error correction approach Using BICS on column power lines for upset detection SMU correction scheme Different scenarios when SEMU results in single error in a data word, these errors are corrected by ECC only Different scenarios when SEMU results in multiple errors in a data word, these errors are corrected by SMU correction approach Radiation-Induced Jitter and Race Chip level clock node upset contribution is computed by integrating the clock SER as a function of delay over the path delay distributions Calibration Methodology for defining W crit and T wov Comparison between TIDEST results and our analytical model as a function of data arrival time (margin) SER Due to clock node upsets as a function of distance to the receiver. 129 xiii

12 Acknowledgements I acknowledge my parents who have guided me all through the early years of my life that provided the foundation for this work. My grandfather will always be a symbol of inspiration for me. I would like to give my sincere appreciation to my academic advisor Prof. Christos Papachristou for his assistance and support through my difficulties. Not only have I learned much from him, it s also a pleasure to work with him. His technical and editorial advice was essential to the completion of this dissertation. His hard-working attitude has always motivated me. My thanks also go to Prof. Daniel Saab, Prof. Steven Garverick, Prof. Merat, Prof. Mehregany, and Dr. Norbert Seifert for being in the dissertation committee. They have provided valuable comments and suggestions on my research work. I am very thankful to Dr. Michael Nicolaidis and Dr. Norbert Seifert for being my industrial mentors. I am also grateful to Dr. Francis G. Wolff, who provided me with a lot of moral support and made my life in Case a very amusing and interesting one. I benefited a lot from his helpful comments and suggestions. I am deeply gratitude to my wife Kinderjit for her understanding during the past few years. Her love, support, and encouragement made this dissertation possible. I acknowledge my daughter Jaslena and my son Mehak for being without me on beautiful evenings while I was working at Case. I am also thankful to my family who provided me endless support to study at Case. xiv

13 Thanks also to all my colleagues at the Department of Electrical Engineering and Computer Science for providing a good working atmosphere. Balkaran Gill, September 08, 2005 xv

14 Design and Analysis Methodologies to Reduce Soft Errors in nanometer VLSI Circuits Abstract by Balkaran Singh Gill As process technology advances into Very Deep Sub-Micron (VDSM) level, CMOS VLSI system reliability is becoming a major concern. One of the main causes of reliability reduction is caused by charge particle strikes due to cosmic radiation which create soft errors, also referred to as Single Event Upsets (SEUs). In past technologies, this problem was limited to radiation hostile environments such as space. With VDSM designs, however, low energy particles at the ground level can cause soft errors, making CMOS circuits sensitive to atmospheric neutrons, as well as to alpha particles created by the unstable isotopes that can be found in materials of a chip. Soft errors are a major problem in mission critical applications where reliability is the main concern over performance and cost, such as heart defibrillators, avionics, etc. Our research focus is to provide design and analysis methodologies that reduce soft error in CMOS VLSI circuits implemented in nanometer process technologies. From the designer s point of view, a VLSI system consists of combinatorial logic, memory, and clock networks. We propose several design and analysis methodologies to reduce soft errors in logic, memories (SRAM), and clock networks. For logic, we xvi

15 pursue two different tracks: 1) Nodes sensitivity analysis and mitigation for soft errors in CMOS logic. 2) Soft Delay errors effects and analysis. For memories, we have developed an efficient Built-in Current Sensor (BICS) for the detection and localization of SEUs. We use a combination of BICS and ECC for single as well as multiple errors correction in SRAM. For the clock networks, we have analyzed the radiation-induced clock jitters and race. Our results for various test circuits show that the accuracy achieved by our analysis approaches is close to Spice and, at the same time, they are several orders of magnitude faster than Spice. We reduced the sensitivity of nodes by applying electrical hardening technique on highly sensitive nodes which were determined by our approaches. The reliability analysis of our new BICS shows that it can work under process, voltage, and temperature variations as well as in harsh noise environments. xvii

16 Chapter 1 Introduction Single Event Upsets (SEUs) in modern VLSI systems are a major reliability concern. These upsets originate from two primary sources: cosmic ray particles occurring in the space environment and alpha particles emitted from the radioactive decay of uranium and thorium impurities located within the chip itself such as the silicon die, interconnects, and ceramic packaging. Soft errors due to SEUs have been a known problem affecting semiconductor memories for quite some time [May and Woods, 1979, Granlund et al., 2003]. However, due to faster clock rates and shrinking process technologies SEUs are now affecting CMOS logic [Shivkumar et al., 2002, Nguyen and Yagil, 2003, Mohanram and Touba, 2003, Dodd and Massengill, 2003, Zhao et al., 2004, Baze and Buchner, 1997, Normand, 1996b]. 1.1 Motivation One of the main causes of the reliability reduction in VLSI circuits is the charged particle strikes that create soft errors. In past technologies, this problem was limited to the radiation hostile environments such as space. However, as the process technology advances into Very Deep Sub-Micron (VDSM) level, the charge stored at the circuit nodes decreases dramatically due to shrinking transistor geometries and 1

17 decreasing supply voltages. Thus, low energy particles at the ground level can cause soft errors. It is to be noted that the occurrence of the low energy particles is much higher than the high energy particles. Soft errors are a major problem in mission critical applications where the reliability is the main concern over the performance and the cost such as implantable medical devices, heart defibrillators, avionics, etc. The Soft Error Rate (SER) of a node in a logic circuit is the failure rate of the node due to SEUs. The SER of the individual nodes is non-uniform in nature as it depends on the transistor strength, the capacitive load at the transistor node, V dd value, temperature, etc. and furthermore, the probability of the input state of the circuit which sensitizes distinct data paths. Thus, the SER of the transistor nodes is a measure of the node sensitivity in a circuit. The SER of a node can be reduced by using node (circuit) hardening techniques but it can result in unacceptable design overhead. Hence, by analyzing and quantifying SER of the node, we can employ appropriate techniques to reduce the SER of highly sensitive nodes which will potentially yield a lower overall circuit SER. Traditional soft error analysis approaches use circuit simulators such as Spice which perform very accurate analysis but are intractable for large circuits. So, there is a need for fast, accurate, and efficient analysis techniques which can be used at the chip level. Memories occupy the largest block area in modern ICs. In addition, memories are more sensitive to failures than logic, and this includes both hard and soft (transient) failures. Thus memories involve the largest amount of failures in modern ICs, becoming the major cause for reliability problems. Moreover, multiple bit upsets in single memory data word are increasing. 2

18 To maintain acceptable reliability levels in memories, Error Correcting Codes (ECC) are often used to detect and correct SEUs. But ECCs may entail significant area, performance, and power dissipation penalties. Also, ECC only detects and corrects the error at the time the faulty word is being read, and not when it occurs. In large memory systems, there can be a long latency between the occurrence of the SEU and the error correction, which can cause accumulation of SEUs that can invalidate the error detection and correction capabilities of ECC. So, there is need for new techniques which can correct errors as soon as they occur with capabilities to correct multiple bit errors. 1.2 Our Approaches Our research focus is to provide design and analysis methodologies to reduce soft errors in CMOS VLSI circuits implemented in nanometer process technologies. From the designer s point of view, a VLSI system consists of combinatorial logic, memory, and clock networks. We propose several design and analysis methodologies to reduce soft errors in logic, memories (SRAM), and clock networks. For logic, we pursue two different tracks: 1) Node sensitivity analysis for soft errors in CMOS logic [Gill et al., 2005d]. 2) Soft Delay error effects and analysis [Gill et al., 2004, Gill et al., 2005c]. For memories, we have developed an efficient Built-in Current Sensor (BICS) for the detection and localization of SEUs [Gill et al., 2005b]. We use a combination of the BICS and Error Correcting Codes (ECC) for single as well as multiple error correction in SRAM [Gill et al., 2005a]. For the clock networks, we have analyzed the radiation-induced clock jitters and race [Seifert et al., 2005]. In the following, we describe briefly our proposed approaches for logic, SRAM, and clock networks. 3

19 1.2.1 Analysis and Mitigation of Soft Errors in Logic To analyze soft errors in logic, we have developed an analysis approach to determine the sensitivity of the circuit nodes to soft errors. We, then use a node hardening technique to reduce soft errors. We have also characterized soft delay errors and developed a node sensitivity metric to quantify these errors in logic circuits. In the following, we discuss briefly these approaches. Node Sensitivity Analysis for Soft Errors - Pulses generated due to the energetic particles strike at sensitive nodes in CMOS circuit can propagate through the functional sensitized paths and latch into the output flip-flops, potentially causing soft errors. The node sensitivity depends on three masking effects: electrical, logic, and timing. We have developed an approach for computing the soft error susceptibility of nodes in large CMOS circuits at the transistor level [Gill et al., 2005d]. A technique is being used to compute the electrical masking of circuit nodes from the gate characterization tables and inverse pulse propagation. We generate these tables for every gate used in the design using Spice simulations for 100nm process technology. We also provide a technique to compute the logic masking of transistor nodes using an Automatic Test Pattern Generation (ATPG) tool. Our results show that this approach provides Spice like accuracy but it is several orders of magnitude faster than Spice. We used this approach to report sensitive nodes in ISCAS85 circuits. This approach can be used to analyze the vulnerability of circuits to (SEUs) at the chip level. One of the advantages of analyzing the node sensitivity is that the failure rate of the circuit due to soft errors can be predicted and then reduced by applying appropriate techniques to harden highly sensitivity nodes. This is demonstrated for two test circuits. Our approach has less time complexity as compared to approaches proposed in [Zhao et al., 2004] and [Mohanram and Touba, 2003]. 4

20 Soft Delay Error Effects - Soft delay errors occur when a highly energetic charged particle strikes at a sensitive transistor node in a combinational logic circuit, introducing an additional delay on the signal path which results in erroneous data latchups. The existence of soft delay errors was observed by us and reported for the first time in [Gill et al., 2004]. We propose a systematic approach for SDE analysis of CMOS circuits [Gill et al., 2005c]. A mixed mode circuit simulation technique, which uses two and three dimensional transistor models, was developed for the characterization of the SDE. We define a metric to compute the sensitivity of circuit nodes to SDEs and describe a step by step procedure to compute it. The node sensitivity metric is based on: a) the upset rate of the node. b) The critical energy of the particle. c) The probability of the error propagation from the node to an observable circuit output. d) The timing window of vulnerability of the node within a clock cycle. Our key contributions are: 1) a technique for logic cell library characterization to create lookup tables which are then used to determine the critical energy of the particle. 2) Deriving a fast saturating averaging value of the critical energy which helps to reduce the simulation time. 3) A technique to determine the probability of the error propagation. The lookup table technique avoids time consuming Spice simulations which otherwise would be used to compute the critical energy. Our technique is orders of magnitude faster than using Spice based analysis with accuracy close to Spice. We provide statistical distributions of node sensitivity for various ISCAS85 benchmark circuits and two adders, implemented in 100 nm process technology. This technique is complementary to the existing glitch analysis techniques used for traditional soft errors in CMOS logic in the sense that they both provide comprehensive reliability analysis. By analyzing and determining the node sensitivity to SDE, node 5

21 hardening techniques can be applied to protect selected highly sensitive nodes Detection and Correction of Soft Errors in SRAM For the detection of soft errors in memory, we have developed a Built-in Current Sensor (BICS). We use combination of BICS and Error Correcting Codes (ECC) for single as well as multiple error correction as described in the following. BICS for Soft Errors Detection in SRAM - A new BICS which was designed for current CMOS process (100nm) operates reliably under wide voltage, temperature, and process variations, as well as stringent noise conditions [Gill et al., 2005b]. At the same time, the new BICS is also smaller than the previously proposed in [Calin et al., 1995b] and dissipates less power. Another important characteristic is that the voltage drop induced by the new BICS on the Vdd and Gnd lines is only 7.5mV and 8.5mV, respectively. Thus, the new BICS will not affect the noise margins of the memory, which is not the case for the old one. These characteristics make our BICS approach practical, while this is not a case in earlier BICS approaches monitoring the logic parts. Single-word Multiple Errors Correction in SRAM - As technology continues scaling, the smaller device size and high precision manufacturing techniques allow placing a large number of memory cells onto a small die area. The separation distance between two adjacent cells is decreasing as the cell density increases. Reducing the separation distance implies that a single particle strike can cause multiple bit upsets also referred to as Single Event Multiple-bit Upsets (SEMU). The Single-word Multiple-bit Upsets (SMU) occurs when these events cause double or more upsets in a memory data word. SMU are becoming a reliability concern in modern semiconductor memories as Hamming Single Error Correction and Double Error Detection 6

22 (SEC/DED) codes will not be suitable for these kinds of errors. We have introduced an approach for SMU correction in SRAM [Gill et al., 2005a] which uses a combination of BICS and SEC/DED codes. The BICS is used with memory columns for on-line detection of upsets. When the upset is detected by the BICS, an immediate error correction is performed by the ECC. If ECC flags for an uncorrectable error i.e. double or more errors in single word, then the information from BICS is used to correct the erroneous bits Analysis of Soft Errors in Clock Networks This study assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs [Seifert et al., 2005]. Two basic upset modes are identified: radiation-induced clock jitter (RIJ) and radiation-induced race (RIR). Our simulation results indicate that RIR cannot be neglected at the chip-level. We have developed analytical models to analyze RIJ and RIR in the clock networks. 1.3 Dissertation Outline We have divided our work into three multi-chapter parts. Design and analysis methodologies to reduce soft errors in: logic are in part I. memory are in part II. clock networks are in part III. Chapter 2 presents a literature survey for soft errors in VLSI circuits and existing related works. 7

23 In chapter 3, we discuss the background of soft errors. The radiation effects in logic, memory, and clock networks are discussed. The increasing susceptibility of VLSI circuits to soft errors is described. Chapters 4, 5 and 6 are covered in part I. Chapter 4 discusses our proposed approach for node sensitivity analysis to soft errors. A node sensitivity metric is defined and a step by step procedure is describe to compute it. The approach accuracy and efficiency are discussed in the results section. Node sensitivity distributions are provided for various ISCAS85 circuits. Chapter 5 presents the soft delay error effects in logic circuits. We discuss our developed models to analyze soft delay error effects of technology scaling, V dd scaling, fanout and transistor strength variations. Chapter 6 discussed our approach for soft delay error analysis in logic. We define a node sensitivity metric for soft delay error analysis and describe a systematic approach to compute it. Results are compared with Spice based analysis approaches for accuracy and time complexity. Node sensitivity distributions are provided for various ISCAS85 circuits. Part II consists of chapters 7 and 8. In chapter 7, we present design of a Built-in Current Sensor (BICS). BICS Spice simulation results are provided. The BICS reliability analysis techniques and results are also discussed and compared with existing BICS. Chapter 8 presents our approach of single as well as multiple error correction in SRAM. The architecture of memory which employs BICS and ECC for multiple 8

24 error correction is described. In depth error correction analysis for various scenarios is presented. Part III covers (in chapter 9) the modelling and an analysis technique for radiation induced jitters and race in the clock networks. Chapter 10 concludes this dissertation and discuss the future work. 9

25 Chapter 2 Related Work This chapter covers the literature survey for soft errors and the work related to our approaches. We discuss various simulation methodologies presented in the open literature for the soft error characterization. These methodologies include device and circuit simulations. We also describe technology scaling effects on the reliability of VLSI circuits due to soft errors. In the related work section, we discuss existing approaches in contrast to our approaches. 2.1 Literature Survey A fundamental, error producing physical mechanism for α-particle induced soft errors was provided by [May and Woods, 1979]. They described physical models to determine α-particle effects. A materials analysis was performed to confirm the source of the α-particles. They also provided error rate factors and a methodology to determine soft error rate in memory. In [II, 1996], a tutorial for soft errors by α-particles was presented. The basic physics for α-particle emissions, α-particle emission rates in packaging materials, analysis of packaging materials including chemical, radioactive, and the device sensitivity analysis were discussed. An α-particle source-drain pene- 10

26 tration effect (ALPEN) phenomena in VLSI was presented in [Takeda et al., 1989]. Various effects on the charge collection were discussed. The cosmic rays induced upsets at the ground level in random access memory of large computers have been reported in [Normand, 1996b]. They found that the majority of the upsets are caused by the atmospheric neutrons at the ground level. In [Heileman et al., 1989a], single event upset (SEU) experiments using Ion Beams were presented. They performed experiments for various devices fabricated using MOSIS 3 µm CMOS p-well process. In the experiments, devices were irradiated with 5 MeV boron ions and 5 MeV α-particles. The transient current waveform, generated due to particle strikes, parameters like rise time, decay time, peak current amplitude, time of peak current, and total collected charge were extracted using high bandwidth super-conducting oscilloscopes. In [Dodd and Sexton, 1995], the critical (minimum) charge concept for CMOS SRAM using the combination of device and circuit simulations was described. They considered the external circuit loading to accurately model the charge collection effect. A mixed-mode simulation approach for SRAM cell was presented in [Detcheverry et al., 1997]. They also quantify the critical charge concept. They reported that the critical charge will drastically decrease in the next SRAM generations. The main reasons for the critical charge drop are due to decrease in the supply voltage, the gate oxide thickness, and the dimensions of the transistor. They also reported that the sensitivity to SEUs of the NMOS transistor is more than for the PMOS transistor. A similar study for the transistor sensitivity to SEUs were discussed in [Castellani-Coulie et al., 2003]. In addition, they found that in some cases, the off-pmos transistor sensitivity was to be similar to the off-nmos transistor. An entire SRAM cell simulations using three dimensional device domain were presented in [Katz et al., 1998]. They compared the mixed-mode simulations with the full-cell device simulations. They found that the accuracy of the mixed- 11

27 mode simulations was close to the full-cell device simulations in most of the cases except when coupling effects between two transistors occur. They suggested using full-cell device simulations for modern technologies for accurate SEU investigations. In [Yamaguchi et al., 2004], they proposed circuit models to evaluate SEU tolerance. They also presented analytical expressions for the tolerance of SRAM devices. A Spice based analysis for SEU sensitivity of a 6-Transistor SRAM cell was discussed in [Alles, 1994]. They used the transistor constructed using fully depleted SOI CMOS technology. They also discuss techniques to reduce SEU sensitivity. [Dai et al., 1999] discussed a modelling and simulation approach for α-particle soft error rate in Sub- 0.25µm CMOS technology. Soft errors in SRAM due to internal ion tracks generated by nuclear reactions were discussed in [Palau et al., 2001]. They observed that the critical charge changes with the geometry and location of the particle track. The cosmic rays induced soft errors, especially due to neutrons, were discussed in [Srinivasan et al., 1994b, Haucha et al., 2000, Dodd et al., 2002]. The particle strike at angle and the charge collection mechanism was discussed in [Dodd et al., 1997]. A study of transient current induced by heavy ion in NMOS/SOI transistors was conducted in [Colladant et al., 2002]. The effect of technology scaling on the soft error rate (SER) of combinational logic was presented in [Shivkumar et al., 2002]. Their models predicted that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to They presented a methodology to determine SER of logic circuits and SRAM. For the calculations of the SER of logic circuits, they considered various masking effects on the SEU generated pulses. The SER of VLSI circuit s increases with the supply voltage down scaling was reported in [Cohen et al., 1999]. The SER increasing in the new generating of SRAM was discussed in [Granlund et al., 2003]. The SRAM sys- 12

28 tem failure rate increasing with technology scaling was discussed in [Baumann, 2002]. The author concluded that the error correction using error correcting codes is the best means of reducing memory soft errors and also discussed the need for new soft error mitigation techniques for the logic. The relationship between the technology scaling and the atmospheric neutron SER was described in [Hazucha and Svensson, 2000]. Two approaches were used to determine the atmospheric neutron SER. The first approach was based on empirical models derived from measurements and device simulations. The second approach was based on theoretically modified burst generation rate (MBGR) model. They observed that the SER on per bit bases decreases linearly with decreasing the feature size. However, as the number of bits per chip are increasing then the SER is increasing linearly with decreasing the feature size. Reasons for decreasing the SER per bit are decreasing the collected charge in highly doped substrates, smaller potential difference on parasitic drain diodes, and reduced collection area, i.e. the size of nodes. SER for SRAMs constructed using SOI and Bulk devices below 130 nm process technology was discussed in [Roche et al., 2003]. They reported that the SER of SOI devices is five times less than the SER of Bulk devices for both alpha particle and neutron sources. They showed the data for various variations on the SER like the supply voltage, deposited charge, and the gate length. Reduction in the SER of partially depleted SOI devices against the Bulk devices was reported in [Hareland et al., 2001]. The technology scaling trend for SEUs in SRAM was discussed in [Dodd et al., 1996]. They used three dimensional device simulations to study the technology trend. They found that in deep sub-micron technologies, the mechanism of charge collection can occur at late times which reduces the hardness of radiation-hardened technologies. The impact of technology scaling on the SER of commercial microprocessors was discussed in [Seifert et al., 2002]. They found that the overall chip level 13

29 SER is dominated by the contributions from cache. But when ECC protection is used then the main SER contribution is from core logic. Due to the introduction of the flip-chip packaging, the SER caused by α-particle increases because the α-particle flux increases. The chip SER dependence on the clock frequency and the circuit design techniques were also discussed. The decrease in the neutron-induces SER was described. The SER of caches increases while core logic decreases with increasing the clock frequency was reported in [Seifert et al., 2001]. The comparisons between error rates in combinational and sequential logic were discussed in [Buckner et al., 1997]. A study of SEU generated transient pulse attenuation in combinational logic has been conducted in [Baze and Buchner, 1997]. Spice circuit analysis, heavy ion test, and pulsed, focused laser simulations were carried to examine the SEU generated pulse. After comparing the laser data and Spice simulations, they suggested that Spice can be used to obtain reasonable simulations of heavy ion pulse attenuation. A structure was described in [Nicolaidis and Perez, 2003] for measuring the duration of SEU generated pulses during the radiation tests. Their method can be used to calibrate/validate three dimensional simulations and laser beam experiments. An approach for SER estimation and solutions is described in [Nguyen and Yagil, 2003]. They considered SER in state of the art microprocessor design. The SER in various components of a microprocessor like machine state and non-machine state, latches, domino gates, static gates etc. was considered. The Failure in Time (FIT) rate estimation using derating factors was described. They also provided SER solutions. A unique and comprehensive computer program called Soft Error Montecarlo Model (SEMM) was introduced in [Srinivasan et al., 1994a, Murley and Srinivasan, 14

30 1996]. SEMM is used for modelling of cosmic ray SER and chip alpha radiation SER. A study for the propagation of SEU generated transient pulses in combinational logic was conducted in [Liden et al., 1994]. They proposed that a voltage pulse may only propagate through a limited number of transistor stages and still be latched. In [Maheshwari et al., 2003, Maheshwari et al., 2004] techniques for SER estimation and transient fault sensitivity analysis and reduction in VLSI circuits were discussed. They compared different methods for the SER estimation. They also discussed fault tolerance techniques to reduce SER. A gate level transient fault simulator was presented in [Cha et al., 1993, Dharchoudhury et al., 1994]. A logic level model for α-particle hits in logic was described in [Cha and Patel, 1993]. They developed an analytical model for the pulse propagation in the logic circuits. Analysis and simulation of transient faults were discussed in [Kaul et al., 1991, Yang and Saleh, 1992]. Techniques to determine the sensitivity of circuit nodes to soft errors have been described in [Mohanram and Touba, 2003, Maheshwari et al., 2005, Zhao et al., 2004, Gill et al., 2005d]. The Timing Vulnerability Factor (TVF) of sequentials has been discussed in [Seifert and Tam, 2004]. The TVF is also known as the fraction of time a node or device is susceptible to upsets. They investigated the relationship between TVF and the propagation delay of the combinational logic paths. A methodology to compute Architectural Vulnerability Factors (AVF) for microprocessor was described in [Mukherjee et al., 2003]. The AVF is the probability that a fault in a device will be observed by the system, i.e. system failure occurs. In-flight measurements of SEUs in SRAM caused by atmospheric radiation environment at aircraft flight altitudes are performed in [Johansson et al., 1998, Olsen 15

31 et al., 1993, Normand, 1996a]. Different upset rates were observed on various latitudes due to different neutron fluxes. The atmospheric neutron flux variations with altitude, latitude, and solar activity were reported in [Normand and Baker, 1993]. The SEU rate variations due to latitude variations over a wide range of geographical locations were also reported. The single event effect measurements in space electronics were conducted in [Dyer et al., 1996]. The comparisons between SER sensitivity of Bulk and SOI devices in the terrestrial neutron environment were discussed in [Baggio et al., 2004]. The cosmic radiation effects on implantable devices were discussed in [Bradley and Normand, 2004]. They observed SEU effects in cardiac defibrillators. Neutron induced single word multiple bit upset and characterization of multibit soft errors in SRAM were discussed in [Koga et al., 1993, Musseau et al., 1996, Johansson et al., 1999, Maiz et al., 2003]. Three dimensional simulations for characterization of multiple bit upsets in silicon devices were described in [Dodd et al., 1994]. SRAM and SRAM-based field programmable gate array (FPGA) technologies have been tested for radiation effects [MacQueen et al., 1999, Ohlsson et al., 1998, Katz et al., 1998, Katz et al., 1997]. These tests have concentrated on singleevent effects, which are the most important for space applications. Relationship between soft error rate and supply voltage of SRAM and SRAM-based FPGAs is shown in [Hazucha et al., 1998]. In [Wang et al., 1999, Katz et al., 1994, Alfke and Padovani, 1998, Lum and Vandenboom, ], several techniques are used to make radiation-hardened version of FPGAs. Unfortunately, the devices available are too slow and gate capacity is also very small. 16

32 Fault tolerant design techniques to reduce errors in memories were discussed in [F J Aichelmann, 1984, Sarrazin and Malek, 1984]. Memory design using error correcting codes to reduce soft errors have been discussed in [Furutani et al., 1989, Kalter et al., 1990, Stapper et al., 1991, Mazumder, 1992]. Time redundancy based soft error detection schemes in logic circuits were proposed and discussed in [Nicolaidis, 1999, Anghel and Nicolaidis, 2000, Zhao et al., 2002]. Soft error reduction and masking techniques were discussed in [Mavis and Eaton, 2002, Weaver et al., 2004, Krishnamohan and Mahapatra, 2004]. An on chip dynamic power supply current testing scheme has been proposed in [Liu et al., 1998, Liu and Makki, 1998]. It uses I DDT to detect functional faults in CMOS SRAM. Using this technique, the authors have reduced test lengths and improved test fault coverage for SRAM test, however, transient faults cannot be detected. Current sensing techniques have been proposed in [Nicolaidis et al., 1993, Vargas and Nicolaidis, 1994, Calin et al., 1995b, Calin et al., 1995a, Gill et al., 2005b]. These techniques use Built-In Current Sensor (BICS) circuit to detect transient faults (single event upsets) and, at the same time, they employ single-parity bit per RAM word for error correction. These BICS are used at the end of every SRAM column to detect transient faults in the SRAM. Techniques for concurrent error detection in logic using current sensing were proposed in [Tsiatouhas et al., 2001, Tsiatouhas et al., 2002]. Circuit node hardening techniques were discussed in [Karnik et al., 2002, Zhou and Mohanram, 2004]. The trade off between the transient fault tolerance and power 17

33 consumption was discussed in [Maheshwari et al., 2005]. Design and analysis of soft error hardened latches was described in [Omana et al., 2003, Krishnamohan and Mahapatra, 2005]. A study for the characterization and modelling of soft errors in CMOS process was conducted in [Dodd and Massengill, 2003, Karnik et al., 2004]. 2.2 Related Work There are few approached related to our node sensitivity analysis approach. Our approach is very efficient and highly accurate which enables us to use this approach at the chip level for the Soft Error Rate (SER) analysis. The SER of nodes can be computed using Spice simulations of the circuits as discussed in [Maheshwari et al., 2005] but for large circuits, it can be intractable. The Spice simulation time increases exponentially with increasing the number of gates in a circuit. In [Mohanram and Touba, 2003], an approach for reducing the soft error failure rate in logic circuits by applying a partial protection technique based on node sensitivity analysis was proposed, but an efficient methodology for node sensitivity analysis was not developed. Their approach uses Spice simulations to compute the SER of circuit nodes which can be very time consuming in large circuits. The compound noise (cross talk, ground bounce, substrate coupling noise, radiation induced noise) effects on the gate nodes were analyzed [Zhao et al., 2004] but the details of SEU pulse propagation, latching and SER of transistor nodes were not described. 18

34 The work in [Calin et al., 1995b], uses a BICS that induces a 300mV voltage drop on the V dd and 400mV on the Gnd lines. This sensor was designed with an old technology and its operation was not validated for voltage, temperature and process variations and for the different shapes of current pulses. We developed a new BICS which is designed for current CMOS process (100nm), operates reliably under wide voltage, temperature, and process variations, as well as stringent noise conditions. At the same time, the new BICS is also smaller than the previous one, and dissipates less power. Another important characteristic is that the voltage drop induced by the new BICS on the V dd and Gnd lines is only 7.5mV and 8.5mV, respectively. Thus, the new BICS will not affect the noise margins of the memory, which is not the case for the old one. 19

35 Chapter 3 Background In this chapter, we discuss the origin of the radiation induced errors in VLSI circuits. First, we discuss the charged particle induced current pulses at the sensitive nodes of the circuits and then, the soft error mechanism due to these current pulses in logic, memory, and the clock networks. 3.1 Radiation-induced Current Pulses Transient errors in the CMOS circuits can be caused by the spikes on the power supply lines due to the poor voltage regulations, by noise introduced due to switching signals, and by the radiations. These transient errors are called soft errors as they don t permanently damage the device. By using suitable filtering and shielding in a design, most of the soft errors can be suppressed except the ones caused by the radiations as they have different origin. Two primary sources of the radiation induced upsets are: cosmic ray particles occurring in the space environment and alpha particles emitted from the radioactive decay of uranium and thorium impurities located within the chip itself such as the 20

36 silicon die, interconnects, and ceramic packaging. Cosmic particles in the form of neutrons and protons can collide with silicon nuclei in the chip and fragment some of them, producing α-particles and other secondary particles. These particles can travel in any direction within the chip with quite high energies. They produce current pulses by penetrating through p-n junctions and creating electron-hole pairs, which are effectively collected by opposite charged nodes. These current pulses result in signal degradation. Figure 3.1: Charge creation due to the particle strike. Fig. 3.1 shows penetration of a charge particle into a silicon chip and generation of the electron-hole pairs. One electron-hole pair is created per 3.6eV loss of the particle energy. The charge collection occurs when the generated electrons and holes drift to the opposite electric field into the the depletion region of the p-n junction. The charge collection occurs almost instantly, initially into the depletion region and then into funnelling and diffusion. 21

37 Single particle hit +V Depletion region Diffusion L L c P Charge Funneling substate Figure 3.2: Different regions of the charge collection after the particle strike. Fig 3.2 shows the charge collection, in three regions: depletion region, funnelling and diffusion, process following a particle strike. A high electric field is present in the equilibrium depletion region, so electrons-holes generated in this region are swept out rapidly. Charges generated beyond the depletion region are collected by diffusion. Funnelling occurs when the junction s depletion layer is temporarily distorted into the low-doped side by the ionizing track (as shown in Fig. 3.2). Charge funnelling plays an important role in the charge collection process. The time scale for charge collection via funnelling is on the order of 0.1ns. [McLean and Oldham, 1982] and [Oldham and Mclean, 1983] have explained this process in terms of an effective funnel length L c such that all charge generated by the incident particle over the distance L c is collected rapidly. Charges generated beyond the equilibrium depletion region width can be collected by diffusion, particularly when the end of the track is in the region within a diffusion length L of the depletion region edge. The time scale for charge collection via the diffusion region is on the order of several minority-carriers life times (tens of nanoseconds for GaAs; microseconds for Si) [Murley and Srinivasan, 1996, Hazucha et al., 1998, Anghel and Nicolaidis, 2000, Messenger, 1982, Vargas and Nicolaidis, 1994, Srour and Mcgarrity, 1988]. 22

38 The charge collection due to the drift of minority carriers in the depletion region and funnelling and diffusion causes a current pulse into an associated terminal. Fig. 3.3 represents the shape of the current pulse generated by the particle strike. The duration and the amplitude of the current pulse depend on the striking particle energy, the transistor strength, the load capacitance, and the V dd value. This pulse can have positive or negative magnitude depending on whether the particle hits at the drain of the NMOS or PMOS transistor. For transient simulations of the circuit for SEUs, the charge collection process is accounted for in our simulations by a current source connected between the circuit node and its substrate [Murley and Srinivasan, 1996, Hazucha et al., 1998, Anghel and Nicolaidis, 2000]. Current Depletion Region Plus Charge Funneling Diffusion Time(ns) Figure 3.3: Current pulse generated due to the particle strike. 23