Design for Testability & Design for Debug
|
|
- Andrew Carson
- 5 years ago
- Views:
Transcription
1 EE-382M VLSI II Design for Testability & Design for Debug Bob Molyneaux Mark McDermott Anil Sabbavarapu EE 382M Class Notes Foil # 1 The University of Texas at Austin
2 Agenda Why test? Scan: What is it? What is it good for? Snapshot! : Debug Scanout Embedded Memory Testing JTAG Summary EE 382M Class Notes Foil # 2 The University of Texas at Austin
3 Why Test? EE 382M Class Notes Foil # 3 The University of Texas at Austin
4 The Manufacturing Process is Imperfect EE 382M Class Notes Foil # 4 The University of Texas at Austin
5 The Manufacturing Process is Imperfect EE 382M Class Notes Foil # 5 The University of Texas at Austin
6 The Manufacturing Process is Imperfect EE 382M Class Notes Foil # 6 The University of Texas at Austin
7 The Manufacturing Process is Imperfect EE 382M Class Notes Foil # 7 The University of Texas at Austin
8 Test Techniques Functional: Make it do what it does. Structural: Divide and conquer EE 382M Class Notes Foil # 8 The University of Texas at Austin
9 Functional Test Does my chip execute all architectural instruction sequences? In the presence of all possible data streams? EE 382M Class Notes Foil # 9 The University of Texas at Austin
10 Structural Test Does SPC1 do its job? Does MCU do its job? Still checking functionality but divide and conquer activity is taking place. EE 382M Class Notes Foil # 10 The University of Texas at Austin
11 Structural Test Do the NOR gates do their job? F1 Does the AND gate do its job? F2 A B C D E F G H F5 F3 F6 Still checking functionality but divide and conquer activity is taking place. F4 EE 382M Class Notes Foil # 11 The University of Texas at Austin
12 Structural Test Thesis If we can prove every gate in the part functions then we can conclude that the part works. Corollary Structural Scan But it makes most sense. EE 382M Class Notes Foil # 12 The University of Texas at Austin
13 Basics of Scan EE 382M Class Notes Foil # 13 The University of Texas at Austin
14 Fault Models Stuck-At Faults Bridging/break Faults Transistor Stuck-On/Open Faults Functional Faults Memory Faults Delay Faults Transition Faults State Transition Faults VLSI Testing Fault model.7 NCKUEE-KJLEE
15 Single Stuck-At Faults Test Vector 0 1 Faulty Response Fault-free Response 0 1/ /0 stuck-at-0 Assumptions: Only one line is faulty. (Why?) Faulty line permanently set to 0 or 1. Fault can be at an input or output of a gate. VLSI Testing Fault model.8 NCKUEE-KJLEE
16 Single Stuck-at Faults # single stuck-at fault sites in a Boolean gate circuit = #PI + #gates + # (fanout branches) Example: A 4-NAND XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults a b c d e f g 1 h i j k 1 z How many faults? VLSI Testing Fault model.9 NCKUEE-KJLEE
17 Multiple Stuck-At Faults Several stuck-at faults occur at the same time - Important in high density circuits For a circuit with k lines - There are 2k single stuck-at faults - There are 3 k -1 multiple stuck-at faults ATPG algorithms for multiple s-a-faults are much more complex and not as well developed VLSI Testing Fault model.10 NCKUEE-KJLEE
18 Why Single Stuck-At Faults? Complexity is greatly reduced. Many different physical defects may be modeled by the same logical single stuck-at fault. Single stuck-at fault is technology independent. Can be applied to TTL, ECL, CMOS, etc. Single stuck-at fault is design-style independent. Gate Arrays, Standard Cell, Custom VLSI Even when single stuck-at fault does not accurately model some physical defects, the tests derived for these faults may still be effective for these defects. Single stuck-at tests cover a large percentage of multiple stuck-at faults. VLSI Testing Fault model.11 NCKUEE-KJLEE
19 Bridging Faults Two or more normally distinct points (lines) are shorted together - Logic effect depends on technology - Wired-AND for TTL A f A f B g B g - Wired-OR for ECL A f A f B g B g - CMOS? VLSI Testing Fault model.12 NCKUEE-KJLEE
20 Feedback Bridging Faults Input C Output Can cause oscillation or latching (additional memory) Consequences: - The shorted signal lines form wired logic so the original logic function is changed - The circuit may become unstable if unwanted feedbacks exist Applying opposite values to the signal lines being tested to test these faults VLSI Testing Fault model.13 NCKUEE-KJLEE
21 CMOS Transistor Stuck-On 0 IDDQ? stuck-on Transistor stuck-on may cause ambiguous logic level. depends on the relative impedances of the pull-up & pull-down networks When input is low, both P and N transistors are conducting causing increased quiescent current, called IDDQ fault. VLSI Testing Fault model.14 NCKUEE-KJLEE
22 CMOS Transistor Stuck-OPEN Transistor stuck-open may cause output floating Can turn the circuit into a sequential one (temporarily keep the previous value) Stuck-open faults require two-vector tests: initialiation and test vectors 0 stuck-open? = previous state initialization vector / 00 test vector stuck-open memory behavior VLSI Testing Fault model.15 NCKUEE-KJLEE
23 (Line) Break Faults Can be on the line between two gates or within one gate. Usually resulting in floating. May require two or more patterns to detect a break fault. IDDQ X X X X VLSI Testing Fault model.16 NCKUEE-KJLEE
24 Functional Faults Fault effects modeled at a higher level than logic for function modules, such as -- Decoders -- Multiplexers -- Adders -- RAM -- ROM -- CPU (instruction set) -- Cache memory VLSI Testing Fault model.17 NCKUEE-KJLEE
25 Functional Faults of Decoder f(l i /L j ): Instead of line L i, Line L j is selected f(l i /L i +L j ): In addition to L i, L j is selected f(l i /L j +L k ): Instead of L i, L j and L k are selected f(l i /0): None of the lines are selected A B 2-bit Decoder AB AB AB AB VLSI Testing Fault model.18 NCKUEE-KJLEE
26 Memory Faults Parametric Faults - Output Levels - Power Consumption - Noise Margin - Data Retention Time Functional Faults - Stuck-at Faults in Address Register, Data Register, and Address Decoder - Cell Stuck Faults - Adjacent Cell Coupling Faults - Pattern-Sensitive Faults VLSI Testing Fault model.19 NCKUEE-KJLEE
27 Memory Faults (Cont.) Pattern-sensitive faults: the presence of a faulty signal depends on the signal values of the nearby points - Most common in DRAMs x b 0 a 0 a=b=0 x=0 a=b=1 x=1 Adjacent cell coupling faults - Pattern sensitivity between a pair of cells VLSI Testing Fault model.20 NCKUEE-KJLEE
28 Delay Fault Model Assumption - Some physical defects, such as process variations, make some delays in the CUT greater than some defined limits Two delay fault models are typically used - Gate delay fault model (a local delay fault model) - Path delay fault model (a global delay fault model) 5ns Regs. D CUT Regs. clk normal clk faulty VLSI Testing Fault model.21 NCKUEE-KJLEE
29 What is a test? Primary inputs (PI) Fault activation Combinational circuit X 1 0 1/ X Stuck-at-0 fault Fault effect 1/0 Primary outputs (PO) Path sensitization 2
30 Primary inputs (PI) What is a test? Test Vector Fault activation Combinational circuit X 1 0 1/ X Stuck-at-0 fault Fault effect 1/0 Primary outputs (PO) Path sensitization Test Response 3
31 Example! Generate a test for e stuck-at-1 Sa1 a b c e g d f 4
32 Example! 1) Activate the fault a 0 b c e g d f 5
33 Example! 1) Activate the fault a 0/1 b c e g d f 6
34 Example! 1) Activate the fault Fault Effect a 0/1 b c e g d f 7
35 Example! 1) Propagate the fault effect a b c 0/1 e 0/1 g d f 8
36 Example! 1) Propagate the fault effect a b c 0/1 e 0/1 g d f 9
37 Example! 1) Propagate the fault effect a b c 0/1 e 0/1 0/1 g d f 0 10
38 Example! 1) Propagate the fault effect a b c 0/1 e 0/1 0/1 g d f 0 11
39 Example! Justification a b c d f e 0 0/1 0/1 0 0/1 g 12
40 Example! Justification a b 1 c 1 d f 0/1 e 0 0/1 0 0/1 g 13
41 Example! Justification a b 0 1 c 1 d f 0/1 e 0 0/1 0 0/1 g 14
42 Some Considerations! Test is easy! But. 15
43 Some problems (the complexity) 2.2 Billion Transistors 16
44 Some problems (the circuit)! Generate a test for c stuck-at-1 Sa1 a b c e g d f 17
45 Some problems (the circuit)! c stuck-at-1 is an untestable fault a b 1 0 c 0/1 d 0 0/1 f e 1 0/1 1 1 g 18
46 Goals! You must use the appropriate tool! Automatic Test Pattern Generator (ATPG) 19
47 Theoretical Foundations: Boolean Difference q The function for the circuit is q Let the target fault be y/0, then the function for the faulty circuit is f = f(y=0) q Goal of test generation: find a vector that makes f XOR f = 1 16 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 16
48 Boolean Difference Continued q f XOR f = 1 iff f and f result in opposing logic values q Thus, any vector that can set f XOR f = 1 is able to produce opposing values at the outputs of the fault-free and faulty circuits respectively q Definition: 17 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 17
49 Boolean Difference Example q To excite the fault y/0, y=1 q Thus, xyz= 110 or 011 can detect the fault 18 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 18
50 Another Example q Let target fault be w/0 xyz=001, 101 can detect w/0 But: 19 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 19
51 A Third Example q Fault: z/0 This fault is untestable! 20 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 20
52 Wrap Up on Boolean Difference q Given a circuit with output f and fault q The set of vectors that can detect this fault includes all vectors that satisfy 21 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 21
53 Sequential ATPG q Huffman Model of a sequential circuit 57 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 57
54 Iterative Logic Array Expansion q To detect a fault, a sequence of vectors may be needed 58 VLSI EE141 Test Principles and Architectures Ch. 4 - Test Generation - P. 58
55 Basics of Scan EE 382M Class Notes Foil # 13 The University of Texas at Austin
56 Sequential Circuits Testing Inputs outputs = f(inputs, state) Combinational Logic Registers State Outputs Clock In sequential circuits the initial state (register s values) is not by default known. Consequently, the sensitization of faults and the propagation of the corresponding erroneous responses may turn to be a hard task. A solution is to use techniques for the proper initialization of the circuit state to known values. Application of proper test vector sequences and/or the use of Set/Reset signals to setup the required state. Developmentofefficienttechniquesto set the initial state and observe the subsequent state after the response of the circuit. Scan Testing 3 General Scan Testing Scheme Scan In Registers Logic Inputs Outputs Scan Register Clock Scan Out The memory elements (latches or Flip Flops) in a design are properly connected to form aunifiedshiftregister(scan register or chain). This way the internal state of the circuit is determined (controlled) by shifting in (scan in)tothescanregistertherequiredtestdata to be applied to the combinational logic. Moreover, the existing internal state (previous logic response) can be observed by shifting out (scan out) thedatastoredintothescan register. Scan Testing 4 2
57 Scan Testing Design (Ι) Primary Inputs PI Combinational Logic PO Primary Outputs Pseudo Primary Outputs Full Scan Register Original Circuit PI PPI Scan In Combinational Logic PO PPO Pseudo Primary Inputs Scan Register Scan Out Scan Testing 5 Scan Testing Design (ΙI) Multiple Scan Chains Partial Scan PI Combinational Logic PO PI Combinational Logic PO Scan In_1 Scan Register Register Scan In_N... Scan Out_1 Scan In Scan Register Scan Register Scan Out_N Scan Out Scan Testing 6 3
58 Scan Path Design (I) Primary In nputs X 1 Z 1 X 2 X K Combinational Logic Z 2 Z N Primary Ou utputs SE SI MUX Scan FF D Flip Flop 0 0 D Q D Q D Q M CLK CLK CLK MUX... MUX Scan Chain 0 1 MUX SO CLK Scan Mode SE= 1 Scan Testing 7 Scan Path Design (II) Primary In nputs X 1 Z 1 X 2 X K Combinational Logic Z 2 Z N Primary Ou utputs SE SI MUX 0 0 D Q D Q D Q M CLK CLK CLK MUX... MUX Scan Chain 0 1 MUX SO CLK Normal Mode SE= 0 Scan Testing 8 4
59 Test Sequences During Scan Testing Prima ary Inputs SI Primary Outputs Test Vector clock cycles 1 st sequence 2 nd sequence 3 rd sequence 4 th sequence Ν th sequence (Ν+1) th sequence Test Response... SO clock cycles Scan Testing 9 Scan Application (Ι) 1 Scan cells testing 2 SE = 1 Scan in of alternating 3 Μ+1 clock cycles 0 and 1 from the SI input 4 Response observation at the SO output Μ = # of scan cells Scan Testing 10 5
60 Scan Application (ΙI) 5 Logic testing 6 SE = 1 : Test data scan in from the SI inputs Μ clock cycles (scan in cycles) 7 SE = 0 : Test pattern application from the PI inputs 8 Single clock pulse and response observation at the POs single clock cycle (capture cycle) Scan Testing 11 Scan Application (ΙII II) 9 SE = 1 : New test data scan in from the SIs and simultaneous scan out of the test responses from the SOs Μ clock cycles 10 Exists another test vector; YES 7 No 11 End Scan Testing 12 6
61 Basics of Scan F7 F8 S R A M F1 F2 A C F E B D G H F5 F9 F3 F6 F0 F4 EE 382M Class Notes Foil # 14 The University of Texas at Austin
62 SCAN IN Basics of Scan F7 F8 S R A M F1 F2 A C F E B D G H F5 F9 F3 F6 F0 F4 SCAN OUT EE 382M Class Notes Foil # 15 The University of Texas at Austin
63 Convert a Memory Element to a Scan Cell Memory element C C data in data out Scannable Register C C A B B data in Scan out Scan in A Master Register EE 382M Class Notes Foil # 16 Slave Register data out The University of Texas at Austin
64 Scan Design Components (1) scan cell (3) scan in and scan out (2) scan chain (4) scan clock scan chain scan chain PI (Scan in) PO (Scan out) PI (Scan in) PO (Scan out) scan cell scan in data in scan A clock scan cell System clock scan B clock EE 382M Class Notes Foil # 17 data out scan out The University of Texas at Austin
65 Why Scan design? Makes internal circuit access much more direct to allow for controllability and observability Converts a sequential test generation problem into a combinational test generation problem Enables automatic test pattern generation (ATPG) Enables use of low-pincount, low cost testers (ATE) EE 382M Class Notes Foil # 18 The University of Texas at Austin
66 Stuck-At Testing SCAN IN Test for C stuck-at 1 F7 F8 S R A M F1 F2 A C F E B D G H F5 F9 F3 F6 F0 F4 SCAN OUT EE 382M Class Notes Foil # 19 The University of Texas at Austin
67 SCAN IN Stuck-At Testing Test for C stuck-at 1 Load Scan Chain S R A M 0 1 A C F E B D G H 1 1 SCAN OUT EE 382M Class Notes Foil # 20 The University of Texas at Austin
68 SCAN IN Stuck-At Testing Test for C stuck-at 1 Pulse Clock Test Result S R A M?? A C F E B D G H 1?? SCAN OUT EE 382M Class Notes Foil # 21 The University of Texas at Austin
69 SCAN IN Stuck-At Testing Test for C stuck-at 1 Unload Scan Chain S R A M 0 1 A C F E B D G H SCAN OUT EE 382M Class Notes Foil # 22 The University of Texas at Austin
70 Scan-based Structural Test Scan Inputs Primary I/O s (no connection) can chains logic logic logic logic sprimary I/O s (no connection) Control and clock inputs Tester Scan Outputs EE 382M Class Notes Foil # 23 The University of Texas at Austin
Testing Digital Systems II
Lecture : Introduction Instructor: M. Tahoori Copyright 206, M. Tahoori TDS II: Lecture Today s Lecture Logistics Course Outline Review from TDS I Copyright 206, M. Tahoori TDS II: Lecture 2 Lecture Logistics
More informationEECS 427 Lecture 21: Design for Test (DFT) Reminders
EECS 427 Lecture 21: Design for Test (DFT) Readings: Insert H.3, CBF Ch 25 EECS 427 F09 Lecture 21 1 Reminders One more deadline Finish your project by Dec. 14 Schematic, layout, simulations, and final
More informationVLSI Design Verification and Test Delay Faults II CMPE 646
Path Counting The number of paths can be an exponential function of the # of gates. Parallel multipliers are notorious for having huge numbers of paths. It is possible to efficiently count paths in spite
More informationOverview ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES. Motivation. Modeling Levels. Hierarchical Model: A Full-Adder 9/6/2002
Overview ECE 3: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Logic and Fault Modeling Motivation Logic Modeling Model types Models at different levels of abstractions Models and definitions Fault Modeling
More informationIES Digital Mock Test
. The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code
More informationTesting Digital Systems II. Problem: Fault Diagnosis
Testing Digital Systems II Lecture : Logic Diagnosis Instructor: M. Tahoori Copyright 26, M. Tahoori TDSII: Lecture Problem: Fault Diagnosis test patterns Circuit Under Diagnosis (CUD) expected response
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Project Presentations
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 28 Memory Project Presentations 293 Cory Tuesday, May 2, 2-4pm o Murmann, Baytekin o Borinski, Dogan, Markow o Smilkstein, Wong o Zanella,
More informationElectronic Circuits EE359A
Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.
More informationTest Automation - Automatic Test Generation Technology and Its Applications
Test Automation - Automatic Test Generation Technology and Its Applications 1. Introduction Kwang-Ting (Tim) Cheng and Angela Krstic Department of Electrical and Computer Engineering University of California
More informationLecture 16: Design for Testability. MAH, AEN EE271 Lecture 16 1
Lecture 16: Testing, Design for Testability MAH, AEN EE271 Lecture 16 1 Overview Reading W&E 7.1-7.3 - Testing Introduction Up to this place in the class we have spent all of time trying to figure out
More informationCode No: R Set No. 1
Code No: R05310402 Set No. 1 1. (a) What are the parameters that are necessary to define the electrical characteristics of CMOS circuits? Mention the typical values of a CMOS NAND gate. (b) Design a CMOS
More informationA Novel Low-Power Scan Design Technique Using Supply Gating
A Novel Low-Power Scan Design Technique Using Supply Gating S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh, and K. Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette,
More informationTopic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection
NMOS Transistors in Series/Parallel Connection Topic 6 CMOS Static & Dynamic Logic Gates Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Transistors can be thought
More informationI DDQ Current Testing
I DDQ Current Testing Motivation Early 99 s Fabrication Line had 5 to defects per million (dpm) chips IBM wanted to get 3.4 defects per million (dpm) chips Conventional way to reduce defects: Increasing
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC
More informationEC 1354-Principles of VLSI Design
EC 1354-Principles of VLSI Design UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY PART-A 1. What are the four generations of integrated circuits? 2. Give the advantages of IC. 3. Give the variety of
More informationObjective Questions. (a) Light (b) Temperature (c) Sound (d) all of these
Objective Questions Module 1: Introduction 1. Which of the following is an analog quantity? (a) Light (b) Temperature (c) Sound (d) all of these 2. Which of the following is a digital quantity? (a) Electrical
More informationYield, Reliability and Testing. Technical University of Lodz - Department of Microelectronics and Computer Science
Yield, Reliability and Testing The Progressive Trend of IC Technology Integration level Year Number of transistors DRAM integration SSI 1950s less than 10 2 MSI 1960s 10 2-10 3 LSI 1970s 10 3-10 5 4K,
More informationCPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
More informationGates and Circuits 1
1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior
More informationEECS 579 Fall What is Testing?
EECS 579 Fall 2001 Recap Text (new): Essentials of Electronic Testing by M. Bushnell & V. Agrawal, Kluwer, Boston, 2000. Class Home Page: http://www.eecs.umich.edu/courses/eecs579 Lecture notes and other
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More informationCOMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA
COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true
More informationLecture 02: Digital Logic Review
CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:
More informationFIRSTRANKER. 1. (a) What are the advantages of the adjustable voltage regulators over the fixed
Code No: 07A51102 R07 Set No. 2 1. (a) What are the advantages of the adjustable voltage regulators over the fixed voltage regulators. (b) Differentiate betweenan integrator and a differentiator. [8+8]
More informationDigital Design and System Implementation. Overview of Physical Implementations
Digital Design and System Implementation Overview of Physical Implementations CMOS devices CMOS transistor circuit functional behavior Basic logic gates Transmission gates Tri-state buffers Flip-flops
More informationModule -18 Flip flops
1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip
More informationReference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering
FPGA Fabrics Reference Wayne Wolf, FPGA-Based System Design Pearson Education, 2004 CPLD / FPGA CPLD Interconnection of several PLD blocks with Programmable interconnect on a single chip Logic blocks executes
More informationEECS150 - Digital Design Lecture 28 Course Wrap Up. Recap 1
EECS150 - Digital Design Lecture 28 Course Wrap Up Dec. 5, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John Wawrzynek)
More informationChapter 2 Combinational Circuits
Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits
More informationCMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits
Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative
More information電子電路. Memory and Advanced Digital Circuits
電子電路 Memory and Advanced Digital Circuits Hsun-Hsiang Chen ( 陳勛祥 ) Department of Electronic Engineering National Changhua University of Education Email: chenhh@cc.ncue.edu.tw Spring 2010 2 Reference Microelectronic
More informationClassification of Digital Circuits
Classification of Digital Circuits Combinational logic circuits. Output depends only on present input. Sequential circuits. Output depends on present input and present state of the circuit. Combinational
More informationLecture 18. BUS and MEMORY
Lecture 18 BUS and MEMORY Slides of Adam Postula used 12/8/2002 1 SIGNAL PROPAGATION FROM ONE SOURCE TO MANY SINKS A AND XOR Signal le - FANOUT = 3 AND AND B BUS LINE Signal Driver - Sgle Source Many Sks
More informationUnit level 4 Credit value 15. Introduction. Learning Outcomes
Unit 20: Unit code Digital Principles T/615/1494 Unit level 4 Credit value 15 Introduction While the broad field of electronics covers many aspects, it is digital electronics which now has the greatest
More informationCombinational Logic Circuits. Combinational Logic
Combinational Logic Circuits The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic 0 or logic 1, at any given instant in time. The
More informationCMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative
More informationThe challenges of low power design Karen Yorav
The challenges of low power design Karen Yorav The challenges of low power design What this tutorial is NOT about: Electrical engineering CMOS technology but also not Hand waving nonsense about trends
More information1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as
BioE 1310 - Review 5 - Digital 1/16/2017 Instructions: On the Answer Sheet, enter your 2-digit ID number (with a leading 0 if needed) in the boxes of the ID section. Fill in the corresponding numbered
More informationCS302 - Digital Logic Design Glossary By
CS302 - Digital Logic Design Glossary By ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital
More informationECOM 4311 Digital System Design using VHDL. Chapter 9 Sequential Circuit Design: Practice
ECOM 4311 Digital System Design using VHDL Chapter 9 Sequential Circuit Design: Practice Outline 1. Poor design practice and remedy 2. More counters 3. Register as fast temporary storage 4. Pipelined circuit
More information! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential
More informationCS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam
CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page
More informationECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment
1 ECEN 720 High-Speed Links: Circuits and Systems Lab3 Transmitter Circuits Objective To learn fundamentals of transmitter and receiver circuits. Introduction Transmitters are used to pass data stream
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018
UNIVERSITY OF BOLTON [EES04] SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationNovel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy School of Electrical and Computer Engineering, Purdue University,
More informationDIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N
DIGITAL INTEGRATED CIRCUITS A DESIGN PERSPECTIVE 2 N D E D I T I O N Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic CONTENTS PART I: THE FABRICS Chapter 1: Introduction (32 pages) 1.1 A Historical
More informationOn Built-In Self-Test for Adders
On Built-In Self-Test for s Mary D. Pulukuri and Charles E. Stroud Dept. of Electrical and Computer Engineering, Auburn University, Alabama Abstract - We evaluate some previously proposed test approaches
More informationPROPOSED SCHEME OF COURSE WORK
PROPOSED SCHEME OF COURSE WORK Course Details: Course Title : Digital System Design Course Code :15EC1110 L T P C : 4 0 0 3 Program: : B.Tech. Specialization: : Electrical and Electronics Engineering Semester
More informationEE 330 Lecture 44. Digital Circuits. Dynamic Logic Circuits. Course Evaluation Reminder - All Electronic
EE 330 Lecture 44 Digital Circuits Dynamic Logic Circuits Course Evaluation Reminder - All Electronic Digital Building Blocks Shift Registers Sequential Logic Shift Registers (stack) Array Logic Memory
More informationWritten exam IE1204/5 Digital Design Friday 13/
Written exam IE204/5 Digital Design Friday 3/ 207 08.00-2.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandqvist tel 08-7904487 Teacher: Valhallavägen, Ahmed Hemani 08-7904469
More informationElectronics. Digital Electronics
Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationComputer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific. Digital Logic
ECPE 170 Jeff Shafer University of the Pacific Digital Logic 2 Homework Review 2.33(d) Convert 26.625 to IEEE 754 single precision floa9ng point: Format requirements for single precision (32 bit total
More informationChapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1
Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar
More informationEXPERIMENT 12: DIGITAL LOGIC CIRCUITS
EXPERIMENT 12: DIGITAL LOGIC CIRCUITS The purpose of this experiment is to gain some experience in the use of digital logic circuits. These circuits are used extensively in computers and all types of electronic
More informationA High Performance Variable Body Biasing Design with Low Power Clocking System Using MTCMOS
A High Performance Variable Body Biasing Design with Low Power Clocking System Using MTCMOS G.Lourds Sheeba Department of VLSI Design Madha Engineering College, Chennai, India Abstract - This paper investigates
More informationEE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector
EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector Group Members Uttam Kumar Boda Rajesh Tenukuntla Mohammad M Iftakhar Srikanth Yanamanagandla 1 Table
More informationExploring the Basics of AC Scan
Page 1 of 8 Exploring the Basics of AC Scan by Alfred L. Crouch, Inovys This in-depth discussion of scan-based testing explores the benefits, implementation, and possible problems of AC scan. Today s large,
More informationDESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM
DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM 1 Mitali Agarwal, 2 Taru Tevatia 1 Research Scholar, 2 Associate Professor 1 Department of Electronics & Communication
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers Friday s class will be a lecture rather
More informationRun-Length Based Huffman Coding
Chapter 5 Run-Length Based Huffman Coding This chapter presents a multistage encoding technique to reduce the test data volume and test power in scan-based test applications. We have proposed a statistical
More informationQUIZ. What do these bits represent?
QUIZ What do these bits represent? 1001 0110 1 QUIZ What do these bits represent? Unsigned integer: 1101 1110 Signed integer (2 s complement): Fraction: IBM 437 character: Latin-1 character: Huffman-compressed
More informationFan in: The number of inputs of a logic gate can handle.
Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationMux-Based Latches. Lecture 8. Sequential Circuits 1. Mux-Based Latch. Mux-Based Latch. Negative latch (transparent when CLK= 0)
Mux-Based Latches Lecture 8 equential Circuits Negative latch (transparent when = 0) Positive latch (transparent when = ) Peter Cheung epartment of Electrical & Electronic Engineering Imperial College
More information6.111 Lecture # 19. Controlling Position. Some General Features of Servos: Servomechanisms are of this form:
6.111 Lecture # 19 Controlling Position Servomechanisms are of this form: Some General Features of Servos: They are feedback circuits Natural frequencies are 'zeros' of 1+G(s)H(s) System is unstable if
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 0 ELECTRONICS AND COMMUNICATION ENGINEERING TUTORIAL QUESTION BANK Name : VLSI Design Code : A0 Regulation : R5 Structure :
More informationChapter 20 Circuit Design Methodologies for Test Power Reduction in Nano-Scaled Technologies
Chapter 20 Circuit Design Methodologies for Test Power Reduction in Nano-Scaled Technologies Veena S. Chakravarthi and Swaroop Ghosh Abstract Test power has emerged as an important design concern in nano-scaled
More informationCS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON
CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Instructor: Andy Phelps TAs: Newsha Ardalani, Peter Ohmann, and Jai Menon Midterm Examination 2 In Class (50 minutes) Wednesday,
More informationEECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations
EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies Mar 12, 2013 John Wawrzynek Spring 2013 EECS150 - Lec15-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)
More informationEECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies
EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies Feb 14, 2012 John Wawrzynek Spring 2012 EECS150 - Lec09-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)
More informationDigital Integrated CircuitDesign
Digital Integrated CircuitDesign Lecture 13 Building Blocks (Multipliers) Register Adder Shift Register Adib Abrishamifar EE Department IUST Acknowledgement This lecture note has been summarized and categorized
More informationLecture 12 Memory Circuits. Memory Architecture: Decoders. Semiconductor Memory Classification. Array-Structured Memory Architecture RWM NVRWM ROM
Semiconductor Memory Classification Lecture 12 Memory Circuits RWM NVRWM ROM Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Reading: Weste Ch 8.3.1-8.3.2, Rabaey
More information5. (Adapted from 3.25)
Homework02 1. According to the following equations, draw the circuits and write the matching truth tables.the circuits can be drawn either in transistor-level or symbols. a. X = NOT (NOT(A) OR (A AND B
More informationLecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University
Lecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 1 Outline
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple
More information! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "
More informationCourse Outline Cover Page
College of Micronesia FSM P.O. Box 159 Kolonia, Pohnpei Course Outline Cover Page Digital Electronics I VEE 135 Course Title Department and Number Course Description: This course provides the students
More informationUMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency
UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter
More informationHomework Problem Set: Combinational Devices & ASM Charts. Answer all questions on this sheet. You may attach additional pages if necessary.
Student Name:.. Student Number:.. Session I (1 or 2):. Table I (1-11):... Group I (,, ): Homework Problem Set: ombinational evices & SM harts We will collect these sheets from students at the start of
More informationLecture 4&5 CMOS Circuits
Lecture 4&5 CMOS Circuits Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese566/ Worst-Case V OL 2 3 Outline Combinational Logic (Delay Analysis) Sequential Circuits
More informationDesign For Test. VLSI Design I. Design for Test. page 1. What can we do to increase testability?
VLS esign esign for Test esign For Test What can we do to increase ability? He s dead Jim... Overview design for architectures ad-hoc, scan based, built-in in Goal: You are familiar with ability metrics
More informationDigital Controller Chip Set for Isolated DC Power Supplies
Digital Controller Chip Set for Isolated DC Power Supplies Aleksandar Prodic, Dragan Maksimovic and Robert W. Erickson Colorado Power Electronics Center Department of Electrical and Computer Engineering
More informationCircuits in CMOS VLSI. Darshana Sankhe
Circuits in CMOS VLSI Darshana Sankhe Static CMOS Advantages: Static (robust) operation, low power, scalable with technology. Disadvantages: Large size: An N input gate requires 2N transistors. Large capacitance:
More informationUnit 3. Logic Design
EE 2: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Unit 3 Chapter Combinational 3 Combinational Logic Logic Design - Introduction to Analysis & Design
More informationLecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques.
Introduction EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Techniques Cristian Grecu grecuc@ece.ubc.ca Course web site: http://courses.ece.ubc.ca/353/ What have you learned so far?
More informationDesign of Low Power Flip Flop Based on Modified GDI Primitive Cells and Its Implementation in Sequential Circuits
Design of Low Power Flip Flop Based on Modified GDI Primitive Cells and Its Implementation in Sequential Circuits Dr. Saravanan Savadipalayam Venkatachalam Principal and Professor, Department of Mechanical
More informationEE 280 Introduction to Digital Logic Design
EE 280 Introduction to Digital Logic Design Lecture 1. Introduction EE280 Lecture 1 1-1 Instructors: EE 280 Introduction to Digital Logic Design Dr. Lukasz Kurgan (section A1) office: ECERF 6 th floor,
More informationIntroduction to CMOS VLSI Design (E158) Lecture 5: Logic
Harris Introduction to CMOS VLSI Design (E158) Lecture 5: Logic David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture 5 1
More informationIn this lecture: Lecture 8: ROM & Programmable Logic Devices
In this lecture: Lecture 8: ROM Programmable Logic Devices Dr Pete Sedcole Department of EE Engineering Imperial College London http://caseeicacuk/~nps/ (Floyd, 3 5, 3) (Tocci 2, 24, 25, 27, 28, 3 34)
More informationDFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers
DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers Muhammad Nummer and Manoj Sachdev University of Waterloo, Ontario, Canada mnummer@vlsi.uwaterloo.ca, msachdev@ece.uwaterloo.ca
More informationCMPEN 411 VLSI Digital Circuits Spring Lecture 24: Peripheral Memory Circuits
CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 24: Peripheral Memory Circuits [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers 1 General Table Lookup Synthesis A B 00
More informationGates and and Circuits
Chapter 4 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the
More informationComputer Architecture (TT 2012)
Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture
More informationIC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System
IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System 1 Raj Kumar Mistri, 2 Rahul Ranjan, 1,2 Assistant Professor, RTC Institute of Technology, Anandi, Ranchi, Jharkhand,
More informationDesign of low-power, high performance flip-flops
Int. Journal of Applied Sciences and Engineering Research, Vol. 3, Issue 4, 2014 www.ijaser.com 2014 by the authors Licensee IJASER- Under Creative Commons License 3.0 editorial@ijaser.com Research article
More informationEECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline
EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies Oct. 31, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy
More informationLab #10: Finite State Machine Design
Lab #10: Finite State Machine Design Zack Mattis Lab: 3/2/17 Report: 3/14/17 Partner: Brendan Schuster Purpose In this lab, a finite state machine was designed and fully implemented onto a protoboard utilizing
More informationField Programmable Gate Array
9 Field Programmable Gate Array This chapter introduces the principles, implementation and programming of configurable logic circuits, from the point of view of cell design and interconnection strategy.
More information