A High Performance Variable Body Biasing Design with Low Power Clocking System Using MTCMOS

Transcription

1 A High Performance Variable Body Biasing Design with Low Power Clocking System Using MTCMOS G.Lourds Sheeba Department of VLSI Design Madha Engineering College, Chennai, India Abstract - This paper investigates the enhancement in the performance of a variable body biasing design with low power clocking system using MTCMOS. Clock gating (CG) is the most common and widely used technique to reduce dynamic power, and power gating (PG) is the dominant technique to reduce standby leakage power. The problem with the design is the dynamic and leakage power consumption during the active and standby mode. In the proposed power gating method Variable body biasing approach is used for reducing the active and standby leakage. An optimized busspecific-clock-gating(obsc) scheme to improve traditional XOR-based CG. It chooses only a subset of flip-flops (FFs) to be gated selectively, and the problem of gated FF selection is reduced from exponential complexity into linear. Then those combinational logics, which completely depend on the outputs of gated FFs, are performing redundant operations. Integration of OBSC and PG, which can be reduce dynamic power and active leakage power simultaneously. The proposed method is simulated in MICROWIND. The proposed OBSC and variable body biasing PG method reduces the dynamic and leakage power while compare with existing CG and PG method. Index Terms - Clock Gating (CG), Bus Specific Clock Gating (BSC), Optimized Bus Specific Clock Gating (OBSC), Power Gating (PG), Run Time Power Gating (RTPG). I. INTRODUCTION With the progress of CMOS technology, there is a steady growth in clock frequency and chip capacity. As a result, the power dissipation of digital CMOS design has Mrs. T. C. Sabareeswari Department of ECE Madha Engineering College, Chennai, India increased tremendously [1]. As a result, low power techniques are highly appreciated in current VLSI design. Power consumption consists of dynamic power and leakage power, and leakage power can be divided into standby leakage and active leakage. Dynamic power is consumed by a circuit during its operation mode (while the circuit has input toggles). Leakage power dissipated in sleep mode (when the circuit does not have input toggles) is normally referred to as standby leakage, while the leakage power consumed in operation mode is active leakage. Clock gating (CG) [2] [4] is the most common and widely used technique to reduce dynamic power, and power gating (PG) [5] is the dominant technique to reduce standby leakage power. As active leakage power becomes more and more important [6], [7], it also requires care. In order to distinguish it from the traditional PG, which is used to reduce the standby leakage, the PG to minimize active leakage power in the operation mode is referred to as run time power gating (RTPG) [7]. CG is a technique used to gate the unnecessary clock toggles of a register. During the clock gated period, there are some components that are performing redundant operations, and RTPG will put these components into sleep. There are several researchers focusing on the integration of CG and RTPG [6] [9]. All of their designs are based on clock gated designs generated after synthesis, and they evaluate the feasibility of RTPG according to the signal activity of the design. However, it is possible that a design cannot be clock gated during synthesis. Then their approach cannot be used. Moreover, with the signal activity of the design, CG should also be analyzed to determine if dynamic power is reduced

2 If dynamic power is increased, the total power may increase even if active leakage power is reduced. In this brief, we have proposed an activity-driven fine-grained CG and RTPG integration, which can reduce dynamic power and active leakage power simultaneously. An activity-driven optimized bus specific CG (OBSC afterward) is used to maximize dynamic power reduction at RT level before synthesis. It chooses only a subset of flip-flops (FF) to be gated selectively, and the problem of gated FF selection is reduced from exponential complexity into linear. After the OBSC is applied to the design, the components performing redundant operations during the clock gated period are determined by forward traversing the circuit from the gated FF outputs. These components will be power gated using the clock enable signal generated by OBSC only if the implementation of RTPG can reduce active leakage power. The feasibility analysis of RTPG is based on our proposed minimum average idle time concept. A. CG Basics II. BACKGROUND Fig. 1(a) is a typical non-cg circuit and Fig. 1(b) is its traditional XOR-based CG circuitry [bus-specific-clockgating (BSC) afterwards]. BSC circuit compares the inputs and outputs, and gates the clock when they are equal. BSC can be used as a final CG option to reduce dynamic power when no CG can be applied during synthesis. However, BSC is far from optimal in terms of dynamic power minimization, and the partial BSC (PBSC afterward) circuit [Fig. 1(c)] may have much less power. The rest of this brief is organized as follows. Section II gives an introduction to CG and PG basics. The proposed activity-driven OBSC is presented in Section III. Section IV. explains the details on how to implement PG after OBSC. Section V explains the details about variable body biasing method. Experimental results are given in Section VI, and this brief is concluded in Section VII. (b) (c) (a) Fig. 1, (a) Non-CG circuit.(b) BSC circuit. (c) PBSC circuit

3 B. PG Basics The most basic PG structure (a single footer) to reduce the leakage power, as shown in Fig. 2. The sleep signal that controls the footer in traditional PG is provided by an independent power management block. In this brief, we do not consider this type of sleep signal. Instead, the sleep signal of RTPG we focus on is generated by CG in operation mode. It is used to turn off the components that are executing redundant operations in operation mode. 4) OP_IV neither clock nor input data toggles. Suppose their corresponding power are POP_I, POP_II, POP_III, and POP_IV, (in fact, POP_IV is 0 since no input toggles) respectively, and their corresponding percentage of the circuit operation time is top_i, top_ii, top_iii, and top_iv (top_i + top_ii + top_iii + top_iv = 1), then the power of a D FF/latch can be calculated as Pseq = POP_I top_i + POP_II top_ii + POP_III top_iii. (1) In conclusion, given the power models that can be obtained in advance (i.e., Pcomb unit, POP_I, etc), the power of either combinational logic or sequential logic in the PBSC circuit Fig. 1(c) can be estimated with the information of the toggle rates of appropriate signals. B. Activity-Driven OBSC Fig. 2, PG scheme. III. ACTIVITY-DRIVEN OPTIMIZED BUS- SPECIFIC CG A. Sequential Logic Power Model The sequential logic is normally a latch or a D FF. The power estimation of the sequential logic cannot be evaluated by the above technique [10]. We propose a new way to measure the power of a sequential logic in this brief. For a D FF/latch, its operation per each clock cycle can be classified into four categories: 1) OP_I both clock and input data toggle; 2) OP_II only clock toggles; 3) OP_III only input data toggles Suppose there are N FFs in the non CG circuit, each FF can be chosen as gated or non gated. So there will be 2N possible CG solutions. One of the contributions of this brief is that this exponential complexity problem is reduced into linear by using the signal activity information. Assume that all the FFs are chosen to be gated initially, then the problem becomes how to determine which FFs should be excluded from gating. Heuristically, the FF with the maximum output data toggle rate should be excluded from gating first. This is because that maximum output data toggle rate indicates that minimum clock toggles will be gated, thus power will reduce least or even increase if the FF is gated. More formally, the FF with the maximum output toggle rate is excluded from gating first, then the FF with the second largest output toggle rate is excluded and so on until all the FFs are excluded (i.e., the original non CG circuit). Apparently, during the process of exclusion, there will be N+1 possible CG solutions (one non-cg circuit and N PBSC circuits) which is linear complexity. PBSC is the effective method for reducing dynamic power because it reduces unwanted switching activity in FFs. It uses clock gating and non clock gating circuit. So it avoids high power consumption

4 completely dependent on the stable gated FF outputs, so they are not active and can be power gated into sleep. However, one input of the XOR gate i is the output of un gated FF A, and one input of the AND gate h is the primary input. Since both the un gated FF output and PI may not be stable during the clock gated period, the XOR gate i and the AND h may be active. So they should not be power gated. In order to avoid floating signal, a holder should be placed at the output of each power gated cell if that output connects to non power gated cells or primary outputs (POs). For example, in Fig. 4, two holder logics should be added to the outputs of the two NOT gates separately. Fig.3, Basic scheme of proposed OBSC technique IV. INTEGRATION OF CG AND RTPG A. Run Time PG Assume that applied OBSC technique to a design, then a subset of FFs is clock gated. During the clock gated period, the outputs of the gated FFs are stable. Consequently, those combinational logics whose inputs only depend on gated FF outputs (forward traversing from the gated FF outputs) will be inactive and can be power gated. For each output of the power gated cell, we need to check if it has connection to primary output, or non power gated cells. If yes, a holder logic should be added in order to avoid signal floating. 1) Forward Traversing Example: In order to understand it clearly, an example is given in Fig. 4. Suppose that four out of five FFs are clock gated. The circled cells are 638

5 power gated. Holders are placed between the power gated cells and the non power gated cells so that the non power gated cells can function properly. Fig. 4, Forward traversing example Fig. 5, Integration of CG and RTPG. B. Integration of CG and RTPG If RTPG is determined to be applied, a footer (high-vth CMOS transistor) between the actual ground and virtual ground of the power gated cells should be added. After the integration of CG and RTPG, the low power design should look like Fig. 5.As we can see, the enable signal generated from OBSC is used as the sleep signal for the PG. The cells that are totally dependent on gated FF outputs are V VARIABLE BODY BIASING METHOD To reduce the leakage current in the sleep mode we ensured that the body to source voltage of the sleep transistor is increased. To do that we added a PMOS (M2) and a NMOS (M5) in the previously discussed sleepy keeper circuit (Fig.6). During sleep mode PMOS (M2) is OFF so 639

6 the body to source voltage of the pull up PMOS (M1) is higher than in the active mode. As a result of Body effect, Vth also increases which lowers the performance. During the active mode, the performance is improved as the PMOS (M2) is ON which makes the V th of the pull up PMOS (M1) lower again. The same discussion is applicable for the pull down NMOS (M4) and NMOS (M5). The remaining NMOS (M3) and PMOS (M6) works together for retaining the state in the sleep mode. If the output is high, in the sleep mode, the NMOS (M3) will keep the output high. Similarly, the PMOS (M6) will maintain the state in sleep mode if the output is low. Fig. 7, Forward traversing example waveform It is an integration of both CG and PG circuit. Here NMOS sleep transistor is used to reduce the leakage current. So the power is 0.321mW. It is shown in fig 8. Fig. 6, Variable Body Biasing Approach VI. EXPERIMENTAL RESULTS The proposed method of combining OBSC and RTPG has been tested on circuits. The active leakage power Fig. 8, Integration of CG and PG waveform It is an integration of both OBSC and variable body biasing approach. It reduces both active and standby leakage. The power is µW is estimated by MICROWIND 2.1 Simulation. It is a forward traversing circuit. It consumes more power.the power is 0.357mW. It is shown in fig

7 REFERENCES Fig.9, Integration of OBSC and Variable body biasing approach. TABLE I EXPERIMENTAL RESULTS FOR DYNAMIC POWER REDUCTION AND LEAKAGE REDUCTION BY VARIOUS APPROACHES S. No Method Time Power 1 CG only 50 ns 0.357mW 2 Integration of OBSC and 50 ns 0.321mW PG 3 Integration of OBSC and 50 ns Variable body biasing µW approach [1] H. Sutter. (2005). The Free Lunch is Over [Online]. Available [2] S. Jairam, M. Rao, J. Srinivas, P. Vishwanath, H. Udayakumar, an J. Rao, Clock gating for power optimization in ASIC design cycle theory & practice, in Proc. Int. Symp. Low Power Electron. Design, Aug. 2008, pp [3] P. Babighian, L. Benini, and E. Macii, A scalable algorithm for RTL insertion of gated clocks based on ODCs computation, IEEE Trans.Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 1, pp , Jan [4] R. Fraer, G. Kamhi, and M. K. Mhameed, A new paradigm for synthesisand propagation of clock gating conditions, in Proc. Des. Autom. Conf., Jun. 2008, pp [5] K. Roy, S. Mukhopadkyay, and H. Mahmoodi- meimand, Leakage current mechanisms and leakage reduction techniques in deep sub micrometer CMOS circuits, Proc. IEEE, vol. 91, no. 2, pp Feb VII. CONCLUSION A fine-grained CG and RTPG integration based on signal activities. An activity driven fine-grained OBSC technique that selects only a subset of FFs to gate. It can reduce dynamic power. The clock enable signal generated in the OBSC circuit can be used as the sleep signal in RTPG. The power gated cells can be determined by, forward traversing from the gated FF outputs. In the power gating, sleep transistors are used as switches to shut off power supplies to parts of a design in standby mode. Our Variable Body Biasing approach shows improved results in terms of static power, dynamic power