Minimization of 34T Full Subtractor Parameters Using MTCMOS Technique

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1 Minimization of 34T Full Subtractor Parameters Using MTCMOS Technique Mohammad Mudassir 1, Vishwas Mishra 2 and Amit Kumar 3 1 Research Scholar, M.Tech RF and Microwave, SITE, SVSU, Meerut (UP) INDIA, mudassir652@gmail.com 2 Assistant Professor, SITE, SVSU, Meerut (UP) INDIA, Vishwasmishra88@gmail.com 3 Assistant Professor, SITE, SVSU, Meerut (UP) INDIA, amitcho119@gmail.com Abstract - Non-regenerative circuits have vast utilizations in various electronic devices, computing devices and memory devices. There are various circuit designs to instrument a given logic function. The parameter that is dominant in high performance digital circuitry is the speed while in battery driven circuit is power dissipation that ultimately results due to leakage in the circuits. The other reason being the continuous scaling of technology has also resulted in increase of leakage parameters. In this paper, low leakage low power consuming 34 transistor full Subtractor using MTCMOS design technique has been proposed in active and standby mode at different supply voltages. This paper also focused on the minimum voltage that can be used in 45 nm technology using cadence virtuoso tool. Sleep mode leakage current of MTCMOS full subtractor at 0.5V was found to be 4.97fA and during active mode 1.45 pa. Keywords- CMOS, Full Substractor, MTCMOS, High Vt transistors and Low power. 1. INTRODUCTION Combinational circuits have the property that at any point of time, output of that circuit is linked with its current or present input signals by any Boolean relation. No interconnected link from output fed backs to input. Full subtractor is one of the family members of combinational circuits that perform subtraction handling three numbers at a time. Full subtractor is used in different logic circuits like multipliers [1], dividers, parity checkers, comparators and compressors and is also used to generate address in case of memory access or cache. There are three types of Full subtractor structure static, dynamic and hybrid. Static Full Substractor are less power consuming than dynamic and then more reliable. Dynamic Full Substractor have cluster switching speed, full swing voltage level and less number of transistors but suffer from charge sharing, clock load, high power due to high switching activity and complexity.[2]-[3]. Hybrid full subtractor is basically a combination of static and dynamic Full Substractor [4]-[5]. There are number of research papers, focus on different types of structures of full subtractor based on different logic structure design and also based on the way of expression of logic function. Full Substractor performs the subtraction bit by bit with carry input and provides bar output with carry output by going through AND logic performance. The carry output becomes the carry input for next input combination. We can see this in truth table in Table 1. On the basis of truth

2 table, the sum and output function can be expressed as (1) AND-OR-NOR structure [6]. The cell view of the full subtractor is shown in the Figure 1. (2) (3) Table 1: Truth Table of Full Substractor A B Cin SUM CARRY (4) (5) (6) Figure 1 Gate level Cell view of Full Substractor The gate level schematic of full subtractor is shown in figure 1. Here we use the carry signal to produce sum signal instead of realize separate function for sum and carry signal [7]-[8]. For the transistor level implementation of full subtractor only 17 NMOS and 17 PMOS are used. 2. FULL SUBTRACTOR WITH MTCMOS TECHNIQUE In neoteric years, power consumption has become a significant design constraint for many non-regenerative or combinational circuits. As the technology is scaling down from micrometer to nanometer regime, there is a rapid increase in demand of low power, high performance and low leakage providing circuit systems. In VLSI for transistor level implementation of any device there is tradeoff mainly between three parameters power dissipation, chip area and operating speed [9]. Chip area depends on the number of transistors and number of wires for connecting them. Operating speed mainly depends on propagation delay of transistors, number of inversion and intra-cell wiring capacitances [10]. Power dissipation in CMOS circuits is mainly due to node capacitance, transistor and switching activity of transistors. In VLSI design, sources of power consumption arise due to: To implement the Full Subtractor with the help of EXOR, AND, OR gate using above equation, 42 transistors were required as a result circuit design needed more area and more power consumption. In this paper a systematic approach to design 1-bit 34 transistor conventional full subtractor with MTCMOS technique, used in ripple carry subtractor and array multipliers in different architectures of digital signal processors and microprocessors is presented. For implementing 1-bit 34 transistor conventional full subtractor the sum and carry function are represented by nested

3 (i) Switching action of charging and discharging of capacitances Powertotal = Pdynamic + Psc + Pstatic (7) Pdynamic =CV 2 ddfsw (8) (ii) Short circuit power due to current flow between power supply and ground when pull up and pull down network act simultaneously Psc = Isc.Vdd. ts fsw (9) Where, Isc stands for short circuit current and ts for delay in switching (iii) Static power due to static current and leakage current. Power dissipation for small size and battery operated equipment s like mobile telephone, palmtops, laptops and other biomedical equipment s are mainly due to leakage current power dissipation. performance. The drawback in low threshold voltage devices is that they have substantially higher static leakage. Transistors with high threshold voltages are used for controlling leakage. MTCMOS technique thus is a solution to many high performance and low power design in modern circuitry. It does so by isolating the low threshold circuitry from ground and VDD using high-threshold transistors or circuits. (10) Where k and n are technology function, is drained induced barrier lowering coefficient sub threshold leakage current also depend on temperature supply voltage, device size, and threshold voltage etc. [11]-[14] we can reduce sub threshold leakage current using higher threshold VTH in some part of design. 3. PROPOSED WORK Diverse techniques of controlling leakage have been developed and one of technique is MTCMOS i.e. a multi-threshold complementary metal oxide semiconductor. It is a technique that is used to suppress the leakage current. As we know that low threshold voltage switches faster and is therefore applied in critical delay paths to minimize clock periods. Transistors with low threshold voltages are used for high Figure 2 MTCMOS technique and Full Subtractor with MTCMOS This technique is made to work in two conditions; one is Active mode and other is

4 Sleep mode or Standby mode. In active mode both the high threshold transistors PMOS and NMOS are turned ON as a result of which their ON resistance is so small that virtual Vdd and virtual ground functions as real power lines or rails. On the other hand, during Sleep mode or standby mode both the high threshold transistors PMOS and NMOS are turned OFF, so that the virtual lines ground and Vdd are assumed to be floating. The comparatively large leakage current estimated by sub-threshold characteristic of low threshold MOSFETs is almost completely suppressed by PMOS and NMOS since they possess high VTH and thus a much lower leakage current. In this paper 34 transistor based full subtractor has been proposed but using MTCMOS techniques, it employs 36 transistors during active mode because of two extra high threshold voltage PMOS and NMOS transistors. 4. SIMULATION RESULT The simulation of full subtractor for input and output wave form is shown in below figures. In figures the simulated leakage current waveform in conventional full subtractor and simulation for reduced leakage current waveform through MTCMOS applied full subtractor are shown. All simulations are performed at 45nm technology using cadence virtuoso tool. The results for leakage current during active and sleep modes have been observed at different voltage range of 0.3V, 0.5V0.7V and 0.9V for conventional full subtractor and MTCMOS technique based full subtractor are shown in Table 2. Figure 3 Input output Waveform of Full Substractor Figure 3 represents the input and output waveform of full subtractor that can handle three bits at a time. It includes three inputs and two outputs as difference and borrows. Table 2 Comparison of leakage Currents between simple and MTCMOS applied full subtractor during active and sleep mode. Sup ply Volt age (V) Conven tional full subtrac tor (Active Mode) in (pa) Full subtr actor Using MTC MOS (Activ e Mode ) in (pa) Conven tional full subtrac tor (Sleep Mode) in (fa) Full subtr actor Using MTC MOS (Sleep Mode ) in (fa) , From table 2, it is clear that at 45nm technology, minimum voltage that can be operated without any further leakage and distortion of output is 0.5V

5 Figure 4 Comparative analysis of leakage currents during active and sleep mode. Figure 5 Leakage current of simple full subtractor during Active Mode Figure 6 Leakage current of MTCMOS full subtractor during Active Mode. 5. CONCLUSION In this paper simulation of leakage reduction technique based full subtractor has been analyzed at different supply voltages. It was observed that minimum voltage that can be operated without any further leakage and distortion of output is 0.5V. Sleep mode \ leakage current of MTCMOS full subtractor at 0.5V was found to be 4.97fA and during active mode 1.45 pa. MTCMOS technique suppressed the leakage currents by creating virtual rails of power and ground during active mode and isolated the low Vth circuit during standby mode. The whole simulation and verification of signals was done on cadence virtuoso tool at 45nm technology. REFERENCES [1]. S. Shigematsu et al., A 1-V high-speed MTCMOS circuit scheme for powerdown applications, in Proc. IEEE Symp. VLSI Circuits Dig.Tech. Papers, pp , [2]. M. Johnson, D. Somasekhar, L.-Y. Chiou, and K. Roy, Leakage control with efficient use of transistor stacks in single threshold CMOS, IEEE Trans. VLSI Systems., vol. 10, no. 1, pp. 1 5, Feb [3]. B.S. Deepaksubramanyan and Adrian Nu nez, Analysis of Sub threshold Leakage Reduction in CMOS Digital Circuits, Proceedings of the 13 th Nasa VLSI Symposium, Post Falls, Idaho, USA, June 5-6, [4]. Khandelwal, S., Akashe, S., (2011). Design of 10T SRAM with Sleep Transistor for Leakage Power Reduction, Journal of Computational and Theoretical Nanoscience, Volume 10, Number 1, p , January [5]. Monikashree T.S, Usharani.S, Baligar,.J.S, Design and Implementation of Full Subtractor using CMOS 180nm Technology, International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 5,p , May [6]. Cheng, K.W., Tseng, C.C., "Quantum full adder and subtractor," Electronics

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