Mux-Based Latches. Lecture 8. Sequential Circuits 1. Mux-Based Latch. Mux-Based Latch. Negative latch (transparent when CLK= 0)

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1 Mux-Based Latches Lecture 8 equential Circuits Negative latch (transparent when = 0) Positive latch (transparent when = ) Peter Cheung epartment of Electrical & Electronic Engineering Imperial College London 0 0 abaey Chapter 7 UL: = Clk + Clk = Clk + Clk Based on slides from Prentice-Hall Lecture 8 - Lecture 8-2 Mux-Based Latch Mux-Based Latch M M NMO only Non-overlapping clocks Lecture 8-3 Lecture 8-4

2 Master-lave (Edge-Triggered) egister Master-lave egister Master lave Multiplexer-based latch pair 0 0 M M I 2 T 2 I 3 I 5 T 4 I 6 I T M I 4 T 3 Two opposite latches trigger on edge Also called master-slave latch pair Lecture 8-5 Lecture 8-6 educed Clock Load Master-lave egister Overpowering the Feedback Loop Cross-Coupled Pairs NO-based set-reset T I I 2 T 2 I 3 I Forbidden tate Lecture 8-7 Lecture 8-8

3 Cross-Coupled NAN izing Issues Cross-coupled NANs Added clock M 8 M 7 (Volts) W/L 5 and 6 (a) Volts 3 2 W = 0.9 µ m W = µ m time (ns) (b) W = µ m W = 0.6 µ m W = 0.7 µ m W = 0.8 µ m This is not used in datapaths any more, but is a basic building block for memory cell put voltage dependence on transistor width Transient response Lecture 8-9 Lecture 8-0 torage Mechanisms Making a ynamic Latch Pseudo-tatic tatic ynamic (charge-based) Lecture 8 - Lecture 8-2

4 Master-lave tatic Flip-flop Two-phase dynamic flip-flop Overlapping Clocks Can Cause ace Conditions Undefined ignals Lecture 8-3 Lecture 8-4 Use 2-phase non-overlapping clocks Latch + Logic Lecture 8-5 Lecture 8-6

5 Other Latches/egisters: C 2 MO sensitive to Clock-Overlap C L M 8 M 7 C L2 0 0 M 8 M 7 Master tage lave tage (a) (0-0) overlap (b) (-) overlap Keepers can be added to make circuit pseudo-static Lecture 8-7 Lecture 8-8 Pipelining Other Latches/egisters: TPC a a log log b b eference Pipelined Positive latch (transparent when = ) Negative latch (transparent when = 0) Lecture 8-9 Lecture 8-20

6 cluding Logic in TPC TPC egister PUN 2 Y M 9 M 8 PN 2 M 7 Example: logic inside the latch AN latch Lecture 8-2 Lecture 8-22 µ π latches: Poor man s TPC Latch µ π latches Final solution What is wrong with this TPC Latch? econd attempt: π-latch output stable when is high Lecture 8-23 Lecture 8-24

7 Pulse-Triggered Latches An Alternative Approach Pulsed Latches Ways to design an edge-triggered sequential cell: Master-lave Latches Pulse-Triggered Latch G G M P G ata L L2 L Clk Clk ata Clk Clk (a) register M N (b) glitch generation Clk G (c) glitch clock Lecture 8-25 Lecture 8-26 Pulsed Latches Hybrid Latch-FF Timing Hybrid Latch Flip-flop (HLFF), AM K-6 and K-7 : 3.0 P x P 3 P 2 Volts time (ns) Lecture 8-27 Lecture 8-28

8 Latch-Based Pipeline Non-Bistable equential Circuits chmitt Trigger V ou t V OH F G C C 2 C 3 VTC with hysteresis estores signal slopes V OL Compute F compute G V M V M+ V in Lecture 8-29 Lecture 8-30 Noise uppression using chmitt Trigger CMO chmitt Trigger V in V out V M+ V in V out V M t 0 t t 0 +t p t Moves switching threshold of the first inverter Lecture 8-3 Lecture 8-32

9 (V) V (V) V x chmitt Trigger imulated VTC CMO chmitt Trigger (2).5.0 V M2 V M.5.0 k= k= 2 k= 3 k= V in (V) Voltage-transfer characteristics with hysteresis V in (V) The effect of varying the ratio of the PMO device. The width is k* m. m Lecture 8-33 Lecture 8-34 Multivibrator Circuits Transition-Triggered Monostable T Bistable Multivibrator flip-flop, chmitt Trigger ELAY t d t d Monostable Multivibrator one-shot Astable Multivibrator oscillator Lecture 8-35 Lecture 8-36

10 Monostable Trigger (C-based) elaxation Oscillator A B I I2 2 C (a) Trigger circuit. C t B V M (b) Waveforms. t t 2 t T = 2 (log3) C Lecture 8-37 Lecture 8-38 Astable Multivibrators (Oscillators) Voltage Controller Oscillator (VCO) 0 2 N- chmitt Trigger restores signal slopes M6 M4 3.0 ing Oscillator V V 3 V 5 I ref M2 M I ref Volts.5.0 V contr M5 M3 Current starved inverter time (ns) simulated response of 5-stage oscillator t ph L (nsec) V contr (V ) propagation delay as a function of control voltage Lecture 8-39 Lecture 8-40

11 ifferential elay Element and VCO V o2 V o v 3 in in 2 v v 2 v 4 V ctrl delay cell 3.0 V V 2 V 3 V time (ns) simulated waveforms of 2-stage VCO two stage VCO Lecture 8-4

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