Module 4: Combinational Logic Glitches and Hazards

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1 Module 4: Combinational Logic Glitches and Hazards Wakerly: Chapter 4 (part 3) : ECEN 3233 r. Keith. Teague Spring TIME RESPONSE in Combinational Networks emphasis on timing behavior of circuits waveforms to visualize what is happening simulation to create these waveforms momentary change of signals at the outputs: hazards can be useful pulse shaping circuits can be a problem glitches: incorrect circuit operation Terms: gate delay time for change at input to cause change at output minimum delay vs. typical/nominal delay vs. maximum delay careful designers design for the worst case! rise time time for output to transition from low to high voltage fall time time for output to transition from high to low voltage 23 2

2 Pulse Shaping Circuit ' = 3 gate delays remains high for three gate delays after changes from low to high is not always! 23 3 Time Response in Combinational Networks Hazards/Glitches and How to void Them glitch is an unwanted switching at the output Glitches occur because delay paths through the circuit experience different propagation delays anger if logic "makes a decision" while output is unstable OR hazard output controls an asynchronous input (these respond immediately to changes rather than waiting for a synchronizing signal called a clock) Usual solutions: wait until signals are stable (by using a clock) never, never, never use circuits with asynchronous inputs design hazard-free circuits Suggest that first two approaches be used, but we'll tell you about hazard-free design anyway! 23 4

3 Hazards/Glitches and How to void Them Static -hazard Static -hazard Input change causes output to go from to to Input change causes output to go from to to ynamic hazards Input change causes a double change from to to to OR from to to to Kinds of Hazards 23 5 \ Time Response in Combinational Circuits G G \ C = C = input change within product term C C = ' + C' \ G \ G \ G C = C = ( is still ) C = ( is ) input change that spans product terms output changes from to to 23 6

4 General Strategy: add redundant terms = ' + C' becomes ' + C' + C' Thus, the K-map can be used to detect static hazards in two-level SOP or POS logic circuits. The presence or absence of static hazards depends on the circuit design for the logic function. properly designed two-level SOP circuit has no static- hazards, but, it may have static- hazards. static- hazard would exist in such a circuit only if a variable and its complement were connected to the same N gate which would not make sense. This eliminates the -hazard? How about -hazards? 23 7 Time Response in Combinational Networks or POS circuits, eliminate static- hazards by working with the zeros in the K-map. Cover transitions between prime implicants (groups of zeros) in a manner similar to that for SOP circuits. C properly designed two-level POS circuit has no static- hazards, but, it may have static- hazards. C static- hazard would exist in such a circuit only if a variable and its complement were connected to the same OR gate which would not make sense. 23 8

5 ynamic Hazards Example with ynamic Hazard \ G Slow \ \ G4 V ery slow G5 Three different paths from or ' to output C =, = to C =, = different delays along the paths: G slow, G4 very slow Handling dynamic hazards is very complex eyond our scope 23 9

Outline. EECS Components and Design Techniques for Digital Systems. Lec 12 - Timing. General Model of Synchronous Circuit

Outline. EECS Components and Design Techniques for Digital Systems. Lec 12 - Timing. General Model of Synchronous Circuit Outline EES 5 - omponents and esign Techniques for igital Systems Lec 2 - Timing avid uller Electrical Engineering and omputer Sciences University of alifornia, erkeley Performance Limits of Synchronous