Integrated Circuits -- Timing Behavior of Gates

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1 Integrated Circuits -- Timing ehavior of Gates Page 1

2 Gates Have Non-Linear Input/Output ehavior V cc V out 0V V in V cc Plotting Vout vs. Vin shows non-linear voltage behavior Page 2

3 Gates lso Don t React Immediately V in V out V in t prop-fall t prop-rise V out t fall t rise time t prop-fall and t prop-rise are measured from 50% of input swing to 50% of output swing t rise is measured from 10% of output swing to 90% of output swing t fall is measured from 90% of output swing to 10% of output swing Page 3

4 Kinds of Gate Delays Propagation Delays Match intuition about how fast the gate is Rising and falling delays may be different Take into acount which nodes rising, which nodes falling to compute delay through network Rising and falling delays may be the same Ignore rising/falling behavior Will use most of this semester Rise and all Times Only indirectly related to how fast the gate is Will not use in this course Page 4

5 Gate Delays Delay values are usually provided for the gates you use Use those delay values when analyzing a circuit s timing Here are the timing values we will use this chapter Wider gates are slower ND = NND+NOT, etc Type NOT ND2 ND3 ND4 NND2 NND3 NND4 OR2 OR3 OR4 NOR2 NOR3 NOR4 XOR2 XOR3 t prop 1ns 3ns 7ns 2ns 4ns 4ns 8ns 3ns 7ns Page 5

6 Critical Path nalysis Given a logic circuit, how fast will it run? How fast will its output react to changes on its inputs? ind the slowest path from any input to the output That is the critical path dd up propagation delays along that path C D C D E G Delay = t OR2 + t ND2 = 7ns Delay = 2 x t NND2 + t OR3 = 10ns Page 6

7 Kinds of Timing nalysis The more detail you provide the more accurate the result Separate t prop-rise and t prop-fall more accurate than a single t prop Take into account other effects more accurate Temperature Power supply voltage Manufacturing variation Rise/fall times Page 7

8 Environmental Delay Effects Temperature Variation Chips run faster when cool, slower when hot Voltage Variation Value of Vcc can affect delay Manufacturing Variation Two gates on the same integrated circuit may run at slightly different speeds Summary: gate delays are always given as a range of values that operational delay is guaranteed to be within. Example: 2ns +/- 0.2ns Page 8

9 Loading Effects gate that drives more circuitry is slower than a gate that drives less circuitry C D E Less heavily loaded faster More heavily loaded slower Page 9

10 Typical Loading-Dependent Delay Typical delay = t prop + k x C load Loading-independent delay Load Loading-dependent factor or MOS technology, load is mostly capacitance or bipolar technology, load is both capacitance and current Page 10

11 nalyzing Logic Network =1 C=1 G t NND2 t NND2 G Page 11

12 =1 C=1 D E G More nalysis 32ns Type NOT ND2 ND3 ND4 NND2 NND3 NND4 OR2 OR3 OR4 NOR2 NOR3 NOR4 XOR2 XOR3 t prop 1ns 3ns 7ns 2ns 4ns 4ns 8ns 3ns 7ns E C D C D E+ G 32ns 8ns 3 20ns 30ns 20ns 30ns 23ns 33ns 8ns 23ns 33ns 3 12ns 27ns 37ns 39ns Page 12

13 =1 C=1 D E G More nalysis 32ns Type NOT ND2 ND3 ND4 NND2 NND3 NND4 OR2 OR3 OR4 NOR2 NOR3 NOR4 XOR2 XOR3 t prop 1ns 3ns 7ns 2ns 4ns 4ns 8ns 3ns 7ns E C D C D E+ G 32ns 8ns 3 20ns 30ns 20ns 30ns 23ns 33ns 8ns 23ns 33ns 3 12ns 27ns 37ns 39ns Page 13

14 =1 C=1 D E G More nalysis 32ns Type NOT ND2 ND3 ND4 NND2 NND3 NND4 OR2 OR3 OR4 NOR2 NOR3 NOR4 XOR2 XOR3 t prop 1ns 3ns 7ns 2ns 4ns 4ns 8ns 3ns 7ns E C D C D E+ G 32ns 8ns 3 20ns 30ns 20ns 30ns 23ns 33ns 8ns 23ns 33ns 3 12ns 27ns 37ns 39ns Page 14

15 =1 C=1 D E G More nalysis 32ns Type NOT ND2 ND3 ND4 NND2 NND3 NND4 OR2 OR3 OR4 NOR2 NOR3 NOR4 XOR2 XOR3 t prop 1ns 3ns 7ns 2ns 4ns 4ns 8ns 3ns 7ns E C D C D E+ G 32ns 8ns 3 20ns 30ns 20ns 30ns 23ns 33ns 8ns 23ns 33ns 3 12ns 27ns 37ns 39ns Page 15

16 =1 C=1 D E G More nalysis 32ns Type NOT ND2 ND3 ND4 NND2 NND3 NND4 OR2 OR3 OR4 NOR2 NOR3 NOR4 XOR2 XOR3 t prop 1ns 3ns 7ns 2ns 4ns 4ns 8ns 3ns 7ns E C D C D E+ G 32ns 8ns 3 20ns 30ns 20ns 30ns 23ns 33ns 8ns 23ns 33ns 3 12ns 27ns 37ns 39ns Page 16

17 =1 C=1 D E G More nalysis 32ns Type NOT ND2 ND3 ND4 NND2 NND3 NND4 OR2 OR3 OR4 NOR2 NOR3 NOR4 XOR2 XOR3 t prop 1ns 3ns 7ns 2ns 4ns 4ns 8ns 3ns 7ns E C D C D E+ G 32ns 8ns 3 20ns 30ns 20ns 30ns 23ns 33ns 8ns 23ns 33ns 3 12ns 27ns 37ns 39ns Page 17

18 =1 C=1 D E G More nalysis 32ns Type NOT ND2 ND3 ND4 NND2 NND3 NND4 OR2 OR3 OR4 NOR2 NOR3 NOR4 XOR2 XOR3 t prop 1ns 3ns 7ns 2ns 4ns 4ns 8ns 3ns 7ns E C D C D E+ G 32ns 8ns 3 20ns 30ns 20ns 30ns 23ns 33ns 8ns 23ns 33ns 3 12ns 27ns 37ns 39ns Page 18

19 Completing a Timing Diagram Method Do most upstream signals first E and in previous picture or every instant in timing diagram Compute each gate output as function of input(s) Place new gate output after appropriate delay on timing diagram. Move to downstream signals Page 19

20 Glitch ehavior Does the glitch propagate to the ND output?? Page 20

21 ehavior #1 Called transport delay ll glitches, no matter how narrow are propagated to output Page 21

22 ehavior #2 Called inertial delay Glitches narrower than some threshold are filtered out Page 22

23 Which ehavior Is Correct? Wires usually exhibit transport delay Gates usually exhibit some form of inertial delay Regardless, both wires and gates will filter out (or change the waveform shape of) extremely narrow pulses We will use transport for both gates and wires since we don t know the pulse width thresholds Page 23

24 Completing a Timing Diagram Shortcut Method ocus on input changes (edges) Everything constant in between Page 24

25 Pulse Generator Pulse width = 3 x t NOT = = 0 so why the pulse? Due to gate delays Page 25

26 More Dynamic Gate ehavior What will this circuit do? It will oscillate ( ) Pulse width = t NOT Period of oscillation is 2 x t NOT Page 26

27 Logic Hazards C C This is the conventional KMap solution = + C Page 27

28 Gates Have Real Timing Need to take into account timing of this inverter g1 g2 =1 g1 C=1 g2 Called a hazard or false output static equations indicate =1 but dynamic behavior gives a glitch Page 28

29 Hazards Each prime implicant from KMap is implemented using a single ND gate When moving between implicants, gates turn off and on at different times C 0 1 Momentarily get false outputs = C=1 Page 29

30 Hazard-ree Logic Design Make sure all prime implicants overlap C Redundant but will eliminate false output C C g2 g1 g3 = + C + C On C = 111 to C = 011, g3 will hold high entire time. Page 30

31 =1 g1 No alse Output C=1 g2 =1 C=1 g3 g1 g2 g3 holds high whole time g3 Page 31

32 nother Example Rule: No 2 adjacent 1 s should be in different implicants CD CD = CD + C This is not hazard-free = CD + C + D This is hazard-free Page 32

33 When To Do Hazard-ree Design? Do you always need to do HD? No Do it when you need to generate a signal which will not glitch Interfacing with other circuitry which is sensitive to edges synchronous memories Page 33

34 Caveat Will only work for single-input changes Other techniques for multiple-input changes Page 34

14:332:231 DIGITAL LOGIC DESIGN. Gate Delays

14:332:231 DIGITAL LOGIC DESIGN. Gate Delays 4:332:23 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all 23 Lecture #8: Timing Hazards Gate Delays hen the input to a logic gate is changed, the output will not