Department of EECS. University of California, Berkeley. Logic gates. September 1 st 2001

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1 Department of EECS University of California, Berkeley Logic gates Bharathwaj Muthuswamy and W. G. Oldham September 1 st Introduction This lab introduces digital logic. You use commercially available Quad NAND Gates to breadboard some simple logic functions, especially the NOT gate and the XOR gate. You will build a simple logic probe with an LED and verify static logic operation. You will also measure propagation delays by using the oscilloscope. 2. Commercial NAND Gates In this lab, you will be using the CMOS NAND gate family to construct logic circuits. In particular, you will be using the MM74HC00, a Quad NAND array (or the Quad NAND chip ). You will need more than one chip to construct the NOR function. NOTE : This is a TOP VIEW. The tiny half circle helps you orient the chip package to the diagram. Figure 1. The MM74HC00 There are 4 NAND gates in one package (see connection diagram above), hence it is named Quad NAND. Two special symbols require attention. One is the Vcc designation on pin 14; this is the power to the chip and is from +2 to +6V 1. The other is GND on pin 7, where you will connect the circuit ground. The full data sheets are attached at the end of this document. 3. Normal Operation and Absolute Maximum Ratings Please observe from the data sheets especially the Absolute Maximum Ratings. In particular: 1 DO NOT USE A NEGATIVE VOLTAGE OR A VOLTAGE VALUE HIGHER THAN +7 V, OTHERWISE YOU WILL DESTROY THE CHIP.

2 1) the VCC pin CANNOT BE MADE NEGATIVE of ground 2) the inputs, Aor B CANNOT BE MADE NEGATIVE of ground 3) the inputs are NOT ALLOWED TO EXCEED V CC The latter caution is somewhat subtle and particularly easy to violate (burning out the chip). For example if you are studying normal operation at 5V you may be tempted to use logic levels of 0 and 5 V at the inputs. Now if you turn down V CC and you continue to drive the inputs with a 5V logic signals, you will violate rule 3!!!! THEREFORE BE CAREFUL TO NEVER DRIVE THE INPUTS WITH VOLTAGES EXCEEDING V CC. Another feature to note from the data sheets is the dependence of the gate delay performance on V CC. Nominal worst case operation is at V CC = 4.5V (because that is the lower end of the nominal power supply range of 5V +/- 10%). But these devices are also designed to work at much lower values of V CC, down to 2V. This provides a great opportunity to observe gate delays in a regime where they are very easy to measure. 4. Logic detector circuit and its calibration To detect the logic level of a given circuit node one can of course use a voltmeter or scope. But for static measurements it is attractive to have a simple visual indicator. You can build such a logic probe using an LED in series with a resistor. Note that the LED is a diode with a polarity you must orient it properly. The amount of current you need (typically from 1 to 10 ma) to be able to clearly see the LED light depends on the LED efficiency. The high current end is limited by the output of the NAND gate which is about 10mA at 5V. Assuming a diode drop of about 1.6 to 1.8V, a resistor in the range of 300 ohms may be adequate for the full voltage range, but you must test your detector for correct operation and adequate LED brightness over the range 2 to 5V. WARNING: YOU CAN DAMAGE both the LED and the logic chip if you have too low a resistance. In no case use less than 200 ohms. Observe the brightness and write it down in your report at 2V and 5V applied. Logic LED Ground 5. Chain of inverters Before studying an XOR gate constructed from NAND gates, we want you to first measure a much simpler circuit; a chain of inverters. Using one chip you construct a chain of 4 gates. This simple circuit will allow you to verify your static logic level detector and to calibrate your measurement of gate delay. On your lab report sheet draw the circuit diagram of the chain of inverters constructed using the MM74HC. (That means the top view of the MM74HC plugged into your prototype board and the wiring used to complete the circuit. HINT: no single pin on the package should be without at least one connection.). In this diagram you can show the internal wiring of the prototype board explicitly. R

3 Calibration a) Verify your static logic probe operation at 2 to 5V using a simple power supply. Note the brightness in your lab report. b) Verify the static operation of the chain of inverters. c) Measure the delay of 4 inverters, 3 inverters, two inverters and a single inverter using the oscilloscope. Measure at V CC = 2V, 5V. (To do this you use the square wave generator to drive the input and to trigger the scope. You can look at the scope trace to measure the gate delay. For example to measure the gate delay through gate 3 you measure the time between when the input reaches 50% and the time the output reaches 50%.) Assuming that the probe disturbs the delay (by adding capacitance), you can estimate this disturbance from the measurements above. In particular, the difference between 1 gate and 3 gates represents two times the average gate delay. τ low to high + τ high to low τ propagationdelay = 2 6. The XOR Function: In the prelab you showed the NAND realization of the XOR function. Although this may not be an optimal design it will work and it will have at most 3 gate delays (one inverter and two NAND delays). On your lab report draw the layout on your prototype board of an XOR circuit using 2 MM74HC packages. Show all wires including the hidden wires in the prototype board. You will of course use 5 NAND gates plus one more to act as the load on the output. (Show this one too in your circuit). Short the inputs on the two unused NAND gates to ground and leave the outputs open. Construct the XOR circuit, and verify its operation with your logic probe. Fill out the truth table on your lab report. 7. Propagation Delay of the XOR You have loaded the output with a spare NAND gate input so that in the following you are measuring the delay of an XOR gate with fanout of 1. Show the circuit to your TA and show proper logic functionality. 7. Now measure the XOR delay at 2V and 5V. AGAIN: THE INPUT LOGIC VOLTAGE CANNOT EXCEED V CC!!! Use the same technique as above: The square wave generator as pulse source and the scope as instrument to measure the 50% point which defines the logic delay. See part 8 below as a variation on how to measure the delay (and seek help from your TA as needed). 8. Using the oscilloscope as logic probe If there is time attempt to use the oscilloscope in the logic analyzer mode to measure gate delay. Comment on the ease of using this mode compared to the basic visual mode.

MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power

4 MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to September 1983 Revised February 1999 static discharge by internal diode clamps to V CC and ground. Features Typical propagation delay: 8 ns Wide power supply range: 2 6V Low quiescent current: 20 µa maximum (74HC Series) Low input current: 1 µa maximum Fanout of 10 LS-TTL loads MM74HC00 Quad 2-Input NAND Gate Ordering Code: Order Number Package Number Package Description MM74HC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow MM74HC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Logic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View 1999 Fairchild Semiconductor Corporation DS prf

5 2 MM74HC00 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (V CC ) 0.5 to +7.0V DC Input Voltage (V IN ) 1.5 to V CC +1.5V DC Output Voltage (V OUT ) 0.5 to V CC +0.5V Clamp Diode Current (I IK, I OK ) ±20 ma DC Output Current, per pin (I OUT ) ±25 ma DC V CC or GND Current, per pin (I CC ) ±50 ma Storage Temperature Range (T STG ) 65 C to +150 C Power Dissipation (P D ) (Note 3) 600 mw S.O. Package only 500 mw Lead Temperature (T L ) (Soldering 10 seconds) 260 C Recommended Operating Conditions Min Max Units Supply Voltage (V CC ) 2 6 V DC Input or Output Voltage 0 V CC V (V IN, V OUT ) Operating Temperature Range (T A ) C Input Rise or Fall Times (t r, t f ) V CC = 2V 1000 ns V CC = 4.5V 500 ns V CC = 6.0V 400 ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: 12 mw/ C from 65 C to 85 C. DC Electrical Characteristics (Note 4) Symbol Parameter Conditions V CC T A = 25 C T A = 40 to 85 C T A = 55 to 125 C Units Typ Guaranteed Limits V IH Minimum HIGH Level 2.0V V Input Voltage 4.5V V 6.0V V V IL Maximum LOW Level 2.0V V Input Voltage 4.5V V 6.0V V V OH Minimum HIGH Level V IN = V IH or V IL Output Voltage I OUT 20 µa 2.0V V 4.5V V 6.0V V V IN = V IH or V IL I OUT 4.0 ma 4.5V V I OUT 5.2 ma 6.0V V V OL Maximum LOW Level V IN = V IH Output Voltage I OUT 20 µa 2.0V V 4.5V V 6.0V V V IN = V IH I OUT 4.0 ma 4.5V V I OUT 5.2 ma 6.0V V I IN Maximum Input V IN = V CC or GND 6.0V ±0.1 ±1.0 ±1.0 µa Current I CC Maximum Quiescent V IN = V CC or GND 6.0V µa Supply Current I OUT = 0 µa Note 4: For a power supply of 5V ±10% the worst case output voltages (V OH, and V OL ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case V IH and V IL occur at V CC = 5.5V and 4.5V respectively. (The V IH value at 5.5V is 3.85V.) The worst case leakage current (I IN, I CC, and I OZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used.

MM74HC00 Quad 2-Input NAND Gate

MM74HC00 Quad 2-Input NAND Gate Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard