Exercise 1: Tri-State Buffer Output Control
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1 Exercise 1: Tri-State Buffer Output Control EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate how the enable and data inputs control the output state of a tri-state buffer. You will verify your results with an oscilloscope. EXERCISE DISCUSSION This is the schematic symbol for a tri-state buffer circuit. A tri-state buffer circuit consists of several transistors. The ENABLE (EN) INPUT is often referred to as the output enable input. The other transistors in the tri-state buffer circuit are simply represented by CONTROL 1, CONTROL 2, AND S FACET by Lab-Volt
2 Tri-State Output The tri-state buffer has a data input and an enable (EN) input. The output is between the Q1 emitter and the Q2 collector. The tri-state buffer output circuit consists of a. b. one transistor called the enable transistor. How many output states can a tri-state buffer have? a. 1 b. 2 c. 3 A tri-state buffer has three output states: high impedance (high-z), high (logic 1), or low (logic 0). The two tri-state buffer inputs, DATA INPUT and ENABLE (EN) INPUT, control the output logic state. FACET by Lab-Volt 237
3 What input causes the tri-state buffer output to be in the high-z state? a. DATA INPUT b. ENABLE (EN) INPUT When the EN input is low, the tri-state buffer is disabled because CONTROL 1 disconnects the data input by opening S1. CONTROL 2 turns off transistors Q1 and Q2. With transistors Q1 and Q2 turned off (not conducting), the output is effectively disconnected from the buffer. The buffer circuit is a high impedance to any loads or devices connected to the output. With the EN input low, the tri-state buffer output is in the high impedance (high-z) state. 238 FACET by Lab-Volt
4 Tri-State Output When the EN input is low, a. output transistor Q1 conducts and output transistor Q2 does not conduct. b. output transistors Q1 and Q2 conduct. c. output transistors Q1 and Q2 do not conduct. When the EN input is high, the output is in what logic state(s)? a. high or low b. high-z When EN is high, the tri-state buffer is enabled because CONTROL 1 connects the data input by closing S1. A high (logic 1) data input causes CONTROL 2 to turn on transistor Q1 and turn off transistor Q2. FACET by Lab-Volt 239
5 With transistor Q1 conducting (on) and transistor Q2 not conducting (off), the output is high (logic 1) because it is connected to V CC (5 Vdc) through Q1. When the EN and data inputs are high, the output is high because transistor a. Q1 conducts and transistor Q2 does not conduct. b. Q2 conducts and transistor Q1 does not conduct. A low (logic 0) data input causes CONTROL 2 to turn off transistor Q1 and turn on transistor Q2. With transistor Q1 not conducting (off) and Q2 conducting (on), the output is low (logic 0) because it is connected to ground (0 Vdc) through Q FACET by Lab-Volt
6 Tri-State Output When the EN input is high and the data input is low, the output connects to a. V CC (5 Vdc) through Q1. b. ground through Q2. The following truth table sums up the input/output logic states for the tri-state buffer. PROCEDURE Locate the TRI-STATE OUTPUT circuit block and the INPUT SIGNALS circuit block. Put a two-post connector in the terminals at BLOCK SELECT. FACET by Lab-Volt 241
7 Connect A at the INPUT SIGNALS circuit block to A (INPUT) at the TRI-STATE OUTPUT circuit block. Connect B at the INPUT SIGNALS circuit block to B (OUTPUT ENABLE) at the TRI-STATE OUTPUT circuit block. At the INPUT SIGNALS circuit block, set toggle switches A and B to the LOW position. This puts a logic 0 (low) to the data input (INPUT) and to the enable input (OUTPUT ENABLE) of the tri-state buffer. With a logic 0 at the OUTPUT ENABLE input, what is the logic state of the output? a. logic 0 b. logic 1 c. high-z 242 FACET by Lab-Volt
8 Tri-State Output Connect the channel 1 probe of the oscilloscope to the OUTPUT of the tri-state buffer. Connect the probe ground clip to a ground terminal on the circuit board. While observing channel 1 on the oscilloscope, set toggle switch A at the INPUT SIGNALS circuit block to the HIGH position and back to the LOW position. This changes the logic level at the data input (INPUT) of the tri-state buffer from logic 0 to logic 1 and back to logic 0. Does the tri-state buffer output logic state change with the change of the input logic state? a. yes b. no FACET by Lab-Volt 243
9 What logic state is required at the OUTPUT ENABLE input of the tri-state buffer to enable the output? a. logic 0 b. logic 1 c. high-z Set toggle switch B at the INPUT SIGNALS circuit block to the HIGH position. This puts a logic 1 to the OUTPUT ENABLE input of the tri-state buffer. While observing channel 1 on the oscilloscope, set toggle switch A at the INPUT SIGNALS circuit block to the HIGH position and then to the LOW position. This changes the logic level at the INPUT of the tri-state buffer from logic 0 to logic 1 and back to logic FACET by Lab-Volt
10 Tri-State Output Does the tri-state buffer output logic state change with the change of the input logic state? a. yes b. no While observing channel 1 on the oscilloscope, set toggle switch A at the INPUT SIGNALS circuit block to the HIGH position. This puts a logic 1 at the INPUT of the tri-state buffer. What is the logic state of the output? a. logic 0 b. logic 1 c. high-z FACET by Lab-Volt 245
11 When the tri-state buffer output is logic 1, what output totem pole transistor is on (conducting)? a. top b. bottom c. neither While observing channel 1 on the oscilloscope, set toggle switch A at the INPUT SIGNALS circuit block to the LOW position. This puts a logic 0 at the INPUT of the tri-state buffer. What is the logic state of the output? a. logic 0 b. logic 1 c. high-z 246 FACET by Lab-Volt
12 Tri-State Output When the tri-state buffer output is logic 0, what output totem pole transistor is on (conducting)? a. top b. bottom c. neither Set toggle switch B at the INPUT SIGNALS circuit block to the LOW position. This puts a logic 0 at the OUTPUT ENABLE input of the tri-state buffer. What is the logic state of the output? a. logic 0 b. logic 1 c. high-z When the tri-state buffer output is in the high-z state, what output totem pole transistor is on (conducting)? a. top b. bottom c. neither FACET by Lab-Volt 247
13 CONCLUSION A tri-state buffer has three output states: high (logic 1), low (logic 0), and high impedance (high-z). When the enable input (OUTPUT ENABLE) is logic 0, the tri-state buffer is in the high impedance (high-z) state. When the enable input (OUTPUT ENABLE) is logic 1, the tri-state buffer output equals the logic state of the input. REVIEW QUESTIONS 1. The output states of a tri-state buffer are a. high or low. b. low or high-z. c. high or high-z. d. low, high, or high-z. 2. The output circuit of a tri-state buffer consists of a. several transistors connected in series and in parallel. b. c. two diodes connected in parallel. d. a diode and one transistor connected in parallel. 3. The input states of the tri-state buffer are shown. The output is a. low. b. high. c. high-z. d. indeterminate. 4. The input states of the tri-state buffer are shown. The output is a. low. b. high. c. high-z. d. indeterminate. 5. The input states of the tri-state buffer are shown. The output is a. low. b. high. c. high-z. d. indeterminate. 248 FACET by Lab-Volt
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