GATES AND SIMPLE DEVICES SUPPLEMENT

Transcription

1 GTES ND SIMPLE DEVICES SUPPLEMENT Dr. Ken Hoganson, ll Rights Reserved. SUPPLEMENT CONTENTS S.1 Selector.. 2 S.2 Multiplexor 3 S.3 Demultiplexor 3 S.4 Multiplexor/Demultiplexor Pair 4 S.5 Simple Memory Device. 5 S.6 Half-dder/dder.. 6

2 2 S.1 Selector The first device to be considered is a selector (Fig. D.1). This device is of limited use by itself, but is a building-block for other more sophisticated constructions. This device allows the selection of one of two inputs, using a single control line. Figure C.1: Selector In this figure, the control line is labeled for Clock. When the clock is high (1), only the input at produces an output that can vary. The value at does not matter, since the results\ of the ND at is guaranteed to be low (0) by the complement of the (which is 0 when is 1). When the clock is low (0), the input at is irrelevant, only can affect the output of it s ND gate. The control line determines which input, or can have any affect on the outputs. This building block will be utilized in the following devices. Copyright 2007, 2010, Ken Hoganson, Ph.D., ll Rights Reserved.

3 3 S.2 2:1 Multiplexor The next device takes the selector and builds a multiplexor (Fig. D.2). The multiplexor is a device that allows multiple inputs to take turns sharing one output. In this example, 2 inputs are combined into one shared output line. The value of the control line determines which input ( or ) flows through to the output. Shared Line Figure C.2: 2:1 Multiplexor When the is high (1), then the value at input flows through the ND gate, and determines the value of the output after the OR. The value at is irrelevant because the inverted forces the value at its ND to a zero. Therefore, the output of the OR will only be 1 if the input at is 1. S.3 1:2 Demultiplexor The demultiplexor (Fig. D.3) does the opposite of a multiplexor: it takes a single input and sends it to one of two outputs, depending on the value of a control line. This device is very similar to the Selector, but with the inputs wired together. In Figure C.3: 1:2 Demultiplexor Copyright 2007, 2010, Ken Hoganson, Ph.D., ll Rights Reserved.

4 4 S.4 Combined Multiplexor and Demultiplexor The multiplexor and demultiplexor are used together to allow sharing a communication line. When the devices are tied together with a common clock, they allow multiple lines to share a common data line. The following diagram (Fig. D.4) shows two input lines sharing a single common data line, but the concept can be expanded to many inputs, all taking turns using a common data line. Shared Data Line 2:1 Multiplexor Common Clock Line 1:2 Demultiplexor Figure C.4: Multiplexor System The multiplexor/demultiplexor pair is a classic data communications device, allowing shared access over both short and long distances. If the cost of the shared line is high, because it must go long distances or perhaps because the short distances is a part of a many bit/line bus, a multiplexor/demultiplexor pair can reduce overall cost of the communication link. If the multiplexor/demultiplexor pair is controlled by a single clock line (as in the above diagram), it is using Time Division Multiplexing (TDM), where access to the shared line rotates over time, depending on the values of the clock line. Copyright 2007, 2010, Ken Hoganson, Ph.D., ll Rights Reserved.

5 5 S.5 Simple Memory Device The simple 2:1 multiplexor of Figure D-2 can be used as the foundation for a simple memory device. memory device should retain its current value which can be read, and allow new values to be written to it. single control line can be used to select between these two functions (Read/Write). In the following diagram (Fig. D-4), the heavy RED line shows the feedback that is a crucial component of memory devices. The feedback line allows the current output to flow back in as an input in order for the device to maintain its currently stored value. When the control line is 0 (RED), the output flows back around through the ND gate, and back into the OR gate. The current output, regardless of whether it is a 0 or 1 determines the future output. Data In Out Ctrl Feedback Figure C.5: Simple Memory Device In order to store (WRITE) a new value into the device, the value to be written must be present on the input, and then the Ctrl line is set to 1 (WRITE). In this state, the input flows through its ND gate to determine the value of the OR gate. If the input is a 1, the output becomes a 1. If the input is a 0, the output becomes a 0. Copyright 2007, 2010, Ken Hoganson, Ph.D., ll Rights Reserved.

6 6 S.6 ddition Circuit simple circuit with only four gates can implement the addition of two bits a core operation required of a computer. This is implemented in a device call a Half-dder. [Called a Half-dder because two are needed to when there could be a carry from a lower bit addition.] truth table that explains the function of the Half-dder follows: Sum S 1 S Table C.1 Half-dder The device has two input bits, labeled and. Those two bits are added together to produce a SUM. The SUM consists of two bits, S 0 for the ones column and S 1 for the twos column when two 1s add together to make a 2. Note that the production of the ones column (S 0 ) looks like an OR operation, producing a 1 for the output if either of the inputs is a 1, but not when OTH inputs are a one. [This is known as an Exclusive-OR]. The production of the two s column (S 1 ) looks like an ND producing a 1 only with OTH inputs are a 1. These observations are the key to building the Half-dder. S 0 S 1 Figure C.6: ddition of two bits Note that in Fig. D.6, the Half-dder ORs the two inputs to produce the low-order bit (S 0 ), and uses an ND to produce the high-order bit (S 1 ). The invertor and ND are used together to produce the correct low-order bit (S 0 ), in the case when OTH inputs are 1. In that case, the output of the OR must be turned-off. Copyright 2007, 2010, Ken Hoganson, Ph.D., ll Rights Reserved.