What you can do with very little:

Size: px

Start display at page:

Download "What you can do with very little:"

Ashlee Bates
6 years ago
Views:

1 page How Computers Work Lecture 3 irect Execution RISC Processor: The Unpipelined ET How Computers Work Lecture 3 Page What you can do with very little: Each instruction class can be implemented using a few simple components. Components: LU Instruction W W W Register File (-port) R R/W ata How Computers Work Lecture 3 Page

2 page r r r Review: β Model of Computation Processor State Instruction 3 bits (4 bytes) Fetch/Execute Loop: Fetch <> <pc>+ Execute fetched instruction Repeat! 3 bits next instr r3 always How Computers Work Lecture 3 Page 3 Review: ET Instructions Two 3-bit Instruction Formats: Ra Unused Rb Rc Ra 6 bit Constant Rc How Computers Work Lecture 3 Page 4

3 page 3 Review: β LU Operations What the machine sees (3-bit instruction word): Ra Unused What we prefer to see: symbolic SSEMLY LNGUGE (ra, rb, rc) lternative instruction format: C(ra, const, rc) Rb Rc rc <ra>+<rb> ddthecontentsofratothecontentsof rb; store the result in rc Ra 6 bit Constant Rc rc <ra> + sext(const) SIMILRLY FOR: SU, SUC (optional) MUL, MULC IV, IVC ITWISE LOGIC: N, NC OR,ORC XOR, XORC SHIFTS: SHL, SHR, SR (shift left, right; shift arith right) COMPRES CMPE, CMPLT, CMPLE ddthecontentsofratoconst;storetheresultinrc How Computers Work Lecture 3 Page 5 escending ata Flow View of the eta Operate class: Rc <- <Ra> op <Rb> XR R(R3,XR,XP) 3:6 5: :5 4: R C R RC + SEL LUFN LU op SEL WSEL W W W W RC MEM RF How Computers Work Lecture 3 Page 6 3

4 page 4 Combinational Read Port on ddress <ddress> How Computers Work Lecture 3 Page 7 ata Register Works like a camera =image = picture E = On/Off Switch clock = shutter release button E Clock How Computers Work Lecture 3 Page 8 4

5 page 5 Register w/ Enable E clk clk clk E E How Computers Work Lecture 3 Page 9 -Port (independent Read addresses) R Write ddress Write Enable Write ata CLK 5 3 W W Register File (-port) 3 3 R CLK W W <> new <> Note: <R3> lways ERO! (Independent Read ata) What if (say) W=??? reads value from last cycle! How Computers Work Lecture 3 Page 5

6 page 6 Selector (a.k.a. Multiplexor / MUX) Output is selected to be of N inputs N is a power of K select inputs, K = log(n) May be ganged to select one W-bit word out of N multi-bit words N- N W S K S K W = s = s How Computers Work Lecture 3 Page escending ata Flow View of the eta Operate class: Rc <- <Ra> op <Rb> XR R(R3,XR,XP) 3:6 5: :5 4: R C R RC + SEL LUFN LU op SEL WSEL W W W W RC MEM RF How Computers Work Lecture 3 Page 6

7 page 7 escending ata Flow View of the eta Operate class: Rc <- <Ra> op C XR R(R3,XR,XP) 3:6 5: :5 4: R C R RC + SEL LUFN LU op SEL WSEL W W W W RC MEM RF How Computers Work Lecture 3 Page 3 Review: β ranches Conditional: rc = <>+; then RN(ra, label, rc) if <ra> nonzero then <- <> + displacement R(ra, label, rc) if <ra> zero then <- <> + displacement Unconditional: R(r3, label, rc) Indirect: JMP(ra, rc) rc = <>+; then <- <> + displacement Note: rc = <>+; then displacement is coded as a <- <ra> CONSTNT in afieldofthe instruction! How Computers Work Lecture 3 Page 4 7

8 page 8 escending ata Flow View of the eta Rc <- <>+; if <Ra>= then <- <>+C XR R(R3,XR,XP) 3:6 5: :5 4: R C R RC + SEL LUFN LU op SEL WSEL W W W W RC MEM RF How Computers Work Lecture 3 Page 5 escending ata Flow View of the eta JMP: Rc <- <>+; <- <Ra> + C XR R(R3,XR,XP) 3:6 5: :5 4: R C R RC + SEL LUFN LU op SEL WSEL W W W W RC MEM RF How Computers Work Lecture 3 Page 6 8

9 page 9 Review: β Loads & Stores L(ra, C, rc) rc < Mem[<ra> + sext(c)] > Old New ST(rc, C, ra) ST(ra, C, rc) Mem[<ra> + sext(c)] <rc> Mem[<rc> + sext(c)] <ra> How Computers Work Lecture 3 Page 7 Straightening Out Store Old Format: ST(Rc, C, Ra) Mem[<Ra> + C] <- <Rc> ST(R,, R3) means Mem[<R3> + ] <- <R> NewFormat:ST(Ra,C,Rc) Mem[<Rc> + C] <- <Ra> ST(R,, R3) means Mem[<R3> + ] <- <R> oth versions of Store work from left to right in assembly language. ifference is only in the binary encoding of the instruction, and the hardware implementation s decoding of the binary encoding. How Computers Work Lecture 3 Page 8 9

10 page escending ata Flow View of the eta L: Rc <- Mem[<Ra>+C] XR R(R3,XR,XP) 3:6 5: :5 4: R C R RC + SEL LUFN LU op SEL WSEL W W W W RC MEM RF How Computers Work Lecture 3 Page 9 escending ata Flow View of the eta ST: Mem[<Rc>+C] <- <Ra> XR R(R3,XR,XP) 3:6 5: :5 4: R C R RC + SEL LUFN LU op SEL WSEL W W W W RC MEM RF How Computers Work Lecture 3 Page

11 page LR Load Relative Used for loading large (3 bit) constants with data from the instruction stream. epends on the fact data and instruction memory are ports of one main memory. Use: LR (label, Rc) RTL escription: Rc <- <Mem[<Next> + Offset]> Note that Ra is ignored, Offset is calculated from label LR (label, R) R (label + ) label: How Computers Work Lecture 3 Page escending ata Flow View of the eta LR: Rc <- Mem[<>++C] XR R(R3,XR,XP) 3:6 5: :5 4: R C R RC + SEL LUFN LU op SEL WSEL W W W W RC MEM RF How Computers Work Lecture 3 Page

12 page Control Logic Truth Table We can specify it via a table of the form... Control Logic Inputs: OP O L ST R RN JMP LR (Illegal) Control Logic Outputs: SEL SEL SEL WSEL LUFN Wr RF WSEL YOU should be able to fill in this table! How Computers Work Lecture 3 Page 3 Next Time - How to dd How Computers Work Lecture 3 Page 4

Pipelined Beta. Handouts: Lecture Slides. Where are the registers? Spring /10/01. L16 Pipelined Beta 1

Pipelined Beta. Handouts: Lecture Slides. Where are the registers? Spring /10/01. L16 Pipelined Beta 1 Pipelined Beta Where are the registers? Handouts: Lecture Slides L16 Pipelined Beta 1 Increasing CPU Performance MIPS = Freq CPI MIPS = Millions of Instructions/Second Freq = Clock Frequency, MHz CPI =