Lecture Topics. Announcements. Today: Pipelined Processors (P&H ) Next: continued. Milestone #4 (due 2/23) Milestone #5 (due 3/2)
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1 Lecture Topics Today: Pipelined Processors (P&H ) Next: continued 1 Announcements Milestone #4 (due 2/23) Milestone #5 (due 3/2) 2 1
2 ISA Implementations Three different strategies: single-cycle implementation multi-cycle implementation pipelined implementation Many different implementations possible within a particular framework 3 Multi-Cycle Implementation Let an instruction take more than one clock cycle to complete Break up instructions into steps where each step takes one clock cycle Clock period is much shorter Not every instruction takes the same number of clock cycles Worst case is Load instruction 4 2
3 Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 LW IFetch Dec Exec Mem WB Cycle 1 fetch instruction, update PC Cycle 2 decode, read registers, extend offset Cycle 3 calculate address (R[rs] + imm16) Cycle 4 read value from data memory Cycle 5 write value into register file 5 Summary Instructions take at least 3 clock cycles: Cycle 1 fetch instruction, update PC Cycle 2 decode, read registers, extend offset Cycle 3 R: SW: LW: CTI: perform operation calculate address (R[rs] + imm16) calculate address (R[rs] + imm16) transfer control (complete) 6 3
4 Summary (continued) Some instructions take 4 or 5 cycles Cycle 4 R: SW: LW: write value into register file (complete) write value into data memory (complete) read from data memory Cycle 5 LW: write value into register file (complete) 7 Multi-Cycle Pros and Cons Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch Uses the clock cycle efficiently the clock cycle accommodates the slowest instruction step Requires additional internal state registers, more MUXes, and more complicated (FSM) control 8 4
5 Single Cycle vs. Multi-Cycle Timing Single Cycle Implementation: Clk Cycle 1 Cycle 2 lw sw Waste multicycle clock slower than 1/5 th of Multiple Cycle Implementation: single cycle clock due to state register overhead Clk Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R-type IFetch 9 Pipelined Implementation Let an instruction take more than one clock cycle to complete Break up instructions into steps where each step takes one clock cycle Clock period is much shorter Every instruction takes the same number of clock cycles (no work in some cycles) Overlap stages of different instructions 10 5
6 Patterson s Laundry Example Ann, Brian, Cathy, Dave each has one load of clothes to wash, dry, and fold A B C D Washing takes 30 minutes Drying takes 40 minutes Folding takes 20 minutes 11 6 PM Midnight Time T a s k O r d e r A B C D Sequential laundry takes 6 hours for 4 loads 12 6
7 6 PM Midnight Time T a s k O r d e r A B C D Pipelined laundry takes 3.5 hours for 4 loads (start next task as soon as possible) 13 6 PM T a s k O r d e r A B C D Time Pipelining: multiple tasks operating simultaneously using different resources Pipelining doesn t help latency of single task, it helps throughput of entire workload Pipeline rate is limited by slowest pipeline stage 14 7
8 T a s k O r d e r 6 PM Time A B C D Potential speed up equals number of pipeline stages Time to fill pipeline and time to drain it reduces speed up Stall pipeline to handle dependencies 15 MIPS Pipelined Implementation Classic five-stage model: IF: Fetch instruction from memory ID: Decode instruction and read registers EX: Execute operation or calculate address MEM: Access memory operand WB: Write result back to register 16 8
9 MIPS Pipelined Implementation Pipeline registers used to hold bits between stages 17 Pipelined Performance How much of an improvement should we expect with a pipelined implementation (compared to single-cycle)? If the work is equally divided among the pipeline stages (the stages are balanced), the speed-up should be equal to N (the number of pipeline stages) In practice, speed-up is lower than N 18 9
10 Pipelined Performance Times for stages: 100ps for register read or write 200ps for other stages Instr Instr fetch Register read ALU op Memory access Register write Total time lw 200ps 100 ps 200ps 200ps 100 ps 800ps sw 200ps 100 ps 200ps 200ps 700ps R-format 200ps 100 ps 200ps 100 ps 600ps beq 200ps 100 ps 200ps 500ps 19 Pipelined Performance Single-cycle (T c = 800ps) Pipelined (T c = 200ps) 20 10
11 Pipelined Performance Example: 3 instructions single-cycle: 2,400 ps pipelined: 1,400 ps Ratio is approximately 1.7 to 1 Time to fill and drain pipeline has disproportionate impact on ratio 21 Pipelined Performance Example: 1,000,003 instructions single-cycle: 800,002,400 ps pipelined: 200,001,400 ps Ratio is approximately 4 to 1 Limitations on speed-up: stages not balanced overhead to capture info between stages 22 11
12 MIPS ISA Design and Pipelining All instructions are 32 bits: fetch and decode in one cycle Regular instruction formats: can decode instruction and read registers in one stage Load/store instructions: calculate address in 3 rd stage, access memory in 4 th stage Memory operands must be aligned: memory access takes only one cycle 23 MIPS Pipelined Implementation Pipeline registers capture results at end of stages All instructions forced into same framework 24 12
13 IF Stage: LW (and all instructions) 25 ID Stage: LW (and all instructions) 26 13
14 EX Stage: LW 27 MEM Stage: LW 28 14
15 WB Stage: LW Wrong register number 29 Corrected Datapath Use 5-bit register number from MEM/WB pipeline register 30 15
16 EX Stage: SW First two stages the same 31 MEM Stage: SW 32 16
17 WB Stage: SW Nothing to do SW does not update a register 33 EX Stage: R-Format First two stages the same 34 17
18 MEM Stage: R-Format Nothing to do does not access memory 35 WB Stage: R-Format 36 18
19 MIPS Pipelined Implementation Five stages in the pipeline Clock cycle long enough to handle work which must be completed in one stage Every instruction uses all 5 stages (but no work done in some stages for some instructions) Overlap execution: different instructions in each of the 5 stages simultaneously 37 Example Sequence of five MIPS instructions: 38 19
20 39 Pipeline Hazards Situations where there are conflicts between two instructions in the pipeline are called hazards Three categories: Structural hazards Data hazards Control hazards 40 20
21 Structural Hazards A structural hazard occurs when the datapath does not contain the necessary resources to perform two operations at the same time Solution: add resources to the datapath (perhaps by replicating existing resources) 41 Structural Hazards Example: separate instruction cache and data cache If single cache, could not simultaneously fetch an instruction and perform the MEM stage of LW or SW instructions Example: separate adder for PC Without a separate adder, PC+4 would have to be done in the ALU; could not simultaneously update PC and perform the EX stage 42 21
22 Data Hazards A data hazard occurs when the result of one instruction is an input to the next instruction Solution: freeze early stages of the pipeline (stall the pipeline) Solution in some cases: use data forwarding 43 Example: Data Hazard Second instruction dependent on first: add $s0, $t0, $t1 sub $t2, $s0, $t3 Old value of $s
23 Delay for two clock ticks: add $s0, $t0, $t1 nop nop sub $t2, $s0, $t3 45 Pipeline Bubbles Cause needed delays by inserting bubbles into the pipeline (cycles when no useful work is done in some stage) Several strategies for inserting bubbles Programmer required to insert no-ops Assembler inserts no-ops Hardware freezes early stages and converts "nullified" instructions into no-ops 46 23
24 Hardware inserts two bubbles: add $s0, $t0, $t1 sub $t2, $s0, $t3 47 Forwarding (Bypassing) Required value is sometimes available earlier in the pipeline Add pathways to forward the value 48 24
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