7.1. Unit 7. Fundamental Digital Building Blocks: Decoders & Multiplexers

Transcription

1 7. Unit 7 Fundamental Digital Building Blocks: Decoders & Multiplexers

2 CHECKER / DECODER 7.2

3 7.3 Gates Gates can have more than 2 inputs but the functions stay the same AND = output = if ALL inputs are Outputs for only input combination OR = output = if AN input is Outputs for only input combination X Z F X Z F x y z F x y z F 3-input AND 3-input OR

4 7.4 Checkers / Decoders An AND gate only outputs for combination That combination can be changed by adding inverters to the inputs We can think of the AND gate as checking or decoding a specific combination and outputting a when it matches. X Z F X Z F x y z F x y z F AND gate decoding (checking for) combination AND gate decoding (checking for) combination

5 7.5 Checkers / Decoders Place inverters at the input of the AND gates such that F produces only for input combination {x,y,z} = {} G produces only for input combination {x,y,z} = {} X Z F X Z G x y z F x y z G AND gate decoding (checking for) combination AND gate decoding (checking for) combination

6 7.6 Checkers / Decoders An OR gate only outputs for combination That combination can be changed by adding inverters to the inputs We can think of the OR gate as checking or decoding a specific combination and outputting a when it matches. x y z OR gate decoding (checking for) combination F X Z F x y z OR gate decoding (checking for) combination F X Z F

7 7.7 Decoder Exercise Compilers translate software to instructions that tell the processor to ADD, LOAD from Memory, tore to Memory, etc. These instructions are binary codes The processor must decode the instruction Create an AND gate decoder for each instruction type in the table that will produce '' when that instruction is about to be executed Instruction Type 6-bit OPCODE OP[5:] ADD LOAD TORE BRANCH ADD LOAD TORE

8 7.8 Full Decoders A full decoder is a building block that: Takes in an n-bit binary number as input Decodes that binary number and activates the corresponding output Individual outputs for ALL 2 n input combinations 3-to-8 Decoder There are gates inside to implement each output D D 3-bit binary number Z (LB) X (MB) D2 D3 D4 D5 output for each combination of the input number D6 D7

9 7.9 Decoders A decoder is a building block that: Takes a binary number as input Decodes that binary number and activates the corresponding output Put in 6=, Output 6 activates ( ) Put in 5=, Output 5 activates ( ) Binary #6 Z (LB) X (MB) D D D2 D3 D4 D5 D6 D7 Only that numbered output is activated

10 7. Decoders A decoder is a building block that: Takes a binary number as input Decodes that binary number and activates the corresponding output Put in 6=, Output 6 activates ( ) Put in 5=, Output 5 activates ( ) Binary #5 Z (LB) X (MB) D D D2 D3 D4 D5 D6 D7 Only that numbered output is activated

11 7. Decoder izes A decoder w/ an n-bit input has 2 n outputs output for every combination of the n-bit input D D D2 X (MB) D3 n inputs (2) 2-to-4 Decoder 2 n outputs (4) n inputs (3) A A A2 (MB) to-8 Decoder 2 n outputs (8)

12 7.2 Exercise Complete the design of a 2-to-4 decoder X (MB) D D D2 D3 D y D x D2 D3

13 7.3 Building Decoders 3-bit number [A2:A] Checker for Checker for Checker for Checker for Checker for Checker for O O O2 O3 O4 O5 A A A2 O O O2 O3 O4 O5 Checker for O6 O6 Checker for O7 O7

14 7.4 Vending Machine Example Assuming the keypad produces a 4-bit numeric output, add logic to produce the release signals for each of the 6 vending items A[3:] 4-to-6 decoder Consider any problems with this design.

15 7.5 Enables In a normal decoder exactly one output is active at all times It may be undesirable to always have an active output We can add an extra input (called an enable) that can independently force all the outputs to their inactive values X D D D2 D3 One output will always be active X E D D D2 D3 2-to-4 Decoder Enable Will force all outputs to when E = (i.e. not enabled)

16 7.6 Enables When E=, inputs is ignored X Enable E D D D2 D3 ince E=, all outputs = When E=, inputs will cause the appropriate output to go active X Enable E D D D2 D3 ince E=, outputs will function normally

17 7.7 Enables Enables can be implemented by connecting it to each AND gate of the decoder A A B B A D D B D2 D3 E When E=, AND anything = When E=, AND anything = that anything, which was the normal decoding logic

18 7.8 Multiplexers Multiplexers are one of the most common digital circuits Anatomy: n data inputs, log 2 n select bits, output A multiplexer ( mux for short) selects one data input and passes it to the output 4-to- Mux i n data inputs i i2 y output i3 s log 2 n select bits

19 7.9 Multiplexers 4-to- Mux 2 Thus, input 2 = C is selected and passed to the output A B C D i i i2 i3 s y C elect bits = 2 = 2.

20 7.2 Multiplexers 4-to- Mux, 32-bit wide mux 2 Thus, input = A is selected and passed to the output A B C D i i i2 i3 s y A elect bits = 2 =.

21 7.2 Multiplexers 2-to- Mux, 32-bit wide mux A i 2 Thus, input = B is selected and passed to the output B i s y B elect bits = 2 =.

22 OEL OEL OEL2 OEL Recall Using T/T2 st Level of AND gates act as barriers only passing channel OR gates combines 3 streams of s with the channel that got passed (i.e. ICH) 2 nd Level of AND gates passes the channel to only the selected output Essentially this logic forms a 4-to- mux where one level of gates blocks all but and then the OR gate combines all signals ICH ICH ICH Connection Point ICH ICH ICH OCH OCH ICH 2 ICH OCH 2 ICH 3 ICH ICH OCH 3 AND: AND ICHx = ICHx AND ICHx = IEL IEL IEL2 IEL3 OR: + ICH + + = ICH AND: AND ICH = ICH AND ICH =

23 7.23 Exercise: Build a 4-to- mux Complete the 4-to- mux to the right by drawing wires between the 2-to-4 decode and the AND gates I I I 2 I 3 = = AND Gates acting as barrier gates = = Final OR gate takes 3 zero s and one selected input 2-to-4 Decoder

24 7.24 Building a Mux To build a mux Decode the select bits and include the corresponding data input. Finally OR all the first level outputs together. I = 2 I I 2 I I I I 3

25 7.25 Building a Mux To build a mux Decode the select bits and include the corresponding data input. Finally OR all the first level outputs together. I = 2 I I 2 I 3 I 3 I 3 I 3

26 7.26 Building a Mux To build a mux Decode the select bits and include the corresponding data input. Finally OR all the first level outputs together. I I

27 7.27 Building Wide Muxes o far muxes only have single bit inputs I is only -bit I is only -bit What if we still want to select between 2 inputs but now each input is a 4- bit number Pass all 4 bits Use a 4-bit wide 2-to- mux B I A B A I I I -bit wide 2-to- mux When we select I of I or I or I we want all 4-bits of that input to be passed A B 4-bit wide 2-to- mux

28 7.28 Building Wide Muxes Use one mux per "lane" (bit) To build a 4-bit wide 2-to- mux, use 4 separate 2-to- muxes Operation: When =, all muxes pass their I inputs which means all the A bits get through When =, all muxes pass their I inputs which means all the B bits get through In general, to build an m-bit wide (i.e. m-lane) n-to- mux, use m individual n-to- muxes A A A2 A3 B B B2 B3 A B A B A2 B2 A3 I I I I I I I 2 3 B3 I

29 7.29 Multiplexers 4-to- Mux, 32-bit wide mux 2 Thus, input = A[3:] is selected and passed to the output A[3:] B[3:] C[3:] D[3:] i i i2 i3 s y A[3:] elect bits = 2 =.

30 7.3 Multiplexers 2-to- Mux, 32-bit wide mux A[3:] i 2 Thus, input = B[3:] is selected and passed to the output B[3:] i s y B[3:] elect bits = 2 =.

31 7.3 Exercise How many -bit wide muxes and of what size would you need to build a 4-to-, 8-bit wide mux (i.e. there are 4 numbers: W[7:], X[7:], [7:] and Z[7:] and you must select one) How many -bit wide muxes and of what size would you need to build a 8-to-, 2-bit wide mux?

32 7.32 Building Large Muxes imilar to a tournament of sports teams Many teams enter and then are narrowed down to winner In each round winners play winners tage 3 Final output tage 2 tage

33 Design an 8-to- mux with 2-to Muxes I I I I I I2 I3 I I I I I4 I I5 I I 2 I I6 I7 I I I 2

34 7.34 Cascading Muxes Use several small muxes to build large ones Rules. Arrange the muxes in stages (based on necessary number of inputs in st stage) 2. Outputs of one stage feed to inputs of the next until only final output 3. All muxes in a stage connect to the same group of select bits Usually, LB connects to first stage MB connect to last stage

35 7.35 Building a 4-to- Mux tage tage 2 D I Rule : Outputs from stage connect to inputs of stage 2 D I I I D 2 I D 3 I 4-to- mux built w/ 2-to- muxes Rule 2: LB connect to all muxes in first stage. MB connects to all muxes in second stage

36 7.36 Building a 4-to- Mux tage tage 2 D I D D D I I D 2 D 3 D 2 I I Walk through an example: D 3 I =

37 7.37 Building a 4-to- Mux tage tage 2 D I D D D 2 D I D I D 3 D 2 I D 3 I Walk through an example: = D 3 I = narrows our choices down to D and D 3

38 7.38 Building a 4-to- Mux tage tage 2 D I D D D I D I D 2 D D 3 D 2 I D 3 I Walk through an example: = D 3 I = selects our final choice, D

39 7.39 Exercise Create a 3-to- mux using 2-to- muxes Inputs: I, I, I2 and select bits, Output: I I D D I I D 2 I2 I I