Lecture 4: Introduction to Pipelining

Transcription

1 Lecture 4: Introduction to Pipelining

2 Pipelining Laundry Example Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes A B C D Dryer takes 40 minutes Folder takes 20 minutes

3 Sequential Laundry 6 PM Midnight Time T a s k O r d e r A B C D Sequential laundry takes 6 hours for 4 loads

4 Pipelined Laundry Start work ASAP 6 PM Midnight Time T a s k O r d e r A B C D Pipelined laundry takes 3.5 hours for 4 loads

5 T a s k O r d e r A B C D Pipelining: Observations 6 PM Time Pipelining doesn t help latency of single task, it helps throughput of entire workload Pipeline rate limited by slowest pipeline stage Multiple tasks operating simultaneously Potential speedup = Number pipe stages Unbalanced lengths of pipe stages reduces speedup Time to fill pipeline and time to drain it reduces speedup

6 5 Steps of DLX Datapath Figure 3.1 Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back + NPC Zero? Cond. M U X PC 4 Inst. Mem. IR Regs A B M U X M U X ALU ALU Output Data Mem. LMD M U X Sign Imm. 16 Ext. 32

7 Pipelined DLX Datapath Figure 3.4 Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc. M U X PC 4 + Inst. Mem. Regs M U X M U X Zero? ALU Memory Access Data Mem. Write Back M U X Sign Ext. IF/ID ID/EX EX/MEM MEM/WB

8 Visualizing Pipelining Figure 3.3 Time (clock cycles) I n s t r. O r d e r

9 Limits to Pipelining Hazards prevent next instruction from executing during its designated clock cycle Structural hazards: HW cannot support this combination of instructions Data hazards: Instruction depends on result of prior instruction still in the pipeline Control hazards: Pipelining of branches & other instructions that change the PC Common solution is to stall the pipeline until the hazard is resolved, inserting one or more bubbles in the pipeline

10 One Memory Port/Structural Hazards Figure 3.6 Time (clock cycles) I n s t r. O r d e r Load Instr 1 Instr 2 Instr 3 Instr 4

11 One Memory Port/Structural Hazards Figure 3.7 I n s t r. O r d e r Load Instr 1 Instr 2 stall Instr 3

12 Speed Up Equation for Pipelining Speedup from pipelining = Ave Instr Time unpipelined Ave Instr Time pipelined = CPI unpipelined x Clock Cycle unpipelined CPI pipelined x Clock Cycle pipelined = CPI unpipelined Clock Cycle x unpipelined CPI pipelined Clock Cycle pipelined Ideal CPI = CPI unpipelined /Pipeline depth Speedup = Ideal CPI x Pipeline depth Clock Cycle x unpipelined CPI pipelined Clock Cycle pipelined

13 Speed Up Equation for Pipelining CPI pipelined = Ideal CPI + Pipeline stall clock cycles per instr Speedup = Ideal CPI x Pipeline depth Clock Cycle x unpipelined Ideal CPI + Pipeline stall CPI Clock Cycle pipelined Speedup = Pipeline depth Clock Cycle x unpipelined 1 + Pipeline stall CPI Clock Cycle pipelined

14 Example: Dual-port vs. Single-port Machine A: Dual ported memory Machine B: Single ported memory, but its pipelined implementation has a 1.05 times faster clock rate Ideal CPI = 1 for both Loads are 40% of instructions executed SpeedUp A = Pipeline Depth/(1 + 0) x (clock unpipe /clock pipe ) = Pipeline Depth SpeedUp B = Pipeline Depth/( x 1) x (clock unpipe /(clock unpipe / 1.05) = (Pipeline Depth/1.4) x 1.05 = 0.75 x Pipeline Depth SpeedUp A / SpeedUp B = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33 Machine A is 1.33 times faster

15 Data Hazard on R1 Figure 3.9

16 Three Generic Data Hazards Instr I followed by Instr J Read After Write (RAW) Instr J tries to read operand before Instr I writes it

17 Three Generic Data Hazards Instr I followed by Instr J Write After Read (WAR) Instr J tries to write operand before Instr I reads it Can t happen in DLX 5 stage pipeline because: All instructions take 5 stages, Reads are always in stage 2, and Writes are always in stage 5

18 Three Generic Data Hazards Instr I followed by Instr J Write After Write (WAW) Instr J tries to write operand before Instr I writes it Leaves wrong result ( Instr I not Instr J ) Can t happen in DLX 5 stage pipeline because: All instructions take 5 stages, and Writes are always in stage 5 Will see WAR and WAW in later more complicated pipes

19 Forwarding to Avoid Data Hazard Figure 3.10

20 HW Change for Forwarding Figure 3.20

21 Data Hazard Even with Forwarding Figure 3.12

22 Data Hazard Even with Forwarding Figure 3.13

23 Software Scheduling to Avoid Load Hazards Try producing fast code for a = b + c; d = e f; assuming a, b, c, d,e, and f in memory. Slow code: LW LW ADD SW LW LW SUB SW Rb,b Rc,c Ra,Rb,Rc a,ra Re,e Rf,f Rd,Re,Rf d,rd Fast code: LW LW LW ADD LW SW SUB SW Rb,b Rc,c Re,e Ra,Rb,Rc Rf,f a,ra Rd,Re,Rf d,rd

24 Compiler Avoiding Load Stalls scheduled unscheduled gcc spice tex 14% 25% 31% 42% 54% 65% 0% 20% 40% 60% 80% % loads stalling pipeline

25 Pipelining Summary Just overlap tasks, and easy if tasks are independent Speed Up vs Pipeline Depth; if ideal CPI is 1, then: Speedup = Pipeline Depth 1 + Pipeline stall CPI X Clock Cycle Unpipelined Clock Cycle Pipelined Hazards limit performance on computers: Structural: need more HW resources Data: need forwarding, compiler scheduling Control: discuss next time