Switching Circuits & Logic Design

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Ralph Gerald Russell
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1 Switching Circuits & Logic Design JieHong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University all 22 4 Derivation of Graphs and Tables Network motifs in developmental transcription networks Uri Alon Nature Reviews Genetics, June 27 2

2 Outline Design of a sequence detector More complex design problems Guidelines for construction of state graphs Serial data code conversion Alphanumeric state graph notation Conversion between Mealy and Moore Graphs 3 Design of a Sequence Detector Sequential Parity Checker (recap) A parity checker for serial data = the total number of inputs received is odd (i.e., input parity is odd) = initially (data input) Block diagram Parity Checker = Q 4

3 Design of a Sequence Detector Sequential Parity Checker (recap) graph = = S = S = = table even = odd S S Next = = S S S S state encoding/assignment Output Logic circuit T Q Q Q + = = T = = CK Q' 5 Design of a Sequence Detector {}Sequence Detector Block diagram (data input) Sequence Detector = input sequence is received Input/output sequence example = = Time:

4 Design of a Sequence Detector {}Sequence Detector Mealy machine diagram table A + B + Next Output AB = = = = = = = = S S S S S S S S S S S : initial state S : sequence ending with received : sequence ending with received S S S 7 Design of a Sequence Detector {}Sequence Detector Mealy machine Nextstate maps Circuit realization A' A CK D AB AB AB x x x x x x A + ='B B + = =A Assume A,B can be reset to B' B (Need to be careful about the don t care assignment if the CK D s do not have reset when powered up) 8

5 Design of a Sequence Detector {}Sequence Detector Moore machine diagram S S S S S S table S S Next = S S = S S S Output AB = A + B + = 9 More Complex Design Problems {,}Sequence Detector Block diagram (data input) Sequence Detector = input sequence or is received Input/output sequence example = = Time:

6 More Complex Design Problems {,}Sequence Detector Mealy machine implementation () Partial graph for S S S a 3 S S Sequence received reset (2) Partial graph for (3) Complete state graph S S? S e d b c S S Sequence ends in reset (but not ) (but not ) i f S S g 4 c e d h More Complex Design Problems {,}Sequence Detector Exercise Moore machine implementation 2

7 More Complex Design Problems Modified Parity Sequence Detector Block diagram (data input) Sequence Detector = the total number of s received is odd and at least two consecutive s have been received Input/output sequence example = odd odd odd odd odd odd = () 3 More Complex Design Problems Modified Parity Sequence Detector Moore machine implementation () Partial graph S (2) Partial graph S S S (3) Complete state graph S S Sequence received S reset on even s odd s even s and ends in even s and occurred odd s and occurred odd s and ends in S Even s Odd s 4

8 More Complex Design Problems Modified Parity Sequence Detector Exercise Mealy machine implementation 5 Construction of Graphs Guidelines. Construct sample input/output sequences 2. Determine under what conditions, if any, the circuit should reset to its initial state 3. If only one or two sequences lead to a nonzero output, construct a partial state graph for those sequences 4. Alternatively, determine what sequences or groups of sequences must be remembered by the circuit and set up states accordingly 5. Each time an arrow is added, determine whether it can go to one of the previously defined states or whether a new state must be added 6. Check there is only one outgoing edge leaving each state for each input value 7. Test the completed graph and make sure correct 6

9 Construction of Graphs Example Block diagram (data input) Sequence Detector = input sequence or occurs The circuit examines groups of 4 consecutive inputs, and resets after every 4 inputs Input/output sequence example = = 7 Construction of Graphs Example Mealy machine implementation () Partial graph (2) Complete state graph S S Sequence received S 6 S S reset or or S 6 Sequence received two inputs received, no output is possible three inputs received, no output is possible 8

10 Construction of Graphs Example 2 (omitted) Block diagram (data input) Sequence Detector 2 = : every time sequence is completed and has never occurred 2 = : every time sequence is completed Input/output sequence example = = 2 = 9 Construction of Graphs Example 2 (omitted) Mealy machine implementation () Partial graph (2) Complete state graph S S Description S S No progress on Progress of on Progress of on No progress on Progress of on No progress on No progress on Progress of on Progress of on Progress of on has never occurred partial graph for S 6 S 7 Progress of on Progress of on No progress on has occurred 2

11 Construction of Graphs Example 2 (omitted) table S S S 6 S 7 Next state Output 2 = = = = S S S S 6 S 7 S 7 2 Construction of Graphs Example 3 (omitted) Block diagram 2 Sequence Detector remains a constant value unless one of the following input sequences occurs (a) Input sequence 2 =, causes = (b) Input sequence 2 =, causes = (c) Input sequence 2 =, causes to change value ( 2 =, means =, 2 = followed by =, 2 = ) 22

12 Construction of Graphs Example 3 (omitted) Moore machine implementation Observation: Only the previous and present inputs (input sequence of length 2) will determine the output Unnecessary to use a separate state for and because neither input starts a sequence which leads to an output change designation Previous Input ( 2 ) Output () Designation or or S S 23 Construction of Graphs Example 3 (omitted) table 2 = Next S S S S S S S S S S S S S S graph 24

13 Serial Data Code Conversion Transmission of serial bit streams Two common approaches. signal transmitted along with the data Serial Data Transmitter Receiver 2. recovery circuit used Serial Data Transmitter Recovery Circuit Receiver 25 Serial Data Code Conversion our typical coding schemes NR (nonreturntozero) code NRI (nonreturntozeroinverted) code R (returntozero) code Manchester code Easy to recover the clock signal Example Bit Sequence NR NRI R Manchester bit time 26

14 Serial Data Code Conversion NRCode to ManchesterCode Mealy machine implementation Use 2, twice the frequency of the basic clock If the NR bit is (), it will be () for two 2 periods NR data 2 Converter Manchester data S NR() Manchester (ideal) S 2 S S S S S S S S S S S S Next = = = Output = (actual) clock period glitch (false output) S S S S S 27 Serial Data Code Conversion NRCode to ManchesterCode Moore machine implementation S S (NR) 2 S S S S S S S S S Next = = Output clock period S S S S S Output delayed by one clock period 28

15 Alphanumeric Graph Notation graphs with variable names on arc labels (and in states for Moore machine) Example R Sequential Circuit Incompletely specified state graph 3 R S R R S Completely specified state graph 'R' 3 S 'R 'R S 2 'R' 'R 'R' 29 Alphanumeric Graph Notation graph 'R' table S PS R= NS Output 'R 'R S 2 'R' 'R 'R' S S S S S S S S S S Check input signals (for every state): + 'R + 'R' = + ' = Transition defined for every input combination 'R =, 'R' =, 'R 'R' = At most one next state for every input combination 3

16 Alphanumeric Graph Notation A completely specified state graph has the following properties. ORing together all input labels on arcs outgoing from a state reduces to (i.e., complete transition) or every input combination, at least one next state is defined 2. ANDing together any pair of input labels on arcs outgoing from a state reduces to (i.e., deterministic transition) or every input combination, no more than one next state is defined If both properties are true, then exactly one next state is defined 3 Alphanumeric Graph Notation Convention for Mealy machine The label i j / p q on an arc means if i and j are (we don t care what the other input values are), the outputs p and q are (and the other outputs are ) E.g., for a circuit with 4 inputs (, 2, 3, 4 ) and 4 outputs (, 2, 3, 4 ) 4 '/ 2 3 is equivalent to / 32

17 Conversion between Mealy and Moore Graphs Convert Mealy to Moore. Push the output label on an edge to its next state (so delay introduced!) 2. If a state receives different output labels, duplicate the state such that every copy has exactly one output label 3. Connect every edge properly to the state with correct output label Convert Moore to Mealy. Distribute the output label of a state to its incoming edges 2. Simplify the state graph by merging equivalent states Mealytype implementation of a circuit can have fewer states than Mooretype implementation 33 Conversion between Mealy and Moore Graphs Exercise S S S S 34

DIGITAL DESIGN WITH SM CHARTS

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