CHAPTER 5 NOVEL CARRIER FUNCTION FOR FUNDAMENTAL FORTIFICATION IN VSI

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1 98 CHAPTER 5 NOVEL CARRIER FUNCTION FOR FUNDAMENTAL FORTIFICATION IN VSI 5.1 INTRODUCTION This chapter deals with the design and development of FPGA based PWM generation with the focus on to improve the fundamental output of the single phase VSI. This PWM generation is based on Amplitude Modulated Inverted Sine Carrier (AMISC) enhancement with a sinusoidal reference signal. It has a better spectral quality and a higher fundamental component compared to the conventional SPWM method without any pulse falling or rising. It also enhances the fundamental output voltage at low modulation index ranges and also maintaining a low THD without any device switching losses. 5.2 PROPOSED NOVEL PWM STRATEGY The generation of PWM patterns through modulation involves amplitude to width transformation. That is, the suitable carrier-based PWM method programs, a per carrier cycle average output voltage equal to the reference voltage. In the traditional unipolar sinusoidal PWM (SPWM), a triangular carrier and a sinusoidal reference are compared for generating the gating pulses. In the SPWM switching strategies, fundamental enhancement demands an increase in pulse width in the regions around the center of the

2 99 reference wave. The reference output voltage relationship is linear until the reference voltage magnitude exceeds the modulator linearity limit and the condition is called over-modulation. There is no simple PWM algorithm which maintains voltage gain linearity until the full utilization of dc input for single-phase inverter system. The transition from PWM to square wave mode operation was an unresolved problem limiting the performance of AC drive systems. Modified regular sampled SPWM scheme named amplitude modulated inverted sine carrier PWM (AISCPWM) has been proposed to give single mode operation of SPWM inverter. It offers linear gain characteristics in comparison to the conventional SPWM without involving complex computations and significant device losses Amplitude Modulated Inverted Sine Carrier PWM Method This makes use of a novel Amplitude Modulated Inverted Sine Carrier (AMISC) function which has the conventional sine wave as a reference signal whereas the carrier is amplitude modulated inverted sine signal as shown in Figure 5.1. The carrier is a high frequency inverted sine, which is (amplitude) modulated by a sinusoidal modulating signal of reference frequency.

3 100 Figure 5.1 Concept of AMISC Function Modified regular sampled SPWM scheme named Amplitude Modulated Inverted Sine Carrier (AMISC) PWM has been developed to give single mode operation of SPWM inverter. This PWM scheme combines the advantages both ISCPWM and AMTCPWM which are presented in the previous chapters. Figure 5.2 illustrates the unipolar pulse pattern of AMISCPWM technique. The intersections between the high frequency amplitude modulated inverted sine carrier and the sinusoidal reference waveform breeds the positive and negative group switching pulses for the single phase inverter. The modulation index (M a ) and frequency ratio (M f ) decides the switching angle location and duty cycle. Figure 5.2 AMISC-PWM Pulse Pattern

4 Performance Analysis The performance analysis of AMISC-PWM technique has been done with the help of Matlab 7.9. The output waveform and harmonic spectrum for the specifications of M a =0.8, M f =15, V dc =300V and R load =100 are shown in Figure 5.3. Performance comparison of AMISC-PWM with SPWM and AMTC-PWM are illustrated in Figure 5.4 and Figure 5.5 respectively. The AMTCPWM achieves fundamental output voltage values with maximum utilization of dc supply and reaches the square wave inverter boundary linearly. AMISCPWM enhances the fundamental while the THD is comparable with AMTCPWM. However, it results in marginal decrease in the linear region. Figure 5.3 Output Voltage and Frequency spectrum

5 PROPOSED DIGITAL IMPLEMENTATION AMISC-PWM METHOD A digital architecture has been developed to implement the AMISC-PWM technique as shown in Figure The architecture consists of Sine Data Manipulation (SDM) Unit, Reference Wave Scaling (RWS) Unit, Amplitude Modulated Sine Inverted Carrier Generation (AMSICG) Unit and Comparing and Pulse Separation (CPS) Unit. In this novel architecture, the modules are performing parallel. The Functionality of the units like SDM, RWS and CPS are similar to the ISC-PWM architecture and it has been discussed detail in the previous chapter. The Amplitude Modulated Inverted Sine Carrier generation Unit (AMISCGU) is designed using the VHDL as in appendix A2.3. This unit comprises the sine generation, sine inversion and peak correction. The function of this unit up to sine inversion is similar to the ISC-PWM method. The amplitude of inverted sine (carrier) can be modulated by limiting the peak of this wave by peak correction method as given in the algorithm.

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7 Algorithm for Amplitude Modulated Inverted Sine Carrier Generation step 1. step 2. step 3. step 4. step 5. step 6. step 7. step 8. step 9. step 10. step 11. step 12. step 13. Start Calculate one quarter cycle sine data, and store it in a Look up table. Fix the output ac voltage frequency of the inverter. Initialize the initial Address value=0 for Sine Look up table. Derive the fetching rate clock (10 KHz) from the board clock Fix the carrier frequency (3 KHz) and derive from board clock Fetch the sine data from memory and make sine envelope Renovate sine envelope into inverted sine carrier Fix the amplitude peak of the each carrier cycle from the 50 Hz sine reference wave Renovate inverted sine carrier into Amplitude Modulated Inverted Sine Carrier (AMISC) Get the sample from sine memory based on present address. Check whether carrier address reaches sampled sine data. If reaches, and decrement the addresses.

8 105 step 14. step 15. step 16. step 17. step 18. Check whether addresses reach base value of sine carrier wave. Compare the Amplitude modulated inverted sine carrier with presents sine reference. If sine reference is high then decrease the PWM pulse. If reaches the address value, increment the address for sine sample, and go to step 8. For 50th sample address decrement the sine sample address step 19. Then go to step SIMULATION AND SYNTHESIS The functional simulation of the designed AMISC-PWM architecture has been carried out using the Modelsim software. Using the Xilinx ISE tool, the functional verification of the design has been done Functional Simulation The gating pulses generated by the VHDL design for the positive and negative group switching devices of inverter have been analyzed in the Modelsim software. The gating pulses generated for the modulation indexes of 0.4 and 0.8 are shown in Figure 5.5 and Figure 5.6 respectively.

9 106 Figure 5.5 Modelsim output pulses for M a = 0.4 Figure 5.6 Modelsim output pulses for M a = 0.8

10 Synthesis The user-specified synthesis constraints like timing, power and area of the AMISC-PWM design have been verified using the Xilinx ISE software tool to optimize and implement the RTL design into equivalent unit-delay primitive blocks (flip-flops, logic gates, etc.). The RTL schematic view of the design and Logic implemented area has been verified virtually as shown in the Figures 5.7 and 5.8 respectively. Table 5.1 shows the details of unit level device utilization for the design. Figure 5.7 RTL Schematic View of AMISC-PWM Design

11 108 Figure 5.8 Logic implemented area for the AMISC-PWM Design Table 5.1 Unit level Device Utilization for the AMISC-PWM Design Module Name RAM (single-port distributed Read Only) 30x32 256x11 3 bit adder 32 bit adder Adders / Subtractors 12 bit subtractor 32 bit add-sub SDMU/ RWSU AMISCGU CPSU Miscellaneo us glue logic Over all Utilization Registers 1 bit Comparators (32 bit) 1-bit 2-to-1 11-bit 2-to Multiplexers 21-bit 2-to-1 32-bit 2-to-1 11x10 Multiplier 32x32 3 bit up counter Counter 32bit up counter 32 bit up-down counter

12 Power Analysis The power analysis for the designed architecture has been thoroughly done using the software tool, Xilinx power estimator. The estimated on-chip power for the design is W as show in Figure 5.9. The temperature dependency of on-chip power is also estimated as illustrated in Figure Figure 5.9 Power Estimation Summary of the Design Figure 5.10 Temperature Dependency of On-Chip Power

13 HARDWARE IMPLEMENTATION AND RESULTS The FPGA based AMISC-PWM architecture has been tested with a prototype of single phase Voltage Inverter as in appendix A3.2 and the output has been recorded and analyzed using Digital Storage Oscilloscope. The experimental setup for the hardware implementation is as shown in Figure The FPGA generated pulses are shown in shown in Figure The output voltage across the load and the frequency spectrum have been achieved for the modulation index (M a ) = 0.8 and frequency ratio (M f ) = 15 with an input voltage (V dc ) of 150V as shown in Figure 5.13 and Figure 5.14 respectively. Figure 5.11 Experimental Hardware setup

14 111 Figure 5.12 FPGA generated ISCPWM pulses Figure 5.13 Output voltage across the load

15 112 Figure 5.14 Frequency spectrum of AMISC-PWM The performance of the novel AMISC-PWM strategy has been compared with the conventional SPWM method and it results a better performance enhancements in terms of Fundamental and THD for different values of modulation indexes (M a ) as shown in Figure and 5.16 respectively. Figure 5.15 Variation of Fundamental with Modulation Index

16 113 Figure 5.16 Variation of THD with Modulation Index 5.6 PERFORMANCE COMPARISON BETWEEN AMTC-PWM, ISC-PWM AND AMISC-PWM METHODS The performance of the designed architecture for three different PWM strategies have been compared with each other and the better performance have been achieved for the novel PWM strategy of Amplitude Modulated Inverted Sine Carrier which is the conceptual combination of AMTCPWM and ISCPWM methods. The graphical illustration of comparison is as shown in 5.17 and Figure 5.18 respectively, meanwhile the numerical comparison is as shown in Table 5.2 and 5.3.

17 114 Figure 5.17 Comparison - Modulation index Vs Fundamental Voltage Figure 5.18 Comparison - Modulation index Vs Total Harmonic Distortion

18 115 Table 5.2 THD and Fundamental Comparison for Modulation Index 0.6 Method THD% Fundamental h3 h5 h7 h9 SPWM ISCPWM AMTCPWM AMISCPWM Table 5.3 THD and Fundamental Comparison for Modulation Index 1.0 Method THD% Fundamental h3 h5 h7 h9 SPWM ISCPWM AMTCPWM AMISCPWM SUMMARY The major expectation from any PWM strategy is the voltage linearity, harmonic distortion, and maximum obtainable output voltage. The proposed architecture of novel AMISCPWM has produced a high output voltage and low THD. The architecture developed for generating the novel carrier function provides a high degree of flexibility in the digital implementation. The FPGA based AMISCPWM architecture is capable of producing the pulses with high resolution and better reliability due to its parallel computational nature. This PWM strategy has exhibited a better hardware realization with a single phase VSI. The comparative analysis between the other modern PWM strategies showed that the proposed novel PWM strategy is suitable for the system which needs a high output voltage.