FPGA Laboratory Assignment 5. Due Date: 26/11/2012

Transcription

1 FPGA Laboratory Assignment 5 Due Date: 26/11/2012 Aim The purpose of this lab is to help you understand the fundamentals image processing. Objectives Learn how to implement image processing operations using HDL Integrate a VGA controller with a memory to display an image on screen Equipment Xilinx ISE 12.XX ISE Simulator (Isim) Spartan 3E Development Board 1

2 Introduction The programmable logic boards used for ECE 408 are Xilinx Spartan 3E-1600 development systems. The centerpiece of the board is a Spartan 3 XC3S1600E FPGA (field-programmable gate array), which can be programmed via a USB cable or compact flash card. The board also features PS/2, serial, Ethernet, stereo audio and video ports, user buttons, switches and LEDS, and expansion ports for connecting to other boards Figure 1. The Xilinx Spartan 3E-1600 Development System Caution! The boards contain many exposed components that are sensitive to static electricity. Before touching the boards, try to remember to discharge any static electricity you may have built up by touching a grounded piece of metal (i.e. part of the desk). Especially remember to do this after you have been walking around the room on a carpeted floor (please keep your shoes on). 2

3 Part 1: Integration In this part, you will use the memory controller from Lab 4 and the VGA controller together to output data from the memory to the VGA output. Start by generating a randomized 240x320 array of 3 bits per value. Each value represents a pixel, but in this part, we are not interested so much to the value, as getting our design to work. You can play with the Windows Color Scheme on any Microsoft Windows machine to perhaps get some ideas for interesting colors. Your array then needs to be stored in the memory (use the controller from Lab 4) and then can be displayed with your VGA controller in a loop mode (i.e. when the picture ends, you can loop back again to maintain a constant video output). The overall diagram of your system is shown below: The Windows color scheme (see below) can be used to give you suggested values for your testing. Implement the integrated design and using a start button (place it in one of your switches) and see the output on the VGA. You can start by placing a single color in the entire picture, then you can split the picture in two colors, three colors, and so on. 3

4 Part 2: Image Processing Application For the second part, you will put your integrated Memory-to-VGA controller to work, by performing some minor image manipulation. You will be given a 320x240 image in RGB (3 bits per pixel) format, which you will store in a BlockRAM memory using Xilinx Core Generator, or more preferably by instantiating them in you VHDL code. You will then proceed to read the image from the BlockRAM, and display it on a screen, in a 2x2 array. The 2x2 array will hold the original image and 3 copies of the image, each with one color component removed, as shown in the figure below: Demonstrate your project by displaying the four images in loop mode. 4

5 Extra Credit For extra credit, you can try to rotate the image 180 degrees, and display the original and the rotated (about the origin) versions of the image in white background. The rotation operator performs a geometric transform which maps the position (x 1, y 1 ) of a pixel in an input image onto a position (x 2, y 2 ) in an output image by rotating it through a user-specified angle θ about an origin O. In most implementations, output locations (x 2, y 2 ) which are outside the boundary of the image are ignored. Rotation is most commonly used to improve the visual appearance of an image, although it can be useful as a preprocessor in applications where directional operators are involved. The rotation operator performs a transformation of the form: where (x o, y o ) are the coordinates of the center of rotation (in the input image) and θ is the angle of rotation with clockwise rotations having positive angles. (Note here that we are working in image coordinates, so the y axis goes downward. Similar rotation formula can be defined for when the y axis goes upward.) Even more than the translate operator, the rotation operation produces output locations (x 2, y 2 ) which do not fit within the boundaries of the image (as defined by the dimensions of the original input image). In such cases, destination elements which have been mapped outside the image are ignored by most implementations. Pixel locations out of which an image has been rotated are usually filled in with black pixels. The rotation algorithm, unlike that employed by translation, can produce coordinates (x 2, y 2 ) which are not integers. In our case, feel free to round them to the nearest integer and overwrite any pixels that were produced before with the latest ones produced. 5

6 Turn-In Instructions Deliverables The ISE project folder containing the code and simulation files for all parts, and a lab report will be submitted electronically through (kyrkou.christos@ucy.ac.cy). The lab report should describe in detail your implementation stategy and design approaches for all parts in the lab. Please use compression software to (winrar or 7zip) to keep the file size at a minimum. If the files are too large to be submitted via please use the UCY file sending service Please notify me in advance if you are going to delay delivering the lab Also consider You are advised to look at the tutorials posted on the lab web site for a more comprehensive overview and detailed explanation of the tools. You are encourage to visit the Xilinx user community forums ( The community forum enables Xilinx FPGA users to share, discuss, and resolve issues related to the Xilinx tools, HDL, FPGA programming and more. GOOD LUCK 6

7 Appendix A Memory Implementation You can see the VHDL syntax for implementing memories and initializing them by clicking on the language templates button, go to VHDL Synthesis Constructs Coding Examples RAM or ROM. There many different implementation options available such as dual port or single port. You are to select the ones that better suits your design and implementation strategies. Your rational for implementing the memories should be detailed in the report. 7

8 Appendix B VGA Display Pin Locations Table I: 3-bit display colour codes Table II: UCF Constraints for VGA signals VGA_Red VGA_Green VGA_Blue VGA_hsync VGA_vsync H14 H15 G15 F15 F14 8

9 Appendix C LEDs and Switches Pin Locations Figure 2. Switches and LEDs on the Spartan3E-1600 development board Table III: UCF Constraints for LEDs and Swiches LEDS Switches Leds_0 Leds_1 Leds_2 Leds_3 Leds_4 Leds_5 Leds_6 Leds_7 SW_0 SW_1 SW_2 SW_3 D4 C3 D6 E6 D13 A7 G9 A8 L13 L14 H18 N17 9