The Application of System Generator in Digital Quadrature Direct Up-Conversion
|
|
- Horatio Lawrence
- 6 years ago
- Views:
Transcription
1 Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP The Application of System Generator in Digital Quadrature Direct Up-Conversion Zhi Chai 1, Jun Shen 2 etc Beijing Institute of Technology, Beijing, China 1 chaizhi113@12.com; 2 bitshen@bit.edu.cn Abstract-This paper presented a new method of digital quadrature up-conversion design based on field-programmable gate arrays (FPGA), which is the hardware design based on System Generator. First, the paper analysed the principle of digital quadrature up-conversion, applied System Generator for modeling, simulation and hardware implementation, then compared the advantages and disadvantages between the hardware design method based on System Generator and traditional RTL-level (register transfer level) design method based on HDL (hardware design language). Finally, the experiment results showed that the method has higher feasibility, more efficiency and full of resource utilization in practical applications, and it helped to shorten the system development cycle greatly. Keywords- Digital Quadrature Up-Conversion; FPGA; System Generator I. INTRODUCTION Currently, FPGA has become the main device in digital signal processing systems, especially in the field of digital communications, navigation, network, video and image applications. In addition, digital quadrature up-conversion is a widely used technology in digital signal processing, so the use of FPGA in the implementation of digital quadrature up-conversion and other digital signal processing techniques is gradually becoming the mainstream, such as the application in radar echo simulation. However, the traditional RTL-level FPGA hardware design mothed obviously cannot follow the short-term trend of system development cycle, meanwhile, there is also a gap between the pre-matlab-based algorithm verification and FPGA-based hardware implementation. More efficient methods are needed. Given the above considerations, this design comes up with a new approach based on System Generator. The FPGA in Virtex5 series from Xilinx Inc. is selected as the design object, using System Generator software for design and simulation, which is a product of cooperation between Xilinx Inc. and Mathwork Inc.. The application of this software makes it a perfect combination between IP cores provided by Xilinx and tools in Matlab Simulink, making the system-level simulation and verification easier. What s more, with its help, the design model can be directly compiled into netlist file which can be layouted in the FPGA device. As a result, a seamless connection between algorithm and hardware implementation can be built, the efficiency improved greatly and the development cycle shortened [1]. Starting from the digital quadrature up-conversion, this paper uses the method of System Generator-based digital quadrature direct up-conversion design to realize the migration from algorithms to FPGA hardware implementation seamlessly, and it illustrates the feasibility and benefits of the System Generator-based hardware design. II. THE PRINCIPLE OF DIGITAL QUADRATURE UP-CONVERSION DESIGN Digital quadrature modulation is a commonly used modulation technology, and I / Q modulation is the primary modulation method, I refers to the same phase, Q refers to quadrature. The nature of this technology is to multiply the baseband signal I / Q components by the orthogonal local oscillator signal, and then add them together to achieve the signal conversion. Formula is as follows: sin( t) cos( t) cos( t) sin( t) sin(( ) t) The diagram of I/Q modulation is shown in Figure 1 [2] Figure 1 The diagram of I/Q modulation What s more, any signal can be expressed in complex signal
2 Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP X () t x () t x () t r in which, xr () t is the real part of the signal, xq () t is the imaginary part of the signal. The quadrature up-conversion of the signal can also be explained in the following way [3]. j t e cos( t) j sin( t) j t that is, complex signal Xt () multiplied by the complex signal e. By taking out the real part, the signal spectrum has been moved, thus we achieve the conversion. We take off the real part of the complex signal to get real signal and symmetrical signal spectrum. The spectra shifting is shown in Figure 2. q Figure 2 Example of the spectra shifting III. SYSTEM GENERATOR-BASED SYSTEM MODELING AND IMPLEMENTATION A. Basic Knowledge on System Generator System Generator is a new FPGA design tool developed by Xilinx Inc. and Mathworks Inc. together. It serves as a bridge between high-level DSP system design and FPGA hardware implementations. Users only need to build the model in Simulink and launch System Generator, then the VHDL source codes and other project files can be generated automatically, and the system model is mapped to the target FPGA device. The typical design process of System Generator includes the following six steps [4]. 1) getting the mathematical description of the algorithm model; 2) building system model in Simulink; 3) the Simulink simulation, and the corresponding parameters adjustment; 4) starting System Generator, and generating the HDL codes and other documents automatically; 5) debugging the generated files, synthesis, translation, map, place&route and timing analysis in the ISE; ) downloading the program to the FPGA device for implementation, running and debugging the program. System Generator provides a module library, named Xilinx Blockset, which includes basic module, digital signal processing module (FIR and FFT), math module, memory module and interface module. And only by using modules in this library, projects can be automatically converted into HDL codes by System Generator. B. System Modeling Based on System Generator The design demonstrates the application of System Generator-based digital quadrature direct up-conversion mothed, selecting sin(5 10 t) and cos(5 10 t) as I / Q signals, and sin(10 t) and cos(10 t) as orthogonal LO signals. Frequencies of I / Q signals are 2.5 MHz, and frequencies of orthogonal LO signals are 5 MHz
3 Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP According to the formula: sin(5 10 t) cos(10 t) cos(5 10 t) sin(10 t) sin( t) we can get a signal as sin( t), frequency of 5 MHz, after the quadrature up-conversion. Then build the model of the system in the System Generator and simulate model, where there are two steps. 1) building the signal models of sin(5 10 t), cos(5 10 t) and cos(10 t) by using DDS technology. 2) combining the above four models together to build the whole system model. Step 1, the building of the four models is shown in Figure 3, which are cos(10 t). sin(5 10 t), cos(5 10 t), sin(10 t) and Figure 3 Model of cos(5 10 t) DDS technology is a new frequency synthesis method, it works as follows: driven by the reference clock, the phase accumulator accumulates frequency control word linearly as the phase code, addressing the waveform memory according to the phase code, then output the corresponding amplitude code, which changes into step wave through analog to digital converter, and finally after smoothed by a low-pass filter, the required frequency of the waveform comes into being. And its formula is as follows: f f K /2 N out clk in which, f out refers to output frequency, f clk refers to the system operating frequency, N is the number of phase accumulator bit, K is the frequency control word, and we can change the value of the output signal frequency by changing the frequency control word K [1]. Figure 3 above shows the model of to the formula: cos(5 10 t), using Convent module to generate a frequency control word, according f f K /2 N out clk 1 we choose the frequency control word K as , Z module is used for delaying one clock cycle data. AddSub module is for the continuous cumulative frequency control word. Convent module is for DDS cut-off position. ROM module is for waveform output, and its initial vector is set to sin( (0 : 4095) / 2048 / 2). OUT module is for the interface of Xilinx data field and Matlab data field. Out1 interface connects the current module to the upper-level model. SpectrumScope module is for the spectrum analyzer. Scope module is for scope [5]. Similarly, you can use the same approach to build the models sin(5 10 t), and cos(10 t), and the frequency control words of them are respectively , and , ROM sampling depth is 409, the beginning of start vectors are respectively sin( (0 : 4095) / 2048), sin( (0 : 4095) / 2048), sin( (0 : 4095) / 2048 / 2). Step 2, building the whole System Model. The whole System Model is shown in Figure
4 Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP Figure 4 Building the whole System Model In Figure 4, SystemGenerator module is the core module of System Generator, and Simulation module is to achieve the conversion of HDL code, the key parameters are set as: compilation for HDL Netlist file, part for Virtex5 xc5vsx95t-1ff113, synthesis tool for XST, hardware description language for VHDL, FPGA clock period for 20/3ns, simulink system period for 1/150e (sec), and so on. ResourceEstimator module is used to analysis the hardware resources needed. Four models, sin(5 10 t), cos(5 10 t), cos(10 t), are corresponding to the four models mentioned above in Figure 3, and they are all the upper-level models. The output is out1 module for every model. Mult1 module is for multiplication between cos(5 10 t) and sin(10 t). Mult2 module is for multiplication between sin(5 10 t) and cos(10 t). AddSub module is for addition between produces the signal sin( t) finally. sin(5 10 t) cos(10 t) and cos(5 10 t) sin(10 t). Then it IV. TESTING RESULTS A. Simulation Results The Simulink simulation parameter is set to 1024/5e, emulation mode is set to normal, then start the simulation. The spectrums of the four modules cos(5 10 t), sin(5 10 t), cos(10 t) are shown in Figure 5, and their frequencies are: 2.5 MHz, 5 MHz, 2.5 MHz, 5 MHz. Figure 5 The spectrum of the four modules The spectrum of the final signal sin( t) is shown in Figure. It shows that the frequency of the signal generated is.5 MHz, so the System Generator-based system model can meet the theoretical requirements [5]
5 Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP Figure The spectrum of the whole System Model B. Hardware Verification After simulation, we can verify the actual performance in FPGA device. Run SystemGenerator module generates standard files (Netlist), then imports the netlist into ISE12.2, compilation, synthesis, translation, map, place&route and timing analysis. When the high system frequency is needed, UCF file can be used for timing constraints, group constraints and other user constraints, and the process of place &route and constraints file modifition are repeated until it meets the requirements, then a downloadable file with configuration data is generated finally. Download it to the FPGA device, collect the final data by using the ChipScope, then analysis and validate the data. At last, we can get the answer that the actual results are consistent with the theoretical results [1]. C. Resource Usage Analysis Running ResourceEstimator module, we can get the information about the hardware resources needed by the system. The result is shown in Figure. It shows that the resource utilization is perfect for such a design. Figure Resource utilization V. COMPARISON WITH TRADITIONAL HDL HARDWARE DESIGN METHODS HDL hardware design, which is also called the traditional RTL-based design method, is divided into two parts: system-level and algorithm-level simulation and varification; hardware programming and implementation based on HDL programming language. The vast majority of algorithm design and system verification are completed in Matlab and Simulink, but this soft system level design environment cannot result in the final hardware implementation, furthermore, most developers based on algorithms are not familiar with the process of hardware programming, so a gap is formed between algorithm modeling and hardware programming implementation finally []. However, System Generator can convert the algorithm design and system simulation to the hardware programming language automatically and efficiently, which provides a good solution to the problem mentioned above. The solution based on System Generator, can greatly shorten the development cycle, improve the efficiency, and increase the rate of resources utilization, and it makes FPGA development much easier. It can also be used to design more complex systems conveniently by combining HDL hardware languages. Of course, it also has its own shortcomings. The multi-clock design and bi-directional bus are not supported here, but these shortcomings can be made up by using the skills of design based on HDL hardware programming language
6 Communications in Information Science and Management Engineering Apr. 2013, Vol. 3 Iss. 4, PP VI. CONCLUSION Through the experiment of digital quadrature up-conversion, this paper indicates that the System Generator-based design method can achieve the successful application in the digital quadrature up-conversion, the same to the field of digital signal processing. Compared with the traditional HDL hardware design method, as a new method, it highlights some advantages, such as strong operability, high development efficiency and resource utilization. What s more, this design provides a seamless top-down FPGA solution to the digital signal processing system designers. There is a reason to believe that, with the development of the technology, hardware design method based on System Generator will bring us higher performance. REFERENCES [1] Xu Wenbo, Tan Yin and Hu Bin. Xilinx ISE Design Suite 10.x FPGA design. POSTS TELECOM PRESS, first edition, [2] Optimization of quadrature modulator performance. RF Micro Devices, Inc., 199. [3] Kenneth W. Martin. Complex signal processing is not complex. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, pages , [4] Dai Qing and Feng Yongxin. The design and implementation of fir filter based on system generator. ELECTRONIC TECHNOLOGY, pages , 200. [5] Ji Zhicheng and Gao Chunneng. Digital signal processing design tutorial based on FPGA introduction and improvement of System Generator. Xi an Electronic and Science University Press, first edition, [] Zhu Jiang. FPGA system-level design in the field of DSP. Jovian Test Control Tech., pages 25 20,
CHAPTER 4 FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF FIVE LEVEL CASCADED MULTILEVEL INVERTER
87 CHAPTER 4 FIELD PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF FIVE LEVEL CASCADED MULTILEVEL INVERTER 4.1 INTRODUCTION The Field Programmable Gate Array (FPGA) is a high performance data processing general
More informationTHE DESIGN OF A PLC MODEM AND ITS IMPLEMENTATION USING FPGA CIRCUITS
Journal of ELECTRICAL ENGINEERING, VOL. 60, NO. 1, 2009, 43 47 THE DESIGN OF A PLC MODEM AND ITS IMPLEMENTATION USING FPGA CIRCUITS Rastislav Róka For the exploitation of PLC modems, it is necessary to
More informationBlock Diagram. i_in. q_in (optional) clk. 0 < seed < use both ports i_in and q_in
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core -bit signed input samples gain seed 32 dithering use_complex Accepts either complex (I/Q) or real input samples Programmable
More informationDesign and Implementation of Software Defined Radio Using Xilinx System Generator
International Journal of Scientific and Research Publications, Volume 2, Issue 12, December 2012 1 Design and Implementation of Software Defined Radio Using Xilinx System Generator Rini Supriya.L *, Mr.Senthil
More informationIJSRD - International Journal for Scientific Research & Development Vol. 5, Issue 06, 2017 ISSN (online):
IJSRD - International Journal for Scientific Research & Development Vol. 5, Issue 06, 2017 ISSN (online): 2321-0613 Realization of Variable Digital Filter for Software Defined Radio Channelizers Geeta
More informationVLSI Implementation of Digital Down Converter (DDC)
Volume-7, Issue-1, January-February 2017 International Journal of Engineering and Management Research Page Number: 218-222 VLSI Implementation of Digital Down Converter (DDC) Shaik Afrojanasima 1, K Vijaya
More informationImplementing DDC with the HERON-FPGA Family
HUNT ENGINEERING Chestnut Court, Burton Row, Brent Knoll, Somerset, TA9 4BP, UK Tel: (+44) (0)1278 760188, Fax: (+44) (0)1278 760199, Email: sales@hunteng.demon.co.uk URL: http://www.hunteng.co.uk Implementing
More informationSingle Chip FPGA Based Realization of Arbitrary Waveform Generator using Rademacher and Walsh Functions
IEEE ICET 26 2 nd International Conference on Emerging Technologies Peshawar, Pakistan 3-4 November 26 Single Chip FPGA Based Realization of Arbitrary Waveform Generator using Rademacher and Walsh Functions
More informationSIMULATION AND IMPLEMENTATION OF LOW POWER QPSK ON FPGA Tushar V. Kafare*1 *1( E&TC department, GHRCEM Pune, India.)
www.ardigitech.inissn 2320-883X, VOLUME 1 ISSUE 4, 01/10/2013 SIMULATION AND IMPLEMENTATION OF LOW POWER QPSK ON FPGA Tushar V. Kafare*1 *1( E&TC department, GHRCEM Pune, India.) tusharkafare31@gmail.com*1
More informationFPGA Based 70MHz Digital Receiver for RADAR Applications
Technology Volume 1, Issue 1, July-September, 2013, pp. 01-07, IASTER 2013 www.iaster.com, Online: 2347-6109, Print: 2348-0017 FPGA Based 70MHz Digital Receiver for RADAR Applications ABSTRACT Dr. M. Kamaraju
More informationAbstract of PhD Thesis
FACULTY OF ELECTRONICS, TELECOMMUNICATION AND INFORMATION TECHNOLOGY Irina DORNEAN, Eng. Abstract of PhD Thesis Contribution to the Design and Implementation of Adaptive Algorithms Using Multirate Signal
More informationVLSI IMPLEMENTATION OF MODIFIED DISTRIBUTED ARITHMETIC BASED LOW POWER AND HIGH PERFORMANCE DIGITAL FIR FILTER Dr. S.Satheeskumaran 1 K.
VLSI IMPLEMENTATION OF MODIFIED DISTRIBUTED ARITHMETIC BASED LOW POWER AND HIGH PERFORMANCE DIGITAL FIR FILTER Dr. S.Satheeskumaran 1 K. Sasikala 2 1 Professor, Department of Electronics and Communication
More informationPre-distortion. General Principles & Implementation in Xilinx FPGAs
Pre-distortion General Principles & Implementation in Xilinx FPGAs Issues in Transmitter Design 3G systems place much greater requirements on linearity and efficiency of RF transmission stage Linearity
More informationAudio Sample Rate Conversion in FPGAs
Audio Sample Rate Conversion in FPGAs An efficient implementation of audio algorithms in programmable logic. by Philipp Jacobsohn Field Applications Engineer Synplicity eutschland GmbH philipp@synplicity.com
More informationMethod We follow- How to Get Entry Pass in SEMICODUCTOR Industries for 2 nd year engineering students
Method We follow- How to Get Entry Pass in SEMICODUCTOR Industries for 2 nd year engineering students FIG-2 Winter/Summer Training Level 1 (Basic & Mandatory) & Level 1.1 continues. Winter/Summer Training
More informationEE25266 ASIC/FPGA Chip Design. Designing a FIR Filter, FPGA in the Loop, Ethernet
EE25266 ASIC/FPGA Chip Design Mahdi Shabany Electrical Engineering Department Sharif University of Technology Assignment #8 Designing a FIR Filter, FPGA in the Loop, Ethernet Introduction In this lab,
More informationPV SYSTEM BASED FPGA: ANALYSIS OF POWER CONSUMPTION IN XILINX XPOWER TOOL
1 PV SYSTEM BASED FPGA: ANALYSIS OF POWER CONSUMPTION IN XILINX XPOWER TOOL Pradeep Patel Instrumentation and Control Department Prof. Deepali Shah Instrumentation and Control Department L. D. College
More informationHardware/Software Co-Simulation of BPSK Modulator and Demodulator using Xilinx System Generator
www.semargroups.org, www.ijsetr.com ISSN 2319-8885 Vol.02,Issue.10, September-2013, Pages:984-988 Hardware/Software Co-Simulation of BPSK Modulator and Demodulator using Xilinx System Generator MISS ANGEL
More informationField Programmable Gate Array Implementation and Testing of a Minimum-phase Finite Impulse Response Filter
Field Programmable Gate Array Implementation and Testing of a Minimum-phase Finite Impulse Response Filter P. K. Gaikwad Department of Electronics Willingdon College, Sangli, India e-mail: pawangaikwad2003
More informationDDC_DEC. Digital Down Converter with configurable Decimation Filter Rev Block Diagram. Key Design Features. Applications. Generic Parameters
Key Design Features Block Diagram Synthesizable, technology independent VHDL Core 16-bit signed input/output samples 1 Digital oscillator with > 100 db SFDR Digital oscillator phase resolution of 2π/2
More informationDATA INTEGRATION MULTICARRIER REFLECTOMETRY SENSORS
Report for ECE 4910 Senior Project Design DATA INTEGRATION IN MULTICARRIER REFLECTOMETRY SENSORS Prepared by Afshin Edrissi Date: Apr 7, 2006 1-1 ABSTRACT Afshin Edrissi (Cynthia Furse), Department of
More informationImplementation of a Real-Time Rayleigh, Rician and AWGN Multipath Channel Emulator
Implementation of a Real-Time Rayleigh, Rician and AWGN Multipath Channel Emulator Peter John Green Advanced Communication Department Communication and Network Cluster Institute for Infocomm Research Singapore
More informationAutomated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems
Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems George J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, F. Foster Dai and Victor P. Nelson
More informationImage Enhancement using Hardware co-simulation for Biomedical Applications
Image Enhancement using Hardware co-simulation for Biomedical Applications Kalyani A. Dakre Dept. of Electronics and Telecommunications P.R. Pote (Patil) college of Engineering and, Management, Amravati,
More informationWideband Spectral Measurement Using Time-Gated Acquisition Implemented on a User-Programmable FPGA
Wideband Spectral Measurement Using Time-Gated Acquisition Implemented on a User-Programmable FPGA By Raajit Lall, Abhishek Rao, Sandeep Hari, and Vinay Kumar Spectral measurements for some of the Multiple
More informationDigital Systems Design
Digital Systems Design Digital Systems Design and Test Dr. D. J. Jackson Lecture 1-1 Introduction Traditional digital design Manual process of designing and capturing circuits Schematic entry System-level
More informationSpectral Monitoring/ SigInt
RF Test & Measurement Spectral Monitoring/ SigInt Radio Prototyping Horizontal Technologies LabVIEW RIO for RF (FPGA-based processing) PXI Platform (Chassis, controllers, baseband modules) RF hardware
More informationSpectraTronix C700. Modular Test & Development Platform. Ideal Solution for Cognitive Radio, DSP, Wireless Communications & Massive MIMO Applications
SpectraTronix C700 Modular Test & Development Platform Ideal Solution for Cognitive Radio, DSP, Wireless Communications & Massive MIMO Applications Design, Test, Verify & Prototype All with the same tool
More informationDesign and Implementation of High Speed Carry Select Adder
Design and Implementation of High Speed Carry Select Adder P.Prashanti Digital Systems Engineering (M.E) ECE Department University College of Engineering Osmania University, Hyderabad, Andhra Pradesh -500
More informationUltrasonic Signal Processing Platform for Nondestructive Evaluation
Ultrasonic Signal Processing Platform for Nondestructive Evaluation (USPPNDE) Senior Project Final Report Raymond Smith Advisors: Drs. Yufeng Lu and In Soo Ahn Department of Electrical and Computer Engineering
More informationStratix Filtering Reference Design
Stratix Filtering Reference Design December 2004, ver. 3.0 Application Note 245 Introduction The filtering reference designs provided in the DSP Development Kit, Stratix Edition, and in the DSP Development
More informationAn Optimized Direct Digital Frequency. Synthesizer (DDFS)
Contemporary Engineering Sciences, Vol. 7, 2014, no. 9, 427-433 HIKARI Ltd, www.m-hikari.com http://dx.doi.org/10.12988/ces.2014.4326 An Optimized Direct Digital Frequency Synthesizer (DDFS) B. Prakash
More informationRapid Design of FIR Filters in the SDR- 500 Software Defined Radio Evaluation System using the ASN Filter Designer
Rapid Design of FIR Filters in the SDR- 500 Software Defined Radio Evaluation System using the ASN Filter Designer Application note (ASN-AN026) October 2017 (Rev B) SYNOPSIS SDR (Software Defined Radio)
More informationBPSK System on Spartan 3E FPGA
INTERNATIONAL JOURNAL OF INNOVATIVE TECHNOLOGIES, VOL. 02, ISSUE 02, FEB 2014 ISSN 2321 8665 BPSK System on Spartan 3E FPGA MICHAL JON 1 M.S. California university, Email:santhoshini33@gmail.com. ABSTRACT-
More informationKeywords: CIC Filter, Field Programmable Gate Array (FPGA), Decimator, Interpolator, Modelsim and Chipscope.
www.semargroup.org, www.ijsetr.com ISSN 2319-8885 Vol.03,Issue.25 September-2014, Pages:5002-5008 VHDL Implementation of Optimized Cascaded Integrator Comb (CIC) Filters for Ultra High Speed Wideband Rate
More informationPartial Reconfigurable Implementation of IEEE802.11g OFDM
Indian Journal of Science and Technology, Vol 7(4S), 63 70, April 2014 ISSN (Print) : 0974-6846 ISSN (Online) : 0974-5645 Partial Reconfigurable Implementation of IEEE802.11g OFDM S. Sivanantham 1*, R.
More informationFPGA Implementation of Desensitized Half Band Filters
The International Journal Of Engineering And Science (IJES) Volume Issue 4 Pages - ISSN(e): 9 8 ISSN(p): 9 8 FPGA Implementation of Desensitized Half Band Filters, G P Kadam,, Mahesh Sasanur,, Department
More informationBPSK Modulation and Demodulation Scheme on Spartan-3 FPGA
BPSK Modulation and Demodulation Scheme on Spartan-3 FPGA Mr. Pratik A. Bhore 1, Miss. Mamta Sarde 2 pbhore3@gmail.com1, mmsarde@gmail.com2 Department of Electronics & Communication Engineering Abha Gaikwad-Patil
More informationEMBEDDED DOPPLER ULTRASOUND SIGNAL PROCESSING USING FIELD PROGRAMMABLE GATE ARRAYS
EMBEDDED DOPPLER ULTRASOUND SIGNAL PROCESSING USING FIELD PROGRAMMABLE GATE ARRAYS Diaa ElRahman Mahmoud, Abou-Bakr M. Youssef and Yasser M. Kadah Biomedical Engineering Department, Cairo University, Giza,
More informationHigh Speed & High Frequency based Digital Up/Down Converter for WCDMA System
High Speed & High Frequency based Digital Up/Down Converter for WCDMA System Arun Raj S.R Department of Electronics & Communication Engineering University B.D.T College of Engineering Davangere-Karnataka,
More informationHigh Speed and Dynamic Switching Type Signal Generation on FPGA for Emulating the Test Signals for Navigation Receivers
High Speed and Dynamic Switching Type Signal Generation on FPGA for Emulating the Test Signals for Navigation Receivers S. V. Devika *, Manohar **, N. Ravi ***, Y. Nagalakshmi ****, Sk. Khamuruddeen *****,
More informationRealization of 8x8 MIMO-OFDM design system using FPGA veritex 5
Realization of 8x8 MIMO-OFDM design system using FPGA veritex 5 Bharti Gondhalekar, Rajesh Bansode, Geeta Karande, Devashree Patil Abstract OFDM offers high spectral efficiency and resilience to multipath
More informationFINITE IMPULSE RESPONSE (FIR) FILTER
CHAPTER 3 FINITE IMPULSE RESPONSE (FIR) FILTER 3.1 Introduction Digital filtering is executed in two ways, utilizing either FIR (Finite Impulse Response) or IIR (Infinite Impulse Response) Filters (MathWorks
More informationSimulating and Testing of Signal Processing Methods for Frequency Stepped Chirp Radar
Test & Measurement Simulating and Testing of Signal Processing Methods for Frequency Stepped Chirp Radar Modern radar systems serve a broad range of commercial, civil, scientific and military applications.
More informationDesign & Implementation of an Adaptive Delta Sigma Modulator
Design & Implementation of an Adaptive Delta Sigma Modulator Shahrukh Athar MS CmpE 7 27-6-8 Project Supervisor: Dr Shahid Masud Presentation Outline Introduction Adaptive Modulator Design Simulation Implementation
More informationImplementation of Digital Modulation using FPGA with System Generator
Implementation of Digital Modulation using FPGA with System Generator 1 M.PAVANI, 2 S.B.DIVYA 1,2 Assistant Professor 1,2 Electronic and Communication Engineering 1,2 Samskruti College of Engineering and
More informationThe Design and Simulation of Embedded FIR Filter based on FPGA and DSP Builder
Research Journal of Applied Sciences, Engineering and Technology 6(19): 3489-3494, 2013 ISSN: 2040-7459; e-issn: 2040-7467 Maxwell Scientific Organization, 2013 Submitted: August 09, 2012 Accepted: September
More informationA Compiler Design Technique for EMS Test CS115
Send Orders for Reprints to reprints@benthamscience.ae The Open Automation and Control Systems Journal, 2014, 6, 1451-1455 1451 A Compiler Design Technique for EMS Test CS115 Open Access Wang-zhicheng
More informationAdvances in Wireless Communications: Standard Compliant Models and Software Defined Radio By Daniel Garcίa and Neil MacEwen
Advances in Wireless Communications: Standard Compliant Models and Software Defined Radio By Daniel Garcίa and Neil MacEwen 2014 The MathWorks, Inc. 1 Advances in Wireless Communications Standard compliant
More informationSoftware Design of Digital Receiver using FPGA
Software Design of Digital Receiver using FPGA G.C.Kudale 1, Dr.B.G.Patil 2, K. Aurobindo 3 1PG Student, Department of Electronics Engineering, Walchand College of Engineering, Sangli, Maharashtra, 2Associate
More informationCHAPTER 2 FIR ARCHITECTURE FOR THE FILTER BANK OF SPEECH PROCESSOR
22 CHAPTER 2 FIR ARCHITECTURE FOR THE FILTER BANK OF SPEECH PROCESSOR 2.1 INTRODUCTION A CI is a device that can provide a sense of sound to people who are deaf or profoundly hearing-impaired. Filters
More informationFPGA Implementation of Digital Modulation Techniques BPSK and QPSK using HDL Verilog
FPGA Implementation of Digital Techniques BPSK and QPSK using HDL Verilog Neeta Tanawade P. G. Department M.B.E.S. College of Engineering, Ambajogai, India Sagun Sudhansu P. G. Department M.B.E.S. College
More informationDigitalFrequencySynthesisusingMultiPhaseNCOforDielectricCharacterizationofMaterialsonXilinxZynqFPGA
Global Journal of Researches in Engineering: F Electrical and Electronics Engineering Volume 14 Issue 7 Version 1.0 Type: Double Blind Peer Reviewed International Research Journal Publisher: Global Journals
More informationDesign of Multiplier Less 32 Tap FIR Filter using VHDL
International OPEN ACCESS Journal Of Modern Engineering Research (IJMER) Design of Multiplier Less 32 Tap FIR Filter using VHDL Abul Fazal Reyas Sarwar 1, Saifur Rahman 2 1 (ECE, Integral University, India)
More informationDIRECT DIGITAL SYNTHESIS BASED CORDIC ALGORITHM: A NOVEL APPROACH TOWARDS DIGITAL MODULATIONS
DIRECT DIGITAL SYNTHESIS BASED CORDIC ALGORITHM: A NOVEL APPROACH TOWARDS DIGITAL MODULATIONS Prajakta J. Katkar 1, Yogesh S. Angal 2 1 PG student with Department of Electronics and telecommunication,
More informationHardware/Software Co-Simulation of BPSK Modulator Using Xilinx System Generator
IOSR Journal of Engineering (IOSRJEN) e-issn: 2250-3021, p-issn: 2278-8719, Volume 2, Issue 10 (October 2012), PP 54-58 Hardware/Software Co-Simulation of BPSK Modulator Using Xilinx System Generator Thotamsetty
More informationA GENERAL SYSTEM DESIGN & IMPLEMENTATION OF SOFTWARE DEFINED RADIO SYSTEM
A GENERAL SYSTEM DESIGN & IMPLEMENTATION OF SOFTWARE DEFINED RADIO SYSTEM 1 J. H.VARDE, 2 N.B.GOHIL, 3 J.H.SHAH 1 Electronics & Communication Department, Gujarat Technological University, Ahmadabad, India
More informationDigital Payload Modeling for Space Applications
Digital Payload Modeling for Space Applications Bradford S. Watson Staff Engineer Advanced Algorithm Development Group Copyright 28. Lockheed Martin Corporation. All rights reserved..ppt 5/9/28 1 Overview
More informationA Simulation of Wideband CDMA System on Digital Up/Down Converters
Scientific Journal Impact Factor (SJIF): 1.711 e-issn: 2349-9745 p-issn: 2393-8161 International Journal of Modern Trends in Engineering and Research www.ijmter.com A Simulation of Wideband CDMA System
More informationCHAPTER 5 NOVEL CARRIER FUNCTION FOR FUNDAMENTAL FORTIFICATION IN VSI
98 CHAPTER 5 NOVEL CARRIER FUNCTION FOR FUNDAMENTAL FORTIFICATION IN VSI 5.1 INTRODUCTION This chapter deals with the design and development of FPGA based PWM generation with the focus on to improve the
More informationRadar System Design and Interference Analysis Using Agilent SystemVue
Radar System Design and Interference Analysis Using Agilent SystemVue Introduction Application Note By David Leiss, Sr. Consultant EEsof EDA Anurag Bhargava, Application Engineer EEsof EDA Agilent Technologies
More informationFPGA DESIGN OF A HARDWARE EFFICIENT PIPELINED FFT PROCESSOR. A thesis submitted in partial fulfillment. of the requirements for the degree of
FPGA DESIGN OF A HARDWARE EFFICIENT PIPELINED FFT PROCESSOR A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Engineering By RYAN THOMAS BONE Bachelor
More informationFIR_NTAP_MUX. N-Channel Multiplexed FIR Filter Rev Key Design Features. Block Diagram. Applications. Pin-out Description. Generic Parameters
Key Design Features Block Diagram Synthesizable, technology independent VHDL Core N-channel FIR filter core implemented as a systolic array for speed and scalability Support for one or more independent
More informationFPGA Implementation of a Digital Tachometer with Input Filtering
FPGA Implementation of a Digital Tachometer with Input Filtering Daniel Mic, Stefan Oniga Electrical Department, North University of Baia Mare Dr. Victor Babeş Street 62 a, 430083 Baia Mare, Romania danmic@ubm.ro,
More informationDesign and Implementation of Signal Processor for High Altitude Pulse Compression Radar Altimeter
2012 4th International Conference on Signal Processing Systems (ICSPS 2012) IPCSIT vol. 58 (2012) (2012) IACSIT Press, Singapore DOI: 10.7763/IPCSIT.2012.V58.13 Design and Implementation of Signal Processor
More informationDeveloping and Prototyping Next-Generation Communications Systems
Developing and Prototyping Next-Generation Communications Systems Dr. Amod Anandkumar Team Lead Signal Processing and Communications Application Engineering Group 2015 The MathWorks, Inc. 1 Proliferation
More informationVHDL based Design of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing
IJSTE - International Journal of Science Technology & Engineering Volume 3 Issue 01 July 2016 ISSN (online): 2349-784X VHDL based Design of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder
More informationGlobally Asynchronous Locally Synchronous (GALS) Microprogrammed Parallel FIR Filter
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 5, Ver. II (Sep. - Oct. 2016), PP 15-21 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Globally Asynchronous Locally
More informationImplementation of Digital Communication Laboratory on FPGA
Implementation of Digital Communication Laboratory on FPGA MOLABANTI PRAVEEN KUMAR 1, T.S.R KRISHNA PRASAD 2, M.VIJAYA KUMAR 3 M.Tech Student, ECE Department, Gudlavalleru Engineering College, Gudlavalleru
More informationFPGA & Pulse Width Modulation. Digital Logic. Programing the FPGA 7/23/2015. Time Allotment During the First 14 Weeks of Our Advanced Lab Course
1.9.8.7.6.5.4.3.2.1.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 DAC Vin 7/23/215 FPGA & Pulse Width Modulation Allotment During the First 14 Weeks of Our Advanced Lab Course Sigma Delta Pulse Width Modulated
More informationMULTIRATE IIR LINEAR DIGITAL FILTER DESIGN FOR POWER SYSTEM SUBSTATION
MULTIRATE IIR LINEAR DIGITAL FILTER DESIGN FOR POWER SYSTEM SUBSTATION Riyaz Khan 1, Mohammed Zakir Hussain 2 1 Department of Electronics and Communication Engineering, AHTCE, Hyderabad (India) 2 Department
More informationDesign and Implemetation of Degarbling Algorithm
Design and Implemetation of Degarbling Algorithm Sandeepa S M Pursuing M.Tech (VLSI&ES) Newton s Institute of Engineering, Macherla, Andhra Pradesh, India S Saidarao Assistant Professor (ECE) Newton s
More information2015 The MathWorks, Inc. 1
2015 The MathWorks, Inc. 1 What s Behind 5G Wireless Communications? 서기환과장 2015 The MathWorks, Inc. 2 Agenda 5G goals and requirements Modeling and simulating key 5G technologies Release 15: Enhanced Mobile
More informationFIR Filter Design on Chip Using VHDL
FIR Filter Design on Chip Using VHDL Mrs.Vidya H. Deshmukh, Dr.Abhilasha Mishra, Prof.Dr.Mrs.A.S.Bhalchandra MIT College of Engineering, Aurangabad ABSTRACT This paper describes the design and implementation
More informationREAL-TIME HILBERT TRANSFORM AND AUTOCORRELATION FOR DIGITAL WIDEBAND COMMUNICATION APPLICATIONS
REAL-TIME HILBERT TRANSFORM AND AUTOCORRELATION FOR DIGITAL WIDEBAND COMMUNICATION APPLICATIONS A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Engineering
More informationStratix II Filtering Lab
October 2004, ver. 1.0 Application Note 362 Introduction The filtering reference design provided in the DSP Development Kit, Stratix II Edition, shows you how to use the Altera DSP Builder for system design,
More informationREALISATION OF AWGN CHANNEL EMULATION MODULES UNDER SISO AND SIMO
REALISATION OF AWGN CHANNEL EMULATION MODULES UNDER SISO AND SIMO ENVIRONMENTS FOR 4G LTE SYSTEMS Dr. R. Shantha Selva Kumari 1 and M. Aarti Meena 2 1 Department of Electronics and Communication Engineering,
More informationDesign of FIR Filter on FPGAs using IP cores
Design of FIR Filter on FPGAs using IP cores Apurva Singh Chauhan 1, Vipul Soni 2 1,2 Assistant Professor, Electronics & Communication Engineering Department JECRC UDML College of Engineering, JECRC Foundation,
More informationFPGA-BASED DESIGN AND IMPLEMENTATION OF THREE-PRIORITY PERSISTENT CSMA PROTOCOL
U.P.B. Sci. Bull., Series C, Vol. 79, Iss. 4, 2017 ISSN 2286-3540 FPGA-BASED DESIGN AND IMPLEMENTATION OF THREE-PRIORITY PERSISTENT CSMA PROTOCOL Xu ZHI 1, Ding HONGWEI 2, Liu LONGJUN 3, Bao LIYONG 4,
More informationPRODUCT HOW-TO: Building an FPGA-based Digital Down Converter
PRODUCT HOW-TO: Building an FPGA-based Digital Down Converter By Richard Kuenzler and Robert Sgandurra Embedded.com (06/03/09, 06:37:00 AM EDT) The digital downconverter (DDC) has become a cornerstone
More informationDesign and Implementation of Parallel Micro-programmed FIR Filter Using Efficient Multipliers on FPGA
2018 IJSRST Volume 4 Issue 2 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology Design and Implementation of Parallel Micro-programmed FIR Filter Using Efficient Multipliers
More informationA HIGH PERFORMANCE HARDWARE ARCHITECTURE FOR HALF-PIXEL ACCURATE H.264 MOTION ESTIMATION
A HIGH PERFORMANCE HARDWARE ARCHITECTURE FOR HALF-PIXEL ACCURATE H.264 MOTION ESTIMATION Sinan Yalcin and Ilker Hamzaoglu Faculty of Engineering and Natural Sciences, Sabanci University, 34956, Tuzla,
More informationImplementation and Comparison of Low Pass FIR Filter on FPGA Using Different Techniques
Implementation and Comparison of Low Pass FIR Filter on FPGA Using Different Techniques Miss Pooja D Kocher 1, Mr. U A Patil 2 P.G. Student, Department of Electronics Engineering, DKTE S Society Textile
More informationImplementation of Huffman Decoder on Fpga
RESEARCH ARTICLE OPEN ACCESS Implementation of Huffman Decoder on Fpga Safia Amir Dahri 1, Dr Abdul Fattah Chandio 2, Nawaz Ali Zardari 3 Department of Telecommunication Engineering, QUEST NawabShah, Pakistan
More informationFPGA-BASED PULSED-RF PHASE AND AMPLITUDE DETECTOR AT SLRI
doi:10.18429/jacow-icalepcs2017- FPGA-BASED PULSED-RF PHASE AND AMPLITUDE DETECTOR AT SLRI R. Rujanakraikarn, Synchrotron Light Research Institute, Nakhon Ratchasima, Thailand Abstract In this paper, the
More informationHardware Implementation of Automatic Control Systems using FPGAs
Hardware Implementation of Automatic Control Systems using FPGAs Lecturer PhD Eng. Ionel BOSTAN Lecturer PhD Eng. Florin-Marian BÎRLEANU Romania Disclaimer: This presentation tries to show the current
More informationBeam Forming Algorithm Implementation using FPGA
Beam Forming Algorithm Implementation using FPGA Arathy Reghu kumar, K. P Soman, Shanmuga Sundaram G.A Centre for Excellence in Computational Engineering and Networking Amrita VishwaVidyapeetham, Coimbatore,TamilNadu,
More informationPerformance Measurement of Digital Modulation Schemes Using FPGA
International Journal of Research in Engineering and Science (IJRES) ISSN (Online): 2320-9364, ISSN (Print): 2320-9356 Volume 3 Issue 12 ǁ December. 2015 ǁ PP.20-25 Performance Measurement of Digital Modulation
More informationBPSK_DEMOD. Binary-PSK Demodulator Rev Key Design Features. Block Diagram. Applications. General Description. Generic Parameters
Key Design Features Block Diagram Synthesizable, technology independent VHDL IP Core reset 16-bit signed input data samples Automatic carrier acquisition with no complex setup required User specified design
More informationDIGITAL PRE-DISTORTION LINEARIZER FOR A REALIZATION OF AUTOMATIC CALIBRATION UNIT
DIGITAL PRE-DISTORTION LINEARIZER FOR A REALIZATION OF AUTOMATIC CALIBRATION UNIT Tien Dzung DOAN, Chih Fung LAM, Kei SAKAGUCHI, Jun-ichi TAKADA, Kiyomichi ARAKI Graduate School of Science and Engineering,
More informationCHAPTER 5 IMPLEMENTATION OF MULTIPLIERS USING VEDIC MATHEMATICS
49 CHAPTER 5 IMPLEMENTATION OF MULTIPLIERS USING VEDIC MATHEMATICS 5.1 INTRODUCTION TO VHDL VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. The other widely used
More informationCyclone II Filtering Lab
May 2005, ver. 1.0 Application Note 376 Introduction The Cyclone II filtering lab design provided in the DSP Development Kit, Cyclone II Edition, shows you how to use the Altera DSP Builder for system
More informationWhat is New in Wireless System Design
What is New in Wireless System Design Houman Zarrinkoub, PhD. houmanz@mathworks.com 2015 The MathWorks, Inc. 1 Agenda Landscape of Wireless Design Our Wireless Initiatives Antenna-to-Bit simulation Smart
More informationWhat s Behind 5G Wireless Communications?
What s Behind 5G Wireless Communications? Marc Barberis 2015 The MathWorks, Inc. 1 Agenda 5G goals and requirements Modeling and simulating key 5G technologies Release 15: Enhanced Mobile Broadband IoT
More informationEXPERIMENT 1: INTRODUCTION TO THE NEXYS 2. ELEC 3004/7312: Signals Systems & Controls EXPERIMENT 1: INTRODUCTION TO THE NEXYS 2
ELEC 3004/7312: Signals Systems & Controls Aims In this laboratory session you will: 1. Gain familiarity with the workings of the Digilent Nexys 2 for DSP applications; 2. Have a first look at the Xilinx
More informationImplementing Multipliers with Actel FPGAs
Implementing Multipliers with Actel FPGAs Application Note AC108 Introduction Hardware multiplication is a function often required for system applications such as graphics, DSP, and process control. The
More informationLecture 3, Handouts Page 1. Introduction. EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Simulation Techniques.
Introduction EECE 353: Digital Systems Design Lecture 3: Digital Design Flows, Techniques Cristian Grecu grecuc@ece.ubc.ca Course web site: http://courses.ece.ubc.ca/353/ What have you learned so far?
More informationDesign of a High Speed FIR Filter on FPGA by Using DA-OBC Algorithm
Design of a High Speed FIR Filter on FPGA by Using DA-OBC Algorithm Vijay Kumar Ch 1, Leelakrishna Muthyala 1, Chitra E 2 1 Research Scholar, VLSI, SRM University, Tamilnadu, India 2 Assistant Professor,
More informationKeywords SEFDM, OFDM, FFT, CORDIC, FPGA.
Volume 4, Issue 11, November 2014 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Future to
More informationAn Accurate phase calibration Technique for digital beamforming in the multi-transceiver TIGER-3 HF radar system
An Accurate phase calibration Technique for digital beamforming in the multi-transceiver TIGER-3 HF radar system H. Nguyen, J. Whittington, J. C Devlin, V. Vu and, E. Custovic. Department of Electronic
More information