2. Transceiver Design Flow Guide

Transcription

1 2. Transceiver Design Flow Guide SIV This chapter describes the Altera-recommended basic design low that simpliies Stratix IV GX transceiver-based designs. Use the ollowing design low techniques to simpliy transceiver implementation. The Guidelines to Debug Transceiver-Based Designs on page 2 15 provides guidelines to trouble-shoot transceiver-based designs. An example o a ibre channel protocol application is also described in this chapter. The transceiver-based design is divided into phases and are detailed in the ollowing sections: Architecture on page 2 3 Implementation and Integration on page 2 7 Compilation on page 2 10 Veriication on page 2 12 Functional Simulation on page 2 12 on page 2 17 Figure 2 1 shows the design low chart o the dierent stages o the design low. The design low stages include architecture, unctional simulation, compilation, and veriication. Each stage o the design low are explained in the sections that ollow.

2 2 2 Chapter 2: Transceiver Design Flow Guide Figure 2 1. Flow Chart o the Dierent Stages in a Transceiver-Based Design Architecture Device Speciication Transceiver Coniguration Select Options in the Dynamic Reconiguration Controller (i required) Clocking Power Supplies Implementation Create Transceiver Instances Is Dynamic Reconiguration Required? No Yes Create a Dynamic Reconiguration Controller using the ALTGX_Reconig MegaWizard Create Reset and Control Logic Create Data Processing Logic Integrate the Design Functional Simulation I used, Include the Stratix IV GX ALTGX megaunction-generated wrapper ile (.v or.vhd) and ALTGX_Reconig megaunction-generated wrapper ile Add Altera Simulation Library Files Simulate the Design Yes Is Simulation Required? No Compilation Synthesize the Design Require SignalTap or Veriication? No Create Pin and OCT Assignments Yes Veriication Add signals to SignalTap II Logic Analyzer Create Timing Constraints Create Clock Grouping Constraints i Required Include SignalTap ile (.stp) in the Compilation Compile the Design Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

3 Chapter 2: Transceiver Design Flow Guide 2 3 Architecture Architecture The irst step in creating a transceiver-based design is to map your system requirements with the Stratix IV GX device supported eatures. The Stratix IV GX device contains multiple transceiver channels that you can conigure in multiple data rates and protocols. It also provides multiple transceiver clocking options. For your design, identiy the transceiver capabilities and clocking options to ensure that the transceiver meets your system requirements. This section describes the critical parameters that you need to identiy as part o this architecture phase. Device Speciication The ollowing device speciications must meet your requirements: Reer to the device data sheet to ensure that the transceivers meet the data rate and electrical requirements or your target high-speed interace application; or example, the jitter speciication and voltage output dierential (V OD ) range. Check whether the device amily that you select supports your design requirements; or example, the number o transceiver channels, FPGA logic density, memory elements, and DSP blocks. I you intend to migrate to a higher logic density or higher transceiver count device in the uture, ensure that the migration device is available. For inormation about device characteristics, reer to the Transceiver Perormance Speciications section in the DC and Switching Characteristics o Stratix IV Devices chapter. For inormation about transceiver resources, reer to the Stratix IV Device Family Overview chapter. Transceiver Coniguration Use the ALTGX MegaWizard Plug-In Manager interace to conigure the Stratix IV transceiver channel s eatures and options. When selecting a transceiver coniguration, check or the ollowing parameters: Check whether the transceiver physical coding sublayer (PCS) and physical medium attachment (PMA) unctional blocks comply with your system requirements. For example, check whether the rate match (clock rate compensation) FIFO in the receiver channel PCS meets the parts per million (PPM) speciications required or your application. For more inormation about transceiver speciications, reer to the Transceiver Perormance Speciications section o the DC and Switching Characteristics o Stratix IV Devices chapter. Select a coniguration that meets your latency requirements. I your system has maximum latency requirements through the transceiver data path, consider the appropriate unctional coniguration. The Stratix IV GX transceiver supports various conigurations that dier in latency (or example, low latency PCS mode and Basic [PMA direct] mode).

4 Chapter 2: Transceiver Design Flow Guide 2 4 Architecture In some conigurations, speciic unctional blocks in the transceiver are disabled or bypassed. Beore you select a transceiver coniguration, understand the unctional blocks that must be implemented in the FPGA abric. For example, Basic (PMA direct) mode provides reduced latency but does not have PCS unctional blocks enabled (or example, word aligner and 8B/10B encoder). Thereore, implement these unctional blocks in the FPGA abric i you need them in your application. Some examples o unctional blocks that you may need to implement in the FPGA abric are shown in Create Data Processing and Other User Logic on page 2 8. For more inormation about the ALTGX MegaWizard Plug-In Manager, reer to the ALTGX Megaunction User Guide chapter. Check whether the loop-back eatures are available or your selected unctional mode. The Stratix IV GX transceiver provides diagnostic loop-back eatures between the transmitter channel and the receiver channel at the transceiver PCS and PMA interaces. These loop-back eatures help in debugging your design. I your design uses multiple transceiver channels within the same transceiver block, based on the transceiver channel conigurations, the Quartus II sotware might impose restrictions on combining these channels. For more inormation about these restrictions, reer to the Coniguring Multiple Protocols and Data Rates in a Transceiver Block chapter. Dynamic Reconiguration You can to use the Stratix IV transceivers in multiple-link interconnect environments by allowing you to dynamically reconigure the PMA controls (or example, V OD, Preemphasis, Equalization, DC gain, and the transceiver channel coniguration). You can reconigure the PMA controls without aecting any other transceiver channel or the logic in the FPGA abric. Use the transceiver channel reconiguration to dynamically switch a transceiver channel to multiple protocols and data rates. The Quartus II sotware allows you to generate a memory initialization ile (.mi) that stores unique transceiver settings and provides a dynamic reconiguration controller, which is sot logic that controls the transceiver reconiguration with minimal user interace logic. You can generate this sot logic using the ALTGX_RECONFIG MegaWizard interace. For more inormation about the ALTGX_RECONFIG interace, reer to the ALTGX_RECONFIG MegaWizard Plug-In Manager chapter. 1 All receiver channels in the Stratix IV GX device require oset cancellation to counter oset variations in process, voltage, and temperature (PVT) on the receiver. The dynamic reconiguration controller initiates the sequence to perorm oset cancellation on the receiver channels. Thereore, i you conigure the Stratix IV GX transceiver channel in Receiver only or Transmitter and Receiver coniguration, you must instantiate a dynamic reconiguration controller. For more inormation about oset cancellation or dynamic reconiguration o PMA controls or channel coniguration, reer to the Oset Cancellation Feature section in the Stratix IV Dynamic Reconiguration chapter.

5 Chapter 2: Transceiver Design Flow Guide 2 5 Architecture Clocking The Stratix IV GX transceiver is clocked by various input reerence clocks, or example: Dedicated transceiver reerence clock (reclk) pins. Altera recommends using reclk pins whenever possible because the reclk pins yield reduced jitter on the transmitted data. Clock sources connected to global clock lines. Clock outputs rom the phase-locked loops (PLLs) in the FPGA abric. Identiy the transceiver channels input reerence clock sources, or example: Ensure that your selected device has the required number o input reerence clock resources to implement your design. Ensure that the transceiver clock input supports the required I/O standards. Ensure that the clocking restrictions work with your selected device: Check whether the allowed requencies or the transceiver input reerence clocks meet your system requirements. I you use the PLL cascade clock, understand its restrictions. I you are using the auxiliary transmit (ATX) PLL, understand the recommendations or the input reerence clock sources and the restrictions on data rate ranges supported by the ATX PLL. For transceiver-fpga interace clocking: Ensure that the transceiver-fpga interace clock requency limits meet your system requirements. For inormation about transceiver speciications, reer to the DC and Switching Characteristics o Stratix IV Devices chapter. Identiy the clocking scheme to clock the transceiver data to the logic in the FPGA abric. For example, i your design has multiple transceiver channels that run at the same data rate and are connected to the one upstream link, you might be able to use a single transceiver-fpga clock to provide clocks to the transceiver data path, which can conserve clock routing resources. I you are using Basic (PMA direct) mode, determine whether you require a let/right PLL to provide phase shited clocks to the FPGA abric. The let/right PLL clocks the data received and transmitted between the transceiver and the FPGA abric interace and may be required to meet the timing requirements o the data transer. For inormation about transceiver clocking, reer to the Stratix IV Transceiver Clocking chapter. Ater you identiy the required transceiver parameters, start the implementation and integration phase.

6 Chapter 2: Transceiver Design Flow Guide 2 6 Architecture Power Supplies The Stratix IV GX device requires multiple power supplies. The pin connection guidelines provide speciic recommendations about the type o power supply regulator (linear or switching) and the voltage supply options and restrictions. For example, the transmitter buer supply VCCHTx has two options -1.5 V and 1.4 V. There are speciic data rate restrictions when using 1.5 V. You must understand these restrictions when you select a power supply value. For more inormation, reer to the Stratix IV Pin Connection Guidelines. Estimate the power required to run your design. This estimation allows you to select the appropriate power supply modules and to design the power distribution network on your board. Use the Early Power Estimator tool to estimate the transient current requirements. For more inormation about the Early Power Estimation tool, reer to the Stratix III and Stratix IV PowerPlay Early Power Estimator. I your design is already complete, use the power optimization eatures available in the Stratix IV Devices. For more inormation about optimizing power in Stratix IV FPGA devices, reer to AN 514: Power Optimization in Stratix IV FPGAs. Board Design Requirements For improved signal integrity on the high-speed serial interace, ollow the best design practices or your power distribution network, PCB design, and stack up. For detailed guidelines and recommendations about your power distribution network, PCB design, and stack up, reer to the Board Design Resource Center web site. For more inormation about the Stratix IV GX design process, reer to AN 519: Stratix IV Design Guidelines.

7 Chapter 2: Transceiver Design Flow Guide 2 7 Implementation and Integration Implementation and Integration Create Transceiver Instances There are three steps to the implementation and integration phase: Create Transceiver Instances on page 2 7 Create Reset Logic to Control the FPGA Fabric and Transceivers on page 2 34 Create Data Processing and Other User Logic on page 2 36 The ALTGX MegaWizard Plug-In Manager to creates the transceiver instance. In the architecture phase, you identiied the transceiver coniguration or your design. Using the ALTGX MegaWizard Plug-In Manager, select the appropriate parameters that apply to your architecture requirements. Reset signals: The ALTGX MegaWizard Plug-In Manger provides various reset and status signals: Reset signals tx_digitalreset, rx_digitalreset, rx_analogreset, and pll_powerdown are required to reset the transceiver PCS and PMA unctional blocks. Status signals rx_reqlocked and pll_locked indicate the state o the receiver CDR and transmitter PLL, respectively. Use these reset and status signals to implement the transceiver reset control logic in the FPGA abric. For more inormation, reer to Create Reset and Control Logic on page 2 8. I you determine that your application requires dynamic reconiguration, select the options in the Reconig screen o the ALTGX MegaWizard interace. I you intend to dynamically reconigure the channel into other protocol modes or data rates, the Reconig screen provides multiple options (or example, the channel interace and Use alternate PLL options) to enable this eature. To understand the logical channel addressing, logical PLL index, and type o reconiguration to select options in the Reconig screen, reer to the Channel and CMU PLL Reconiguration Mode Details section in the Stratix IV Dynamic Reconiguration chapter. Depending on your system, when you use multiple transceiver channels, you might be able to share the transmitter and receiver parallel clocks o one channel with the other channels. I your design requires sharing a clock resource, select the tx_coreclk and rx_coreclk ports. Transceiver-FPGA abric interace clock sharing conditions are provided in the Stratix IV Transceiver Clocking chapter. For more inormation about using the ALTGX MegaWizard Plug-In Manager and the unctionality o the dierent options and signals available, reer to the ALTGX Megaunction User Guide chapter.

8 Chapter 2: Transceiver Design Flow Guide 2 8 Implementation and Integration Create Dynamic Reconiguration Controller Instances Use the ALTGX_RECONFIG MegaWizard interace to create the dynamic reconiguration controller instance. I you intend to use the channel and CMU PLL reconiguration eature, select the relevant options in the ALTGX_RECONFIG Megawizard Plug-In Manager. For descriptions o the options in the ALTGX_RECONFIG megaunction, reer to the Stratix IV ALTGX_RECONFIG Megaunction User Guide chapter. For more inormation about using the signals, reer to the Stratix IV Dynamic Reconiguration chapter. Create Reset and Control Logic The reset sequence is important or initializing the transceiver unctional blocks to proper operating condition. Altera recommends a reset sequence or dierent transceiver conigurations and protocol unctional modes. The ALTGX MegaWizard Plug-In Manager provides the tx_digitalreset, rx_analogreset, rx_digitalreset, and pll_powerdown signals to reset the dierent unctional blocks o the transceiver. You can reset the CMU PLL or the ATX PLL (based on your selection) using the pll_powerdown signal. For transceiver instances that share the same CMU PLL or ATX PLL, the pll_powerdown port o these instances must be driven by the same logic. For more inormation about reset sequences, reer to the Reset Control and Powerdown chapter. Create Data Processing and Other User Logic A typical transceiver-based design consists o custom data processing and other user logic that must be implemented in the FPGA abric based on your application requirements. In addition to application-speciic logic, or speciic transceiver conigurations, you may need additional logic to interace with the transceivers. This section provides examples o such logic. PPM Detector When the Receiver CDR Is Used in Manual Lock Mode Each receiver channel contains a clock data recovery (CDR) that you can use in automatic or manual lock mode. I you use receiver CDR in manual lock mode, you can control the timing o the CDR to lock to the input reerence clock using the rx_locktoreclk port or lock to the recovered data using the rx_locktodata port. When you use the receiver CDR in manual lock mode, you may need to implement the PPM detector in the FPGA abric to determine the PPM dierence between the upstream transmitter and the Stratix IV GX receiver.

9 Chapter 2: Transceiver Design Flow Guide 2 9 Implementation and Integration Synchronization State Machine in Manual Word Alignment Mode Each receiver channel contains a synchronization state machine in the PCS that you can enable in certain unctional modes. The synchronization state machine triggers the loss o synchronization status to the FPGA abric based on invalid 8B/10B code groups. However, the synchronization state machine in the PCS is not available in some unctional modes. You may need to implement custom logic in the FPGA abric to indicate the loss-o-synchronization status o the received data. Gear Boxing Logic Some protocols require a wider data path than provided by the transceiver interace; or example, the Interlaken Protocol requires 64/67-bit encoding and decoding, but the maximum data path interace in the Stratix IV GX transceiver is 40 bits. Thereore, you must implement gear boxing logic to interace the 64/67-bit encoder-decoder with the transceiver interace. Functional Blocks to Interace with the Transceiver Conigured in Basic (PMA Direct) Mode In Basic (PMA direct) mode, all the PCS unctional blocks in the transceiver channel are disabled. Thereore, you may need to implement the ollowing blocks in the FPGA abric: Word Alignment To align the byte boundary on the received data. Byte Deserializer To increase the data path width to the rest o the user logic and to reduce the clock requency o the data path by two. Phase Compensation FIFO (or bonded channel applications) In bonded channel applications in which multiple transceiver channels are connected to the same upstream system (or example, one Interlaken Protocol link using 24 transceiver channels). To minimize the global clock routing resources you use, implement a phase compensation FIFO to interace the receiver side o the transceiver interace with the logic in the FPGA Fabric. Use the recovered clock rom each channel to clock the write side o the phase compensation FIFO. Use the recovered clock rom any o the channels to clock the read side o the phase compensation FIFO. With this method, you only use one clock resource and the subsequent receive-side logic in the FPGA abric can operate in this single clock domain. Deskew Logic (or bonded channel applications) In bonded channel applications in which multiple transceiver channels are connected to the same upstream system, the data received between multiple channels are not aligned due to potential skew in the interconnect and the upstream transmitter system. To compensate or the skew, use deskew logic in the FPGA abric. Encoding/Decoding or Scrambling/Descrambling Many protocols require the transmitter data to be encoded or scrambled to maintain signal integrity. This logic may be required in the FPGA abric based on your application requirements.

10 Chapter 2: Transceiver Design Flow Guide 2 10 Compilation Integrate the Design Ater you implement all o the required logic, integrate the transceiver instances with the remaining logic and provide the appropriate transceiver-fpga abric interace clocking. Synthesize the design using third-party synthesis tools, such as Synopsys Synplicity or the Quartus II sotware synthesis tool. This allows you to detect the syntax errors in your design. Compilation I you are using the transceiver in Basic (PMA direct) mode, you must develop all the PCS unctionality in the FPGA abric. When you compile your design, the Quartus II sotware generates an SRAM Object File (.so) or programmer object ile (.po) that you can download to the Stratix IV GX hardware. Typically, the irst step in compiling the design is assigning pin locations or the I/Os and clocks. Use the pin planner tool in the Quartus II sotware to assign pins. 1 For a basic tutorial on the Quartus II sotware, open the Quartus II sotware, click the Help menu and select Tutorial. Stratix IV GX transceivers support a variety o I/O standards or the input reerence clocks and serial data pins. Assign pins and the logic level standard (or example, 1.5-V PCML and LVDS) or the input and output pins. For more inormation, reer to the I/O Features in Stratix IV Devices chapter. I you share the same transceiver-fpga abric interace clocks or multiple transceiver channels (tx_coreclk and rx_coreclk) in your design, set the 0 ppm constraints. These constraints enable the Quartus II sotware to relax the legality check restrictions on clocking. For more inormation, reer to the Common Clock Driver Selection Rules section o the Stratix IV Transceiver Clocking chapter. For transceiver serial pins and reclk pins, set the on-chip termination (OCT) resistor settings. For more inormation about supported OCT settings, reer to Transmitter Output Buer section o the Stratix IV Transceiver Architecture chapter. Create timing constraints or the clocks and data paths. Use the TimeQuest Timing Analyzer to set timing constraints. For more inormation about the TimeQuest Timing Analyzer, reer to the Quartus II Development Sotware Handbook. Compile the design. This generates a.so that can be downloaded in the FPGA.

11 Chapter 2: Transceiver Design Flow Guide 2 11 Compilation The Quartus II sotware generates multiple report iles that contain inormation such as transceiver coniguration and clock resource utilization. The ollowing section describes the report iles relevant to using transceivers and clock resource. Report Files The Quartus II sotware provides a report ile in the synthesis, itter, map, placement, and assembler stages. The report ile provides useul inormation on the device and transceiver coniguration generated by the Quartus II sotware. This section only describes the reports provided in the itter stage. To access the report, click on the Processing menu, select the Compilation Report option and expand the Fitter tab. Fitter Summary The itter summary provides high-level inormation on FPGA abric resources and transceiver channels used by your design. For example, to ensure that the Quartus II sotware has created the number o transceiver channels as speciied in your design, reer to the GXB Receiver channels and GXB Transmitter channels ield at the bottom o the report. For detailed inormation on resource utilization, expand the Fitter tab. Pin-Out File Select the Pin-Out ile option under the Fitter tab. The Quartus II sotware displays the I/O standards and bank numbers o all the pins (used and unused) needed to connect to the board. The Quartus II sotware also generates a PIN ile (.pin) with the above inormation. Altera recommends that you use the.pin as a guideline. Use the pin connection guidelines or board layout. For more inormation about pin connection guidelines or board layout, reer to Stratix IV GX Device Family Pin Connection Guidelines. Resource Section Expand the Resource Section option under the Fitter tab to view the ollowing tabs: The GXB Transmitter channel tab Provides generated settings or all the transmitter channels instantiated in your design. The GXB Transmitter PLL tab Provides generated settings or all the transmitter PLLs instantiated in your design. The GXB Receiver channel tab Provides generated settings or all the receiver channels instantiated in your design. The Global and other ast signals tab Displays the list o clock and other signals in your design that are assigned to the global and regional clock resources. You can use the report ile to veriy whether the transceiver settings (or example, data rate), are generated per your settings in the ALTGX MegaWizard Plug-In Manager.

12 Chapter 2: Transceiver Design Flow Guide 2 12 Veriication Veriication The SignalTap Logic Analyzer allows you to veriy design unctionality using the on-chip logic analyzer. SignalTap provides options to create multiple sets o signals that can be sampled using dierent trigger clocks. You can add the signals to the SignalTap Logic Analyzer and save the ile as an STP ile (.stp). When you include this.stp along with the design iles and compile the design, the Quartus II sotware creates an.so that allows you to veriy the unctionality o the signals that you added in the SignalTap Logic Analyzer ile. You can run the.stp that connects to the device through the JTAG port and displays the signal transitions using the Quartus II sotware. Because the JTAG port is required to run SignalTap, consider designing the board with the JTAG interace or debugging your system. For more inormation about using SignalTap, reer to the In-System Design Debugging section in volume 3 o the Quartus II Development Sotware Handbook. To veriy the unctionality o the PCS and PMA blocks, the Stratix IV GX transceiver provides diagnostic loop-back eatures between the transmitter and receiver channels. For more inormation, reer to the Loopback Modes section in the Stratix IV Transceiver Architecture chapter. Functional Simulation Use the ALTGX MegaWizard-generated wrapper ile to simulate the instantiated transceiver coniguration in third-party simulation sotware such as ModelSim. For simulation, speciic Altera simulation library iles are required (listed in Table 2 1). The ollowing library iles are available in VHDL and Verilog versions: 220pack 220model altera_m_components altera_m sgate_pack sgate stratixiv_hssi_component stratixiv_hssi_atoms These simulation iles are available under the ollowing older in the Quartus II installation directory: <Quartus II installation older>/eda/sim_lib 1 The stratixiv_hssi_component library ile is only applicable i the transceiver instance is created using VHDL.

13 Chapter 2: Transceiver Design Flow Guide 2 13 Functional Simulation For VHDL simulation using ModelSim, create the ollowing libraries in your ModelSim project: lpm sgate altera_m stratixiv_hssi These simulation iles are available under <Quartus II installation older\quartus\eda\sim_lib>. Compile the simulation iles into the libraries speciied in Table 2 1. Table 2 1. Library to Compile Simulation Files Altera Simulation Files 220pack 220model sgate pack sgate altera_m_components altera_m stratixiv_hssi_component stratixiv_hssi_atoms user design iles Library lpm lpm sgate sgate altera_m altera_m stratixiv_hssi stratixiv_hssi work For example, to compile a ile into a speciic library using ModelSim, right click on the ile, select Properties, then click the General tab. In the Compile to library option, select the corresponding library or the ile selected. Figure 2 2 shows the ModelSim window compilation o iles in a speciic library or the Stratix II GX device.

14 2 14 Chapter 2: Transceiver Design Flow Guide Functional Simulation Figure 2 2. ModelSim Option to Compile Files in a Speciic Library Include all the libraries in the search path. Add the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Manager-generated wrapper iles (.v or.vhd) and all o the design iles to the library. Compile all the library iles irst, then the design iles, and lastly run the simulation. For Verilog simulation, add the ALTGX and ALTGX_RECONFIG MegaWizard Plug-In Manager-generated Verilog wrapper iles (.v), the Altera library iles, and all o the design iles. Compile all the library iles irst, then the simulation model ile, ollowed by the design iles. Lastly, run the simulation. These guidelines are urther described in Example 1: Fibre Channel Protocol Application below. For more inormation about unctional RTL simulation or post-it simulation, reer to the Simulation chapter in volume 3 o the Quartus II Handbook. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

15 Chapter 2: Transceiver Design Flow Guide 2 15 Guidelines to Debug Transceiver-Based Designs Guidelines to Debug Transceiver-Based Designs This section provides guidelines to debug transceiver-based designs. I a system ailure occurs, the irst step is to ensure the unctionality o the logic within the FPGA. Use the ollowing inormation when you observe a system ailure. Guidelines to Debug the FPGA Logic and the Transceiver Interace Beore checking the unctionality in silicon, perorm unctional simulation to ensure the basic unctionality o the RTL and the transceiver-fpga abric interace. Understand the limitations o unctional simulation. I you intend to simulate timing parameters, consider post-it simulation. The unctional simulation model or transceivers does not model timing-related parameters or uncertainties in the transceiver data path. For example, the PPM dierence in the rate matcher clocks (clock rate compensation) or the phase dierences between the read and write side o the phase compensation FIFO are not modeled. For inormation about unctional RTL simulation or post-it simulation, reer to the Simulation chapter in volume 3 o the Quartus II Handbook. Check whether the compiled design has timing violations in the TimeQuest Timing Analyzer report. Set the appropriate timing constraints on the ailing paths. For inormation about using the TimeQuest Timing Analyzer, reer to the Timing Analysis chapter in volume 3 o the Quartus II Handbook. Veriy the unctionality o the transmitter and receiver data path with serial loopback. Dynamically control the serial loopback through the rx_seriallpbken port. When this signal is asserted, data rom the transmitter serializer is looped back to the receiver CDR o the channel. Use SignalTap to veriy the behavior o the user logic and the transceiver interace signals. I you have FPGA I/O pins available or debug, you can also use the external logic analyzer to debug the unctionality o the device. For more inormation, reer to the In-System Debugging Using External Logic Analyzers chapter in volume 3 o the Quartus II Handbook. 1 To use these eatures, you must connect the JTAG coniguration pins in the FPGA. Veriy the interconnect on the receive side by coniguring the transceiver in reverse serial loopback mode. In this case, the recovered data rom the receiver channel is sent to the transmitter buer. To conigure a transceiver channel operating in a dierent coniguration to reverse serial loopback mode, use the dynamic reconiguration controller. Check whether the transceiver FPGA abric interace clocking schemes ollow the recommendations provided in the FPGA Fabric-Transceiver Interace Clocking section in the Stratix IV Transceiver Clocking chapter. Ensure that you have used the recommended transceiver reset sequence.

16 2 16 Chapter 2: Transceiver Design Flow Guide Guidelines to Debug Transceiver-Based Designs Guidelines to Debug System Level Issues I you have determined that the logic in the FPGA abric is unctionally correct, check or system level issues: Check the voltage ripple across the 2 kω resistor that is connected to the RREF pin. The voltage ripple must be less than 60 mv. Measure the eye on the near-end and ar-end o the transmitter to understand the jitter added by the transmitter and interconnect. Ensure that the high-speed scopes you use or measurement have suicient bandwidth (bandwidth rating on the scope and cables must be at least three times the serial data rate). Check whether the eye meets the eye-mask requirements i speciied by the protocol application. Use scopes that provide inormation on the dierent jitter components to understand the possible source o the increased jitter. For example, increased intersymbol interace (ISI) indicates potential bandwidth limitations on the interconnect. 1 Some scopes, such as Agilent 86100C DCA, require pre-deined patterns (or example, PRBS7 or PRBS23) to provide jitter components. Measure signals on the traces (no connector) using high-impedance dierential probe with short leads. Ensure that characteristic impedance on the interconnect matches the source and load systems. Check or impedance discontinuities on the trace by Time Domain Relectometry (TDR). Revisit the board design, layout, and routing or any inconsistencies that can cause impedance discontinuities. Check whether the termination schemes on the Stratix IV GX device and on the upstream system are matched. Altera recommends using OCT in the Stratix IV GX device instead o external termination to improve signal integrity. Change the transmit output dierential voltage to improve eye amplitude. Compensate or high requency losses in the interconnect by changing the equalization settings o the Stratix IV GX device and check or improvement o the bit error rate. I the upstream system does not have an equalization eature, increase the pre-emphasis (1st post tap) o the Stratix IV GX transmitter. In cases where there are multiple interconnects between the Stratix IV GX device and upstream system, use the pre-tap and 2nd post tap. Altera provides tools to select the pre-emphasis. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

17 Chapter 2: Transceiver Design Flow Guide 2 17 Measure the increase in jitter at the near end and ar end with one channel turned on at a time i you have multiple transceiver channels connected to the upstream system. This helps to observe the eect o cross talk rom adjacent channels on the victim channel. Check the board layout and routing to ensure that you have implemented the design practices to mitigate cross talk. Ensure that the input voltage and duty cycle o the input reerence clock source provided to the transmitter PLLs meet the input reerence clock requirements. Check whether the voltage drop on the power supplies is within the speciied tolerance range. Measure the voltage at the via beneath the power supply pin using a highimpedance probe. Check whether the voltage regulator speciications meet the Stratix IV GX power supply requirements. Revisit the power distribution scheme or the supply voltage to ensure that it is designed to handle the transient current requirements o the transceiver. For the tolerance values o the dierent power supplies, reer to the Stratix IV DC and Switching Characteristics chapter. Check or periodic modulation o other requency components on the transmit data. Send a high-requency pattern (1010) rom the transmitter side and connect the transmitter serial output to a spectrum analyzer. For more inormation about Stratix IV GX transceivers, reer to AN 553: Debugging Transceivers. Assume that you want to implement a ibre channel protocol application using three transceiver channels. Consider the ollowing system requirements: You need three transceiver channels All the channels need to be placed in the same transceiver block All the channels need to have independent control to reset their PCS and PMA unctional blocks Table 2 2 shows the transceiver channel coniguration or Example 1. Table 2 2. Transceiver Channel Coniguration or Example 1 Channels Mode o Operation Data Rate Input Reerence Clock Frequency 0 Receiver and Transmitter FC4G (4.25 Gbps) MHz 1 Receiver and Transmitter FC1G ( Gbps) MHz 2 Transmitter Only FC4G (4.25 Gbps) MHz

18 2 18 Chapter 2: Transceiver Design Flow Guide Phase 1 Architecture Table 2 3. Device Speciic Parameters In this phase, check whether the Stratix IV GX device supports or meets your design requirements. Device Speciication Consider the questions listed in Table 2 3 beore setting device-speciic parameters. Questions Do the parameters meet the ibre channel protocol electrical requirements? Are three transceiver channels available? Is there support or 4.25 Gbps and Gbps data rates? Answer Yes For more inormation, reer to the Transceiver Perormance Characteristics section in the DC and Switching Characteristics o Stratix IV Devices chapter Yes Yes Two CMU PLLs are available within each transceiver block to support two dierent transmitter data rates. Each receiver channel contains a dedicated receiver CDR that supports 4.25 Gbps and Gbps data rates. For the maximum data rates supported, reer to the Transceiver Perormance Speciications section in the DC and Switching Characteristics o Stratix IV Devices chapter. Table 2 4. Coniguring the Transceiver Transceiver Coniguration The ibre channel protocol uses an 8B/10B encoder and requires clock rate compensation. Functional Blocks Consider the questions listed in Table 2 4 beore coniguring the transceiver. Questions Is the 8B/10B encoder in the PCS block ibre channel compliant? Is there a workaround? Is the clock rate compensation block in the PCS available without an 8B/10B encoder? Answer No The ibre channel protocol consists o two dierent End-o- Frame (EOFt) ordered sets. The correct EOFt ordered set sent by user logic depends on the ending disparity o the word preceeding the EOFt. The Stratix IV GX transceiver does not provide running disparity lags to the user logic. Thereore, the user logic might not be able to select the correct EOFt ordered set. Yes Implement the 8B/10B encoder in the FPGA abric. No You can implement this in the FPGA abric. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

19 Chapter 2: Transceiver Design Flow Guide 2 19 Table 2 5. Multiple Channels The design requires a Transmitter and Receiver coniguration or two channels and a Transmitter Only coniguration or one channel (Table 2 5). Questions Does the Stratix IV GX transceiver support these two conigurations and allow you to combine them within the same transceiver block Answer Yes The available FPGA abric interace width is 20 or 40 bits to support 4.25 Gbps and Gbps data rates, respectively. This FPGA abric interace acilitates 8B/10B encoding and decoding in the FPGA abric without additional rearrangement o the received parallel data to a 10-bit boundary. Dynamic Reconiguration I your application requires you to dynamically reconigure the transceiver PMA controls, ensure that you understand the settings, options, and user logic required to enable this eature. For more inormation, reer to the Interacing ALTGX and ALTGX_RECONFIG Instances section in the Stratix IV Dynamic Reconiguration chapter. For more inormation about initiating read and write transactions, reer to the Dynamically Reconiguring PMA Controls section in the Stratix IV Dynamic Reconiguration chapter. I you are using the channel reconiguration eature, enable the appropriate options in the ALTGX and ALTGX_RECONFIG MegaWizards. You can dynamically use the reconiguration modes to reconigure dierent unctional blocks in a transceiver channel using.mis. For inormation about generating.mis, reer to the Channel and CMU PLL Reconiguration Mode Details section in the Stratix IV Dynamic Reconiguration chapter. Clocking Consider the questions listed in Table 2 6 beore coniguring clocking. Table 2 6. Coniguring Clocking (Part 1 o 2) Questions Is there support or two dierent input reerence clocks? Do the reclk pins support the required requency range? Answer Yes The Stratix IV GX transceiver has two reclk pins or each transceiver block. Yes The minimum requency range o reclk is 50 MHz; the maximum requency range is MHz.

20 2 20 Chapter 2: Transceiver Design Flow Guide Table 2 6. Coniguring Clocking (Part 2 o 2) Questions Can transceiver-fpga abric interace clocking be shared? Does the Stratix IV GX transceiver support this eature? Answer No The design requires independent control on all channels, so you must not share the transceiver-fpga abric interace clock o one channel with another channel. Each o the channels must use its own tx_clkout and rx_clkout signals to clock the data between the transceiver channels and the FPGA abric. Yes For more inormation about clocking the transmitter and receiver channel data path or this type o coniguration, reer to the Transmitter Channel Datapath Clocking section o the Stratix IV Transceiver Clocking chapter. Figure 2 3 shows the transmitter side o the transceiver setup or Example 1. 1 The transmitter side receives its clocks rom the clock multiplier unit (CMU) PLLs. The receiver side contains its dedicated CDR that provides the high-speed serial and low-speed parallel clocks to its PMA and PCS blocks, respectively. Figure 2 3. Top-Level Transceiver Setup Transmitter-Side Only Transceiver Block Channel 0 (4.25 Gbps) TX RX reclk0 ( MHz) One CMU PLL Conigured or 4.25 Gbps Data Rate Channel 1 ( Gbps) reclk1 ( MHz) Second CMU PLL Conigured or Gbps Data Rate TX RX Channel 2 (4.25 Gbps) TX Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

21 Chapter 2: Transceiver Design Flow Guide 2 21 Phase 2 Implementation Create the transceiver instance using the ALTGX MegaWizard Plug-In Manager. For a description o the individual options, reer to the ALTGX Megaunction User Guide chapter. Create the Transceiver Instance or an FC4G Coniguration (Channel 0) Figure 2 4 through Figure 2 14 show the dierent options available in the ALTGX MegaWizard Plug-In Manager to create the transceiver channel instance or the FC4G data rate. Use this instance or channel 0, with the ollowing settings: General screen You can conigure the Stratix IV GX transceiver or ibre channel protocol using Basic mode. Set the options with the values shown in Figure 2 4. Figure 2 4. FC4G Instance Settings (General Screen)

22 2 22 Chapter 2: Transceiver Design Flow Guide PLL/Ports screen Check the Train Receiver CDR rom PLL inclk option, as shown in Figure 2 5. When you select this option, the same input reerence clock used or the CMU PLL is provided as a training clock to the receiver CDR. Figure 2 5. FC4G Instance Settings (PLL/Ports Screen) Check the pll_powerdown signal. This signal allows you to power down the CMU PLL. Use this signal as part o your reset sequence. Check the pll_locked signal. This signal indicates whether the CMU PLL is locked to the input reerence clock. The user logic waits until the pll_locked signal goes high beore transmitting data. Check the rx_reqlocked signal. This signal indicates whether the receiver CDR is locked to data. When the receiver CDR is conigured in automatic lock mode, assert the rx_digitalreset signal i the rx_reqlocked signal goes low to keep the receiver PCS under reset. Altera recommends speciic transceiver reset sequences to ensure proper device operation. For more inormation about receiver CDR and lock modes, reer to the Receiver Channel Datapath section o Stratix IV Transceiver Architecture chapter. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

23 Chapter 2: Transceiver Design Flow Guide 2 23 Ports /Cal Blk screen The calibration block is required so it is always enabled. Select the options shown in Figure 2 6. Figure 2 6. FC4G Instance Settings (Ports/Cal Blk Screen)

24 2 24 Chapter 2: Transceiver Design Flow Guide RX Analog screen Select the options shown in Figure 2 7. Figure 2 7. FC4G Instance Settings (RxAnalog Screen) For a description o the individual options, reer to the ALTGX Megaunction User Guide chapter. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

25 Chapter 2: Transceiver Design Flow Guide 2 25 TX Analog screen Select the output dierential voltage and common mode voltage values that meet the ibre channel protocol speciication. I you intend to transmit data through aulty interconnects, select the pre-emphasis settings shown in Figure 2 8. Figure 2 8. FC4G Instance Settings (TX Analog Screen) For more inormation about pre-emphasis settings, reer to the DC and Switching Characteristics o Stratix IV Devices chapter.

26 2 26 Chapter 2: Transceiver Design Flow Guide Reconig screen Set the starting channel number to 0. Because oset cancellation is required or receiver channels, the Oset Cancellation or Receiver Channels option is automatically enabled. Ensure that you connect the reconig_romgxb and reconig_togxb ports with the dynamic reconiguration controller (Figure 2 9). Figure 2 9. FC4G Instance Settings (Reconig Screen) 1 For more inormation about the starting channel numbers, reer to the Logical Channel Addressing While Reconiguring the PMA Controls section o the Stratix IV Dynamic Reconiguration chapter. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

27 Chapter 2: Transceiver Design Flow Guide 2 27 Lpbk screen The serial loopback option is enabled, as shown in Figure Figure FC4G Instance Settings (Lpbk Screen)

28 2 28 Chapter 2: Transceiver Design Flow Guide Basic/8B10B screen The Basic/8B10B screen is shown in Figure The 8B/10B encoder is not compatible with the ibre channel protocol application; thereore, this option is unchecked. Figure FC4G Instance Settings (Basic 8B/10B) Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

29 Chapter 2: Transceiver Design Flow Guide 2 29 Word Aligner screen The ibre channel protocol requires that you use K28.5 to align the byte boundary. In the What is the word alignment pattern? option, set one o the 10-bit disparity values to K28.5. The word aligner automatically detects when the other disparity value is received. Figure FC4G Instance Settings (Word Aligner Screen) Select the rx_patterndetect and rx_syncstatus signals. The rx_patterndetect signal indicates whenever the word alignment pattern is detected in the word boundary. Click Finish to exit the ALTGX MegaWizard Plug-In Manager.

30 2 30 Chapter 2: Transceiver Design Flow Guide Create the Transceiver Instance or an FC1G Coniguration (Channel 1) Creating the instance or FC1G is very similar to that o the FC4G coniguration, with the ollowing changes: General screen Set the values shown in Figure Figure FC1G Instance (Channel 1) Settings (General Screen) Reconig screen Set the starting channel number to 4. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

31 Chapter 2: Transceiver Design Flow Guide 2 31 Create the Instance or an FC4G Coniguration Transmitter Only Mode (Channel 2) This coniguration is similar to the channel 0 coniguration, with the ollowing changes: Set the operation mode to Transmitter Only, as shown in Figure Because this is a Transmitter Only instance, all the options relevant to the receiver are not available in the ALTGX MegaWizard Plug-In Manager. Figure FC4G_TXONLY Instance (Channel 1) Settings (General Screen)

32 2 32 Chapter 2: Transceiver Design Flow Guide Reconig screen Set the starting channel number to 8. Select the Analog controls option even i you do not intend to dynamically reconigure the PMA controls, as shown in Figure Selecting this option is required or this example scenario because: For a Transmitter Only instance, oset cancellation is not available; thereore, the reconig_romgxb and reconig_togxb ports are not available. The other two instances (containing a receiver channel) have these ports available because oset cancellation is automatically enabled. I one transceiver instance has the reconig_romgxb and reconig_togxb ports enabled, the Quartus II sotware requires the other transceiver instances to have these ports enabled to combine them in the same transceiver block. Thereore, or this Transmitter Only instance, the Analog options... must be selected. Figure FC4G_TXONLY Instance (Reconig) Screen For more inormation about the requirements to combine multiple transceiver instances, reer to the Combining Transceiver Instances in Multiple Transceiver Blocks section in the Coniguring Multiple Protocols and Data Rates in a Transceiver Block chapter. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

33 Chapter 2: Transceiver Design Flow Guide 2 33 Create the Dynamic Reconiguration Controller (ALTGX_Reconig) Instance This section only describes the relevant options that must be set to implement the application. Figure ALTGX_Reconig Settings (Reconiguration Settings Screen) For more inormation, reer to the Stratix IV Dynamic Reconiguration chapter. Figure 2 16 shows the options that you must set (assuming that you do not require dynamic reconiguration o the PMA controls in the transceiver channels). For more inormation about selecting the Number o Channels option, reer to the Total Number o Channels Option in the ALTGX_RECONFIG Instance section in the Stratix IV Dynamic Reconiguration chapter. Connect the ollowing: reconig_romgxb[16:0] o the ALTGX_RECONFIG instance to the FC4G instance (channel0) reconig_romgxb[33:17] to the FC1G instance (channel1) reconig_romgxb[50:34] to the FC4G Transmitter Only instance (channel2) reconig_togxb[3:0] o the ALTGX_RECONFIG instance to all three transceiver instances

34 2 34 Chapter 2: Transceiver Design Flow Guide Create Reset Logic to Control the FPGA Fabric and Transceivers The design requires independent control on each channel. Altera recommends creating independent reset control logic or each channel. In this design, channel 0 and channel 2 share the same CMU PLL (because they are conigured at the same data rate) and channel 1 uses the second CMU PLL. When you create a Transmitter Only or Receiver and Transmitter instance, the ALTGX MegaWizard Plug-In Manager provides a pll_powerdown signal to reset the CMU PLL that provides clocks to the transmitter channel. In this design example, because channels 0 and 2 share the same CMU PLL, drive the pll_powerdown port o channel 0 and channel 2 in the ALTGX instance rom the same logic. Stratix IV Device Handbook Volume 3 November 2009 Altera Corporation

35 Chapter 2: Transceiver Design Flow Guide 2 35 Channels 0, 1, and 2 have separate rx_digitalreset, rx_analogreset, and tx_digitalreset signals. Figure 2 17 shows the interace between the three transceiver instances and the FPGA abric. Figure Transceiver FPGA Fabric Interace User Logic rx_reqlocked Reset Control Logic tx_digitalreset rx_digitalreset rx_analogreset ALTGX Instance Channel0 data processing logic Transmitter Side Logic 8B/10B encoder tx_datain Starting channel number = 0 reconig_romgxb[16:0] reconig_togxb[3:0] ALTGX_RECONFIG Instance Receiver Side Logic rx_patterndetect data processing logic 8B/10B decoder rx_syncstatus rx_dataout reconig_romgxb[16:0] Reset Control or CMU PLL pll_locked pll_powerdown reconig_romgxb[50:34] reconig_romgxb[33:17] Reset Control Logic tx_digitalreset ALTGX Instance Channel 2 reconig_romgxb[16:0] reconig_togxb[3:0] data processing logic Transmitter Side Logic 8B/10B encoder tx_datain Starting channel number = 8 Reset Control Logic pll_powerdown pll_locked rx_reqlocked tx_digitalreset rx_digitalreset rx_analogreset ALTGX Instance Channel 1 reconig_togxb[3:0] reconig_romgxb[16:0] data processing logic Transmitter Side Logic 8B/10B encoder tx_datain data processing logic Receiver Side Logic 8B/10B decoder rx_patterndetect rx_syncstatus rx_dataout Starting channel number = 4