BeRadio SDR Lab & Demo

Transcription

1 BeRadio SDR Lab & Demo 1. Overview This lab demonstrates a rudimentary AM radio on the BeRadio Software Defined Radio (SDR) development board together with the BeMicroSDK FPGA-based MCU evaluation board. The radio receives the AM signal through a built-in antenna, converts it to a digital signal, filters and decodes it in the FPGA, and then plays the decoded audio through a headphone jack. You will build the AM radio and then experiment with some design features of the radio. 2. Getting Started This section ensures you have the right equipment to complete the lab and shows you how to install the software needed. The lab requires the following resources: BeRadio SDR development board BeMicroSDK FPGA-based MCU evaluation board PC running Quartus II web edition USB-Blaster device driver for the PC BeRadio Lab design and Quartus II project files Earbud headphones 2.1. BeRadio SDR Development Board The BeRadio SDR development board, shown in Figure 1, is a daughter card that plugs into the BeMicroSDK evaluation board via the 80-pin edge connector. Figure 1 BeRadio SDR Development Board Zephyr Engineering, Inc 1 Altera Corporation

2 As shown in Figure 2, the BeRadio consists of an analog filter preceding a Linear Technology LTC2225 analog-to-digital converter (ADC) plus a Linear Technology LTC1641 digital-to-analog converter (DAC). Filter (LTC6409) Filter (LTC6200) ADC (LTC2225) DAC (LTC2641) data control clock SPI control 80-pin Edge Connector Figure 2: BeRadio Block Diagram 2.2. BeMicroSDK Evaluation Board The BeMicro SDK evaluation board, pictured in Figure 3, is a low-cost development platform featuring an Altera Cyclone IV FPGA. The board also features DDR RAM, 10/100 ethernet, pushbuttons, DIP switches, LEDs, an 80-pin edge connector for attaching expansion boards, a micro-sd card socket, and a temperature sensor. It plugs into the USB port of a PC for power and communication for configuring the FPGA and programming the on-board EPCS16 FLASH memory. The block diagram is shown in Figure 4. Figure 3: BeMicroSDK FPGA-Based MCU Evaluation Board Zephyr Engineering, Inc 2 Altera Corporation

3 Figure 4: BeMicroSDK Block Diagram 2.3. Quartus II Web Edition Quartus II is the Altera synthesis and compilation tool used with Altera FPGAs. If Quartus II has not already been installed on your lab PC, follow these instructions to install it. Zephyr Engineering, Inc 3 Altera Corporation

4 1. Go to the Altera Download web page at Click the Download Windows Version button. 2. Login to your myaltera account. Use your existing login or fill out the Get One-Time Access form. 3. The Altera Installer executable should start downloading automatically. If not, follow the instructions on the page to download it manually. This could happen if you have your browser set to block pop-up windows. Zephyr Engineering, Inc 4 Altera Corporation

5 4. Run the Altera Installer and proceed to the Installer Setup page. Select the Download Installation Files from the Internet radio button and proceed to the Select Products page. Zephyr Engineering, Inc 5 Altera Corporation

6 5. For components to install, the only component you need is the Quartus II Software Web Edition; under the Device Families group, only Cyclone IV E needs to be selected. No other components or devices are required, although you may install them if you wish USB-Blaster Device Driver To install the USB-Blaster device driver, plug the BeMicroSDK board into a USB port on your PC. The PC will detect the new hardware and run the Found New Hardware Wizard to prompt for installation of the driver. Follow these instructions to install it on a Windows XP system: Zephyr Engineering, Inc 6 Altera Corporation

7 1. Select the Install from a list or specific location (Advanced) radio button and click Next. Zephyr Engineering, Inc 7 Altera Corporation

8 2. Select the Search for the best driver in these locations radio button and check the Include this location in the search checkbox. 3. Click the Browse button and navigate to <install_directory>\quartus\drivers\usb-blaster, where <install_directory> is the location you specified while installing Quartus II, and click Next. Zephyr Engineering, Inc 8 Altera Corporation

9 4. If you get a warning that the driver has not passed Windows logo testing, click Continue Anyway BeRadio Lab Files Download the BeRadio.zip ZIP archive from the web page to a folder on your PC. Extract the contents of the ZIP archive into a working directory. This will be your Quartus II project directory. Table 1 lists the files contained in the ZIP archive. Zephyr Engineering, Inc 9 Altera Corporation

10 Table 1: BeRadio Lab File List File am_demod.v binary_to_bcd.v cos.hex digit_display.v freq_phase_cntrs.v lut_cos.v lut_sin.v nco.v output_fir.v output_fir_rom.hex output_fir_rom.v ram_2_port_rden.v sat_rnd.v sin.hex spi_if.v sqrt.qip sqrt.v sysclk_pll.ppf sysclk_pll.qip sysclk_pll.v udpsdr_hf0.cdf udpsdr_hf0.qpf udpsdr_hf0.qsf udpsdr_hf0.sdc udpsdr_hf0.stp udpsdr_hf0.v z_cic.v Description AM Demodulator design file Binary-to-BCD converter design file Memory contents of cosine LUT LED display controller design file Frequency and phase increment counters design file Cosine LUT design file (generated by MegaWizard) Sine LUT design file (generated by MegaWizard) NCO design file Output FIR filter design file Memory contents for coefficient ROM Output FIR coefficient ROM design file 2-port RAM design file Saturation/rounding function design file Memory contents of sine LUT SPI interface design file Square root Megafunction IP variation file (generated by MegaWizard) Square root Megafunction design file (generated by MegaWizard) PLL Megafunction Pin Planner ports file (generated by MegaWizard) PLL Megafunction IP variation file (generated by MegaWizard) PLL Megafunction design file (generated by MegaWizard) BeRadio SDR Quartus II Programmer Chain Description File BeRadio SDR Quartus II project file BeRadio SDR Quartus II settings file BeRadio SDR Synopsys design constraints file SignalTap file BeRadio SDR design file CIC filter design file 2.6. EarBud Headphones The BeRadio board has a headphone jack for playing audio. Plug a set of EarBud headphones into the jack so you can hear the output of your AM radio. 3. BeRadio SDR FPGA Design This section describes the BeRadio FPGA design and shows you how to compile the design and program the FPGA on the BeMicroSDK Verilog Design Files The BeRadio FPGA design is shown in Figure 5. The ADC provides samples at 10 Mega-samples per second (Msps). These samples are first mixed with cosine and sine waves generated by a numerically Zephyr Engineering, Inc 10 Altera Corporation

11 controlled oscillator (NCO); the frequency of the waveforms is determined by a phase increment that may be increased or decreased to tune the radio to different AM frequencies. The radio defaults to 550 khz and may be tuned up or down in 10 khz steps. ADC data cos, sin CIC 1 NCO (LPF) 10 Msps (one sample every clock) ksps (one sample every 25 clocks) CIC 2 (LPF) Demod 50 ksps (one sample every 200 clocks) FIR (LPF) SPI I/F DAC data Figure 5: BeRadio FPGA Design Block Diagram The output of the mixing operation is then down-sampled to 50 kilo-samples per second (ksps) using a pair of cascaded integrator-comb (CIC) filters. These filters are very efficient for large interpolation or decimation ratios; they also act as coarse low-pass filters (LPFs). The filter design included in the lab allows you to specify the decimation ratio and the number of integrator-comb stages. More stages means better performance but also means more resources used. The resources used increases by the Log base 2 of the decimation and by the square of the number of stages. As a trade-off, the BeRadio design uses two CIC filters, one with a high decimation ratio but fewer stages to get the sample rate down quickly and another with a low decimation rate but more stages to improve performance. The down-sampled signal is then demodulated. The AM radio waveform encodes information by modulating the amplitude of the signal; thus, we demodulate the signal by finding the amplitude of the received samples. The amplitude A is calculated by the equation component of the signal and Q is the quadrature component. A = I Q, where I is the in-phase The demodulated signal is then filtered using a low-pass FIR filter. This filter eliminates out-of-band noise. FIR filters are more effective at filtering the pass band than CIC filters. The resulting samples are then sent to the DAC by serially shifting the bits in each sample over a SPI bus interface Quartus II Settings The Quartus II Settings File (QSF) contains settings entered either manually or using the Assignments Editor or Pin Planner tools in Quartus II. For this project, the settings file specifies the design files, pin assignments, and pin properties. No edits are required in this file for this lab. Zephyr Engineering, Inc 11 Altera Corporation

12 3.3. Timing Constraints Project timing constraints are specified in the Synopsys Design Constraints (SDC) file. This file defines the clocks used in the design and specifies the delay on the I/O pins external to the FPGA. The BeRadio allows you to clock the ADC using either the on-board 10 MHz oscillator or a generated clock from the FPGA. The current design uses the on-board oscillator. Whichever clock source you choose, a copy of that clock is sent back to the FPGA to be used as a sample clock. The design also defines the clock output for the DAC SPI interface. Thus, the SDC file defines six (6) clocks total: clk50: The original 50 MHz input clock from the BeMicro adc_clk_in: The 10 MHz output clock generated by a PLL going to the BeRadio (currently not used) adc_clk: 10 MHz virtual clock defined at the ADC clock input adc_clk_out: 10 MHz clock input from the BeRadio dac_sclk: 5 MHz clock generated for SPI interface, defined at the output of the register P26: 5 MHz SPI interface clock at the FPGA output port The input pins from the ADC are constrained by specifying all the delays external to the FPGA using the set_input_delay command. The TimeQuest timing analyzer will subtract these delays from the clock period to determine the maximum allowed setup and hold times on the inputs. The delays are as follows: Clock skew. Positive clock skew is defined as the delay from the FPGA clock input port to the ADC clock input pin. In this case there is an extra delay going to the FPGA clock input port so the clock skew is negative. Clock-to-output delay. This is the delay from the external clock edge to the output data being valid at the ADC pins. Trace delay. This is the delay from the ADC output data being valid on the ADC pins to their being valid on the FPGA pins. The maximum input delay is the sum of the maximum clock skew and clock-to-output and trace delays. The minimum input delay is the sum of the minimums of these same parameters. The clock is inverted at the input to the ADC; the virtual clock is not defined this way, so this inversion is accounted for by specifying that the ADC outputs are produced on the falling edge of the virtual clock. The output pins to the DAC are constrained by specifying all the delays external to the FPGA using the set_output_delay command. The TimeQuest timing analyzer will subtract these delays from the clock Zephyr Engineering, Inc 12 Altera Corporation

13 period to determine the maximum allowed clock-to-output times on the outputs. Since the SPI clock pin is the clock, it does not need to be constrained with regard to itself. The SPI data pin needs to be constrained with respect to the SPI clock pin. Since the SPI bus data and clock signal are generated from the internal ADC clock, and since the SPI bus clock is half the frequency of the ADC clock, the timing constraints may be relaxed. The SPI bus data are launched on the falling edge of the SPI bus clock and latched on the rising edge of the SPI bus clock. TimeQuest automatically considers the worst-case pairings of launch and latch clock edges. For the default setup time analysis, the latch clock is one ADC clock period after the launch clock; this is correct since the ADC clock edge that produced the data also produced the falling edge of the SPI clock and the following ADC clock produces the rising edge of the SPI clock. For the default hold time analysis, the launch and latch clock edges are the same. This scenario cannot happen since new data are launched on the ADC clock edge following the one that generated the previous SPI clock rising edge. Thus, a startmulticycle-hold constraint is added to reflect the more relaxed timing constraint. Output ports that are treated as asynchronous do not need to be analyzed by TimeQuest. For instance, some of the outputs going to the ADC configuration pins are fixed at a given value. Push-button inputs and LED outputs are inherently asynchronous. The set_false_path command removes these paths from the timing analysis. Also, the set_clock_groups command specifies groups of clocks such that clocks within a group are synchronous to one another but asynchronous to clocks in other groups; this implicitly removes any paths between clocks from different groups from the timing analysis Synthesis and Compilation Open Quartus II Web Edition and choose Open Project from the File pull-down menu. Navigate to the directory where you unzipped the design file archive and select the Quartus II Project File (udpsdr_hf0.qpf). This opens the AM radio project in Quartus II. Choose Start Compilation from the Processing pull-down menu to initiate synthesis and compilation (or click the maroon triangle in the toolbar, or press Ctrl-L). You will get up to ten (10) warnings that may be ignored: Analysis and Synthesis Warnings: o 20028: Parallel compilation is not licensed and has been disabled. The Web Edition of the Quartus II software does not support parallel processing; a licensed version of Quartus II will not produce this message. o 14284: Synthesized away the following node(s). Quartus II optimizes the design by removing logic that does not drive any subsequent logic. For instance, the FIR filter has two output channels but only one channel is used; the outputs for the second channel are not connected, so Quartus II optimizes away the logic for that channel. Zephyr Engineering, Inc 13 Altera Corporation

14 o 13024: Output pins are stuck at VCC or GND. Some of the control outputs are fixed at logic high or low, so this is normal. o 21074: Design contains 44 input pin(s) that do not drive logic. All of the pins going to the FPGA are defined in the project port list, but not all of them are used. Fitter Warnings: o 20028: Parallel compilation is not licensed and has been disabled. The Web Edition of the Quartus II software does not support parallel processing; a licensed version of Quartus II will not produce this message. Occurs three (3) times. o : Feature LogicLock is only available with a valid subscription license. The Web Edition of the Quartus II software does not support LogicLogic; a licensed version of Quartus II will not produce this message. o 15064: PLL... feeds output pin "P2~output" via non-dedicated routing. None of the dedicated PLL output ports are routed to the 80-pin expansion connector, so the output clock to the ADC must use non-dedicated routing. o : 69 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. This is just a reminder about proper termination of high-speed data lines and may be ignored. o : Following 24 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results. Some of the RAM interface ports are bi-directional and produce this warning when fixed to a given value. TimeQuest Warnings: o 20028: Parallel compilation is not licensed and has been disabled. The Web Edition of the Quartus II software does not support parallel processing; a licensed version of Quartus II will not produce this message. Occurs three (3) times Programming the BeMicro Follow these steps to program the image you just compiled into the Cyclone IV FPGA on the BeMicroSDK. 1. Make sure the BeRadio board is plugged into the 80-pin expansion connector on the BeMicroSDK board. 2. Plug the BeMicroSDK into a USB port on your PC. 3. Open the Quartus II Programmer by choosing Programmer from the Tools pull-down menu. Zephyr Engineering, Inc 14 Altera Corporation

15 4. If you don t see USB-Blaster next to the Hardware Setup button, click the button. Otherwise, skip to step 6. Zephyr Engineering, Inc 15 Altera Corporation

16 5. Double-click USB-Blaster and click Close. Zephyr Engineering, Inc 16 Altera Corporation

17 6. If no devices are listed in the window, click Auto Detect. Otherwise, skip to step 8. Zephyr Engineering, Inc 17 Altera Corporation

18 7. If no file is listed for the device, select the device and click Change File. Navigate to udpsdr_hf0.sof in your Quartus II project directory and click Open. Zephyr Engineering, Inc 18 Altera Corporation

19 8. Make sure the Program/Configure checkbox is checked and then click Start to program the device. 4. Operating the BeRadio SDR AM Radio Now that your BeMicroSDK is programmed with the AM radio design, LED1 should be flashing slowly; this is the heartbeat LED. Plug your earbud headphones into the headphone jack on the BeRadio SDR. The radio defaults to 550 khz; if there is a local station broadcasting at 550 khz, you should hear it now Tuning the Radio Check the position of SW1 DIP switch on the BeMicroSDK. If it s in the OFF position (the switch is on the side of the USB connector and LED3 is off), then pressing the User pushbutton on the BeMicroSDK tunes the radio to a frequency 10 khz higher. If SW1 is in the ON position (the switch is on the side of the 80- pin expansion connector and LED3 is on), then pressing the User pushbutton on the BeMicroSDK tunes the radio to a frequency 10 khz lower. Zephyr Engineering, Inc 19 Altera Corporation

20 You will also notice that LEDs 5 through 7 start flashing when you change the frequency. The sequence of flashes indicates the current frequency. There is a slight delay before the start of the sequence so it won t start right away if you press the button multiple times. The sequence is timed using the heartbeat LED. When you release the push-button, all four LEDs flash on for half the duration of the heartbeat LED. Then, every time the heartbeat LED flashes on, one digit of the frequency is displayed on frequency LEDs. The digits are encoded in binary-coded decimal (BCD) and are displayed most significant digit first and least significant digit last. For instance, the first time you press the User push-button, the frequency will change to 560 khz, so the LEDs will display the digits 0, 5, 6, and 0 in order. After the final digit is displayed, all four LEDs flash on for half the duration of the heartbeat LED. Experiment with tuning up and down until you find some more AM radio stations. To return to the default frequency of 550 khz, press the Reset push-button on the BeMicroSDK. Increasing the frequency above 1700 khz causes the BeRadio to roll over to 500 khz; decreasing the frequency below 500 khz causes the BeRadio to roll over to 1700 khz. Note: If you accidentally press the RECFG button, the FPGA will be re-configured with data from the onboard PROM. Repeat step 8 in section 3.5 to re-program with the BeRadio design Improving the Reception With the radio tuned to a strong local station, try moving your hand close to the antenna on the BeRadio board. Try touching the antenna with your finger. Does the audio get louder? Does it sound clearer? Experiment with various ways of changing the size and geometry of the antenna and note the change in the audio. A better antenna results in a stronger signal; a stronger signal results in louder, clearer audio. Keep an eye on LED 2 on the BeMicroSDK. This LED is attached to the overflow bit from the ADC; the LED comes on when the analog signal is too strong and overflows the digital output. This will cause distortion in your audio SignalTap Open the SignalTap file for the project by going to the Files tab in the Project Navigator window in Quartus II and double-clicking the udpsdr_hf0.stp file. Click the Run Analysis button (or press F5) and look at the waveforms for z_nco:z_nco_inst fcos and z_nco:z_nco_inst fsin. Select these two waveforms and, on the right-mouse-button menu, select Bus Display Format? Signed Line Chart. These signals should look like cosine and sine waves. Now press the User pushbutton on the BeMicroSDK a few times and run the analysis again; how did the cosine and sine waves change? Also, look at how the waveforms on the bottom of the SignalTap screen don t change value as often as the waveforms at the top. This is because of the decimation done in the CIC filters. The outputs of the first CIC filter (z_cic:z_cic1_inst out1_data and z_cic:z_cic1_inst out2_data) change only once for every 25 changes to i_data and q_data; the outputs of the second CIC filter (z_cic:z_cic2_inst out1_data and z_cic:z_cic2_inst out2_data) change only once for every 8 changes to the first CIC output. Zephyr Engineering, Inc 20 Altera Corporation

21 Now zero in on the signals at the very bottom of the SignalTap window. This is where data are shifted out to the DAC using the SPI bus. Observe that for every output of the FIR filter (output_fir:output_fir_inst strobe_out high), the ch1_out value of the FIR is transferred to shifter and then shifted out through spi_if:spi_if_inst shifter(15), which is the SPI data pin Changing the Default Channel Open the top-level design file udpsdr_hf0.v and search for Default frequency (line 214): parameter START_FREQ_KHZ = 550; // Default frequency at reset or power-up This is the line that defines the default starting frequency, which you can customize for your current location. Pick the frequency of a strong local station (or get one from the instructor) and replace the value 550 with your chosen frequency. Then, repeat the steps above for synthesis, compilation, and programming (Hint: you may want to make a copy of the existing udpsdr_hf0.sof file before compiling so you can switch back and forth between old and new images. Be sure to give the copy a meaningful name so you know what the difference is. It s a good idea to do this before every new compile). When you program your new image into the FPGA, does the radio start out tuned to your local station? 4.5. Changing the Number of CIC Filter Stages Now let s try changing the characteristics of the radio. Recall from the CIC filter section that the performance of the CIC filters and the resources used by them depends on the number of stages. Experiment with changing the number of CIC filter stages and see how that affects the resources used by the filter. We can see the resources used by each component by looking in the Compilation Report; if the report isn t already up, you may see it by pressing Ctrl-R. In the report, look under Fitter? Resource Section? Resource Utilization by Entity. There are two CIC filter components: z_cic:z_cic1_inst z_cic:z_cic2_inst Note that the CIC filters show resources used in the Logic Cells column but not the M9Ks or DSP Elements columns. Write down the number of cells used by each filter. Now go back to the top-level design file (udpsdr_hf0.v). Search for Decimation and Filtering, which takes you to the section of the design where the CIC filters are instantiated (line 517). Each instantiation specifies the number of stages to implement using the N_STAGES parameter. In Verilog, parameters are passed to components in a list indicated by the pound (#) symbol, such as in this instantiation of the first CIC filter starting on line 551: Zephyr Engineering, Inc 21 Altera Corporation

22 z_cic #(.IN_SIZE (22),.OUT_SIZE (23),.N_STAGES (5),.DEC_RATE (25) ) z_cic1_inst (.clk (adc_clk_out),.reset_n (reset_n),.instrobe (1'b1),.in1_data (cic_in_i),.in2_data (cic_in_q),.outstrobe (cic1_strb),.out1_data (cic1_i),.out2_data (cic1_q)); You can see from the bold text that this instantiation specifies a 5-stage filter. The second CIC filter has fourteen (14) stages. Notice from the numbers you found in the Fitter Report that the filter with 14 stages uses a lot more resources than the one with 5 stages. Experiment with changing the number of stages in each filter by changing the values in parentheses for N_STAGES. Synthesize, compile, and program as before; don t forget to make a copy of udpsdr_hf0.sof. How does it affect the resource usage? How does it affect the sound quality? 4.6. Changing the DAC Sample Rate The DAC sample rate is determined by the decimation factors in the CIC filters; each filter creates a strobe when its output is valid and this strobe triggers the following logic. Changing the decimation rate changes the rate at which output samples are produced. The decimation rate of each CIC filter may be changed by changing the value in the parentheses for the DEC_RATE parameter, as shown by the bold text here: z_cic #(.IN_SIZE (22),.OUT_SIZE (23),.N_STAGES (5),.DEC_RATE (25) ) z_cic1_inst (.clk (adc_clk_out),.reset_n (reset_n),.instrobe (1'b1),.in1_data (cic_in_i),.in2_data (cic_in_q),.outstrobe (cic1_strb),.out1_data (cic1_i),.out2_data (cic1_q)); Zephyr Engineering, Inc 22 Altera Corporation

23 Currently, the first filter decimates by 25 and the second by 8. The first filter inputs a new sample on every clock cycle; thus, the second filter inputs a new sample once every 25 clock cycles and outputs a new sample every 200 clock cycles. The FIR filter requires 133 clock cycles to process each output sample, so the overall CIC filter decimation rate cannot be lower than 133. If you change the decimation rate of the second filter to 6, then the overall decimation rate is 6 x 25 = 150 as shown in Figure 6, so the FIR filter still has time to work. Changing the value to 5 results in an overall decimation rate of 125, so that would not work. 10 Msps 400 ksps 50 ksps One sample every clock 25 One sample 8 every 25 clocks One sample every 200 clocks 10 Msps 400 ksps 66.7 ksps One sample every clock 25 One sample 6 every 25 clocks One sample every 150 clocks 10 Msps 400 ksps 80 ksps One sample every clock 25 One sample 5 every 25 clocks One sample every 125 clocks Figure 6: Sample Decimation Illustration Experiment with changing the decimation rate of each CIC filter, taking care to keep the overall decimation rate above 133. Again, simply change the values in parentheses for DEC_RATE, synthesize, compile, and program. How does the resource usage change with decimation rate? How does it affect the sound quality? Zephyr Engineering, Inc 23 Altera Corporation

24 4.7. Changing Bit Selections One of the most difficult decisions to make in digital design is choosing which bits to keep and which to throw away. Simply adding two 16-bit values together produces a 17-bit output; multiplying two 16- values produces a 32-bit output. If you don t start throwing away bits, your data paths will quickly grow to unmanageable sizes. When you decide to discard bits, you then have to decide which bits to discard. You can either discard bits on the right (the least significant bits, or LSBs) or bits on the left (the most significant bits, or MSBs). Dropping LSBs sacrifices precision and dropping MSBs sacrifices dynamic range. Dropping too many of either causes distortion. In the BeRadio FPGA design, the sat_rnd component is used to drop bits. To mitigate the distortion, rounding is performed when dropping LSBs and saturation is performed when dropping MSBs. The component has three parameters: the number of bits in the input (IN_SIZE), the number of LSBs to discard (TRUNC_SIZE), and the number of bits to keep in the output (OUT_SIZE). The difference between IN_SIZE and the sum of TRUNC_SIZE and OUT_SIZE is the number of MSBs to discard. As with the CIC filter, the parameters are passed to the component at instantiation. For instance, the 12- bit data coming from the ADC are multiplied by 16-bit cosine and sine values from the NCO to produce a 28-bit output. The first CIC filter has only a 22-bit input, so we need to discard six (6) bits. Currently, five LSBs and one MSB are dropped. This is shown by the bold text in this example instantiation of sat_rnd on line 540 of the top-level design file: sat_rnd #(.IN_SIZE (28),.TRUNC_SIZE (5),.OUT_SIZE (22) ) sat_rnd_cic_inst (.d1 (i_data),.d2 (q_data),.q1 (cic_in_i),.q2 (cic_in_q)); Try dropping more MSBs and fewer LSBs by changing the TRUNC_SIZE values. Synthesize, compile, and program as before. What happens to your AM radio signal? Experiment with changing the antenna size and geometry by touching it as before; is there more or less distortion than before? 4.8. Advanced Activities There are many ways to change the behavior of the radio. Here are some activities for the more advanced user. Zephyr Engineering, Inc 24 Altera Corporation

25 1. Try instantiating two different combinations of CIC filters at the same time. Use the RECONFIG_SW2 input to switch between the two combinations in real time. This way you can compare the results directly without having to reprogram or recompile. You ll have to create some intermediate signals to do the multiplexing. 2. Try removing the FIR filter and see how that affects the sound quality. Again, you can use RECONFIG_SW2 to multiplex the FIR output with the FIR input so you can compare the results directly. The FIR filter uses M9K RAM blocks and DSP elements as well as logic cells; how many does it use? How does it affect the sound quality? BeRadio SDR Lab & Demo - Rev 24 Oct 2012 Zephyr Engineering, Inc 25 Altera Corporation